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Journey Back to 1981: David Patterson Recounts the Birth of RISC and Its Legacy in RISC-V

Journey Back to 1981: David Patterson Recounts the Birth of RISC and Its Legacy in RISC-V
by Daniel Nenni on 12-25-2025 at 10:00 am

RISC V Summit 2025 David Patterson

In a warmly received keynote at the RISC-V Summit, computer architecture legend David Patterson took the audience on a captivating trip back to 1981, using scanned versions of his original overhead transparencies to recount the birth of Reduced Instruction Set Computing (RISC) at UC Berkeley.

Patterson began with humor, noting… Read More


Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon

Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon
by Daniel Nenni on 12-21-2025 at 10:00 am

Google RISC V in Datacenter 2025

In a engaging presentation at a recent RISC-V summit, Martin Dixon, Google’s Director of Data Center Performance Engineering, took the audience on a metaphorical “road trip” to explore the company’s vision for integrating RISC-V into its massive warehouse-scale computing infrastructure. Drawing… Read More


Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development

Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development
by Daniel Nenni on 12-21-2025 at 6:00 am

AWS RISC V Summit 2025 SemiWiki

In a compelling keynote at the RISC-V Summit North America 2025, Jeremy Dahan from AWS explored the challenges of embedded systems development and how cloud technologies can bridge the gap between local hardware tinkering and scalable, shareable environments. Drawing from his experience as an engineer, Dahan highlighted … Read More


The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role
by Daniel Nenni on 10-09-2025 at 8:00 am

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RISC-V  has emerged as a cornerstone of modern computing, offering an open-source alternative to proprietary designs like ARM and x86. Free from licensing fees and highly extensible, RISC-V powers everything from IoT devices to AI accelerators, with over 13 billion cores shipped globally. Annual RISC-V Summits, organized… Read More


Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo

Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo
by Daniel Nenni on 10-03-2025 at 10:00 am

Daniel is joined by Andrea Gallo, CEO of RISC-V International. Before joining RISC-V he worked in leadership roles at Linaro for over a decade and before Linaro he was a fellow at STMicroelectronics.

Dan explores the current state of the RISC-V movement with Andrea, who describes the focus and history of this evolving standard.… Read More


Yuning Liang’s Painstaking Push to Make the RISC-V PC a Reality

Yuning Liang’s Painstaking Push to Make the RISC-V PC a Reality
by Jonah McLeod on 09-24-2025 at 10:00 am

Embedded World Germany

At Embedded World 2025 in Nuremberg, Germany, on March 11, 2025, Yuning Liang, DeepComputing Founder and CEO walked onto the stage with a mischievous smile and a challenge. “What’s the hardest product to make?” he asked rhetorically. “A laptop. It’s bloody hard… but we did it. You can swap the motherboard, you can upgrade, you can’t… Read More


SiFive Launches Second-Generation Intelligence Family of RISC-V Cores

SiFive Launches Second-Generation Intelligence Family of RISC-V Cores
by Kalar Rajendiran on 09-18-2025 at 6:00 am

SiFive 2nd Gen Intelligence Family

SiFive, founded by the original creators of the RISC-V instruction set, has become the leading independent supplier of RISC-V processor IP. More than two billion devices already incorporate SiFive designs, ranging from camera controllers and SSDs to smartphones and automotive systems. The company no longer sells its own chips,… Read More


Beyond Von Neumann: Toward a Unified Deterministic Architecture

Beyond Von Neumann: Toward a Unified Deterministic Architecture
by Admin on 09-04-2025 at 6:00 am

Beyond Von Neumann

By Thang Tran

For more than half a century, the foundations of computing have stood on a single architecture: the Von Neumann or Harvard model. Nearly all modern chips—CPUs, GPUs, and even many specialized accelerators—rely on some variant of this design. Over time, the industry has layered on complexity and specialization to… Read More


Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs

Beyond Traditional OOO: A Time-Based, Slice-Based Approach to High-Performance RISC-V CPUs
by Kalar Rajendiran on 09-01-2025 at 10:00 am

Hot Chips Logo 2025

For decades, high-performance CPU design has been dominated by traditional out-of-order (OOO) execution architectures. Giants like Intel, Arm, and AMD have refined this approach into an industry standard—balancing performance and complexity through increasingly sophisticated schedulers, speculation, and runtime … Read More


Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo

Basilisk at Hot Chips 2025 Presented Ominous Challenge to IP/EDA Status Quo
by Jonah McLeod on 08-31-2025 at 10:00 am

Hot Chips Logo 2025

At Hot Chips 2025, Philippe Sauter of ETH Zürich presented Basilisk, a project that may redefine what’s possible with open-source hardware. Basilisk is a 34 mm² RISC-V SoC fabricated at IHP Microelectronics on its open-source 130nm BiCMOS process in Germany. Basilisk, named after the Greco-Roman mythical creature known… Read More