WP_Term Object
(
    [term_id] => 51
    [name] => RISC-V
    [slug] => risc-v
    [term_group] => 0
    [term_taxonomy_id] => 51
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 156
    [filter] => raw
    [cat_ID] => 51
    [category_count] => 156
    [category_description] => 
    [cat_name] => RISC-V
    [category_nicename] => risc-v
    [category_parent] => 178
    [is_post] => 
)
            
SemiWiki Podcast Banner
WP_Term Object
(
    [term_id] => 51
    [name] => RISC-V
    [slug] => risc-v
    [term_group] => 0
    [term_taxonomy_id] => 51
    [taxonomy] => category
    [description] => 
    [parent] => 178
    [count] => 156
    [filter] => raw
    [cat_ID] => 51
    [category_count] => 156
    [category_description] => 
    [cat_name] => RISC-V
    [category_nicename] => risc-v
    [category_parent] => 178
    [is_post] => 
)

SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion

SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion
by Daniel Nenni on 01-26-2026 at 10:00 am

SiFive Data Center Nvidia NVLink Fusion

In a strategic move that could reshape the future of AI data center design, SiFive, a leading developer of RISC-V processor IP and compute subsystems, has announced plans to integrate NVIDIA’s NVLink Fusion interconnect technology into its high-performance data center platforms. This collaboration bridges the open-architecture… Read More


Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
by Daniel Nenni on 01-20-2026 at 6:00 am

Pushing the Packed SIMD Extension Over the Line Andes RISCV Summit

The rapid growth of signal processing workloads in embedded, mobile, and edge computing systems has intensified the need for efficient, low-latency computation. Rich Fuhler’s update on the RISC-V Packed SIMD extension highlights why scalar SIMD digital signal processing (DSP) instructions are becoming a critical architectural… Read More


2026 Outlook with Volker Politz of Semidynamics

2026 Outlook with Volker Politz of Semidynamics
by Daniel Nenni on 01-08-2026 at 10:00 am

Volker Politz Semidynamics

Tell us a little bit about yourself and your company.
I am the Chief Sales Officer for Semidynamics and I lead the global sales team and drive the overall sales process.

Semidynamics was founded in 2016 as a design service company with a focus on RISC-V. This was so successful that the CEO decided to pivot the company towards its own … Read More


CEO Interview with Rabin Sugumar of Akeana

CEO Interview with Rabin Sugumar of Akeana
by Daniel Nenni on 01-06-2026 at 10:00 am

unnamed (5)

Rabin Sugumar was Distinguished Engineer and Chief Architect at Marvell/Cavium and built and led the architecture group for the ThunderX Arm server processor line. Most recently he led the architecture of the ThunderX3 processor, which had industry leading single thread performance and socket level performance at time of … Read More


RISC-V: Powering the Era of Intelligent General Computing

RISC-V: Powering the Era of Intelligent General Computing
by Daniel Nenni on 12-29-2025 at 8:00 am

Andes RISC V Summit 2025 Charlie Su

Charlie Su, President and CTO of Andes Technology, delivered a compelling keynote at the 2025 RISC-V Summit North America, asserting that RISC-V is primed to drive the burgeoning field of Intelligent General Computing. This emerging paradigm integrates AI and machine learning into everyday computing devices, from AI-enabled… Read More


Journey Back to 1981: David Patterson Recounts the Birth of RISC and Its Legacy in RISC-V

Journey Back to 1981: David Patterson Recounts the Birth of RISC and Its Legacy in RISC-V
by Daniel Nenni on 12-25-2025 at 10:00 am

RISC V Summit 2025 David Patterson

In a warmly received keynote at the RISC-V Summit, computer architecture legend David Patterson took the audience on a captivating trip back to 1981, using scanned versions of his original overhead transparencies to recount the birth of Reduced Instruction Set Computing (RISC) at UC Berkeley.

Patterson began with humor, noting… Read More


Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon

Google’s Road Trip to RISC-V at Warehouse Scale: Insights from Google’s Martin Dixon
by Daniel Nenni on 12-21-2025 at 10:00 am

Google RISC V in Datacenter 2025

In an engaging presentation at a recent RISC-V summit, Martin Dixon, Google’s Director of Data Center Performance Engineering, took the audience on a metaphorical “road trip” to explore the company’s vision for integrating RISC-V into its massive warehouse-scale computing infrastructure. Drawing… Read More


Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development

Bridging Embedded and Cloud Worlds: AWS Solutions for RISC-V Development
by Daniel Nenni on 12-21-2025 at 6:00 am

AWS RISC V Summit 2025 SemiWiki

In a compelling keynote at the RISC-V Summit North America 2025, Jeremy Dahan from AWS explored the challenges of embedded systems development and how cloud technologies can bridge the gap between local hardware tinkering and scalable, shareable environments. Drawing from his experience as an engineer, Dahan highlighted … Read More


The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role

The RISC-V Revolution: Insights from the 2025 Summits and Andes Technology’s Pivotal Role
by Daniel Nenni on 10-09-2025 at 8:00 am

block ad (2)

RISC-V  has emerged as a cornerstone of modern computing, offering an open-source alternative to proprietary designs like ARM and x86. Free from licensing fees and highly extensible, RISC-V powers everything from IoT devices to AI accelerators, with over 13 billion cores shipped globally. Annual RISC-V Summits, organized… Read More


Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo

Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo
by Daniel Nenni on 10-03-2025 at 10:00 am

Daniel is joined by Andrea Gallo, CEO of RISC-V International. Before joining RISC-V he worked in leadership roles at Linaro for over a decade and before Linaro he was a fellow at STMicroelectronics.

Dan explores the current state of the RISC-V movement with Andrea, who describes the focus and history of this evolving standard.… Read More