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WEBINAR: How to Achieve 95%+ Accurate Power Measurement During Architecture Exploration

WEBINAR: How to Achieve 95%+ Accurate Power Measurement During Architecture Exploration
by Daniel Nenni on 11-01-2023 at 6:00 am

AVFS IP SOC

Today’s power modeling solutions are trained at measuring power using the micro-events captured from detailed RTL simulation or studying the electromagnetic radiation from IR drop and side channel attacks. These solutions are fantastic for debugging and verification of the implementation. There are both open source and … Read More


Podcast EP190: The Growth and Impact of RISC-V and a Peek at the Upcoming RISC-V Summit with Calista Redmond

Podcast EP190: The Growth and Impact of RISC-V and a Peek at the Upcoming RISC-V Summit with Calista Redmond
by Daniel Nenni on 10-27-2023 at 10:00 am

Dan is joined by Calista Redmond, CEO of RISC-V International. Prior to RISC-V International, Calista held a variety of roles at IBM, including vice president of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement… Read More


CEO Interview: Venkata Simhadri of MosChip

CEO Interview: Venkata Simhadri of MosChip
by Daniel Nenni on 10-27-2023 at 6:00 am

Venkata Simhadri

Mr. Venkata Sudhakar Simhadri is a serial entrepreneur with a proven track-record in the semiconductor industry. He was the Founder, President & CEO of Gigacom Semiconductor LLC & Founder / Director of Gigacom India (Both the Companies acquired by MosChip) and the driving force behind establishing IP licensing and … Read More


100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers

100G/200G Electro-Optical Interfaces: The Future for Low Power, Low Latency Data Centers
by Kalar Rajendiran on 10-23-2023 at 6:00 am

112G Ethernet PHY IP EOE InterOp Demo JR5 0179

Electrical copper interconnects, once the backbone of data center networks, are facing growing challenges. Rapid expansion of AI and ML applications is driving a significant increase in cluster sizes within data centers, resulting in substantial demands for faster I/O capabilities. While the surge in I/O requirements is … Read More


Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors

Analog Bits Leads the Way at TSMC OIP with High-Accuracy Sensors
by Mike Gianfagna on 10-18-2023 at 6:00 am

Analog Bits Leads the Way at TSMC OIP with High Accuracy Sensors

The 15th TSMC Open Innovation Platform® (OIP) event was held recently. This event is a focal point across the industry for cutting-edge development and industry-level collaboration. Appropriately, advanced packaging, paving the way for multi-die design was a focal point for the event. You can get a good overview of what was Read More


TSMC N3E is ready for designs, thanks to IP from Synopsys

TSMC N3E is ready for designs, thanks to IP from Synopsys
by Daniel Payne on 10-12-2023 at 10:00 am

synopsys ucie phy ip min

TSMC has been offering foundry services since 1987, and their first 3nm node was called N3 and debuted in 2022; now they have an enhanced 3nm node dubbed N3E that has launched.  Every new node then requires IP that is carefully designed, characterized and validated in silicon to ensure that the IP specifications are being met and … Read More


Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem

Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem
by Kalar Rajendiran on 10-10-2023 at 10:00 am

L.C. OIP 2023

As the focal point of the TSMC OIP ecosystem, TSMC has been driving important initiatives over the last few years to bring multi-die systems to the mainstream. As the world is moving quickly toward Generative AI technology and AI-based systems, multi-die and chiplet-based implementations are becoming essential. TSMC recently… Read More


Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design

Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design
by Kalar Rajendiran on 10-10-2023 at 6:00 am

AresCORE UCIe PHY Support for All Package Types

The world of computing is evolving rapidly, with a constant demand for more powerful and efficient systems. Generative AI has driven exponential growth in the amount of data that is generated and processed at very high data speeds and very low latencies. Traditionally, computing systems have been built using monolithic designs,… Read More


Pairing RISC-V cores with NoCs ties SoC protocols together

Pairing RISC-V cores with NoCs ties SoC protocols together
by Don Dingee on 10-05-2023 at 6:00 am

An architecture pairing RISC-V cores with NoCs

Designers have many paths for differentiating RISC-V solutions. One path launches into various RISC-V core customizations and extensions per the specification. Another focuses on selecting and assembling IP blocks in a complete system-on-chip (SoC) design around one or more RISC-V cores. A third is emerging: interconnecting… Read More


Transformers Transforming the Field of Computer Vision

Transformers Transforming the Field of Computer Vision
by Kalar Rajendiran on 10-03-2023 at 10:00 am

The Structure of a Transformer: Attention

Over the last few years, transformers have been fundamentally changing the nature of deep learning models, revolutionizing the field of artificial intelligence. Transformers introduce an attention mechanism that allows models to weigh the importance of different elements in an input sequence. Unlike traditional deep learning… Read More