wide 1
WP_Term Object
(
    [term_id] => 178
    [name] => IP
    [slug] => ip
    [term_group] => 0
    [term_taxonomy_id] => 178
    [taxonomy] => category
    [description] => Semiconductor Intellectual Property
    [parent] => 0
    [count] => 1866
    [filter] => raw
    [cat_ID] => 178
    [category_count] => 1866
    [category_description] => Semiconductor Intellectual Property
    [cat_name] => IP
    [category_nicename] => ip
    [category_parent] => 0
    [is_post] => 
)

Podcast EP291: The Journey From One Micron to Edge AI at One Nanometer with Ceva’s Moshe Sheier

Podcast EP291: The Journey From One Micron to Edge AI at One Nanometer with Ceva’s Moshe Sheier
by Daniel Nenni on 06-13-2025 at 10:00 am

Dan is joined by Moshe Sheier, Ceva’s vice president of marketing. Moshe brings with him more than 20 years of experience in the semiconductor IP and chip industries in both development and managerial roles. Prior to this position, Mr. Sheier was the director of strategic marketing at Ceva.

Dan explores the history of Ceva with … Read More


CEO Interview with Krishna Anne of Agile Analog

CEO Interview with Krishna Anne of Agile Analog
by Daniel Nenni on 06-13-2025 at 6:00 am

Agile Analog Krishna Anne headshot photo

Krishna has over 30 years of expertise in the semiconductor industry, holding senior roles at Rambus, AMD and Broadcom. As a serial entrepreneur, he co-founded SCI Semi Ltd and previously established DataTrails and Secure Thingz.

 Tell us a bit about your career background. What are you most proud of?

Over the course of my 30 year… Read More


Legacy IP Providers Struggle to Solve the NPU Dilemna

Legacy IP Providers Struggle to Solve the NPU Dilemna
by Admin on 06-11-2025 at 10:00 am

Fracture the IO Network

At Quadric we do a lot of first-time introductory visits with prospective new customers.  As a rapidly expanding processor IP licensing company that is starting to get noticed (even winning IP Product of the Year!) such meetings are part of the territory.  Which means we hear a lot of similar sounding questions from appropriately… Read More


Mixel at the 2025 Design Automation Conference #62DAC

Mixel at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-10-2025 at 10:00 am

62nd DAC SemiWiki

Mixel, Inc., a leading provider of mixed-signal interface IP, will exhibit at booth #2616 at Design Automation Conference (DAC) 2025 on June 23-25. The company will demonstrate its latest customer demos featuring Mixel’s MIPI PHY IP and LVDS IP. Mixel’s customers include many of the world’s largest semiconductors and system… Read More


Analog Bits at the 2025 Design Automation Conference #62DAC

Analog Bits at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-10-2025 at 6:00 am

Analog Bits at the 2025 Design Automation Conference

Analog Bits attends a lot of events. I know because I see them a lot in my travels. Lately, the company has been stealing the show with cutting-edge analog IP on a broad range of popular nodes and a strategy that will change the way design is done. Analog Bits is quietly rolling out a new approach to system design. One that delivers a holistic… Read More


Arm Reveals Zena Automotive Compute Subsystem

Arm Reveals Zena Automotive Compute Subsystem
by Bernard Murphy on 06-05-2025 at 6:00 am

Zena CSS min

Last year Arm announced their support for standards-based virtual prototyping in automotive, along with a portfolio of new AE (automotive enhanced) cores. They also suggested that in 2025 they would be following Arm directions in other LOBs by offering integrated compute subsystems (CSS). Now they have delivered: their Zena… Read More


Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination

Relaxation-Aware Programming in ReRAM: Evaluating and Optimizing Write Termination
by Admin on 06-03-2025 at 6:00 am

Im1 Weebit Relaxation Aware Programming in ReRAM Optimizing Write Termination RRAM 1024x704

Resistive RAM (ReRAM or RRAM) is the strongest candidate for next-generation non-volatile memory (NVM), combining fast switching speeds with low power consumption. New techniques for managing a memory phenomenon called ‘relaxation’ are making ReRAM more predictable — and easier to specify for real-world applications.… Read More


Breker Verification Systems at the 2025 Design Automation Conference #62DAC

Breker Verification Systems at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-02-2025 at 10:00 am

62nd DAC SemiWiki

Breker Verification Systems Plans Demonstrations of its Complete Synthesis and SystemVIP Library and Solutions Portfolio

Attendees who step into the Breker Verification Systems booth during DAC (Booth #2520—second floor) will see demonstrations of its Trek Test Suite Synthesis and SystemVIP libraries and solutions portfolio.… Read More


Synopsys Addresses the Test Barrier for Heterogeneous Integration

Synopsys Addresses the Test Barrier for Heterogeneous Integration
by Mike Gianfagna on 05-29-2025 at 10:00 am

Synopsys Addresses the Test Barrier for Heterogeneous Integration

The trend is clear, AI and HPC is moving to chiplet-based, or heterogenous design to achieve the highest levels of performance, while traditional monolithic system-on-chip (SoC) designs struggle to scale. What is also clear is the road to this new design style is not a smooth one. There are many challenges to overcome. Some are … Read More


Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000

Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000
by Bernard Murphy on 05-29-2025 at 6:00 am

Anirudh Keynote at CadenceLIVE 2025 Reveals Millennium M2000

Another content-rich kickoff covering a lot of bases under three main themes: the new Millennium AI supercomputer release, a moonshot towards full autonomy in chip design exploiting agentic AI, and a growing emphasis on digital twins. Cadence President and CEO Anirudh Devgan touched on what is new today, and also market directions… Read More