SILVACO 051525 Webinar 800x100 v2
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A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips

A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips
by Mike Gianfagna on 04-03-2025 at 10:00 am

A Synopsys Webinar Detailing IP Requirements for Advanced AI Chips

Generative AI is dramatically changing the compute power that must be delivered by advanced designs. This demand has risen by more than 10,000 times in the past five to six years.  This increased demand has impacted the entire SoC design flow. We are now faced with going beyond 1 trillion transistors per chip, and systems now consist… Read More


Evolution of Memory Test and Repair: From Silicon Design to AI-Driven Architectures

Evolution of Memory Test and Repair: From Silicon Design to AI-Driven Architectures
by Kalar Rajendiran on 04-01-2025 at 6:00 am

STAR Memory System (SMS) Solution

Memory testing in the early days of computing was a relatively straightforward process. Designers relied on simple, deterministic approaches to verify the functionality of memory modules. However, as memory density increased and systems became more complex, the likelihood of faults also rose. With advancements in memory… Read More


Vision-Language Models (VLM) – the next big thing in AI?

Vision-Language Models (VLM) – the next big thing in AI?
by Daniel Nenni on 03-27-2025 at 6:00 am

Semidynamics AI SemiWiki

AI has changed a lot in the last ten years. In 2012, convolutional neural networks (CNNs) were the state of the art for computer vision. Then around 2020 vison transformers (ViTs) redefined machine learning. Now, Vision-Language Models (VLMs) are changing the game again—blending image and text understanding to power everything… Read More


Ceva-XC21 and Ceva-XC23 DSPs: Advancing Wireless and Edge AI Processing

Ceva-XC21 and Ceva-XC23 DSPs: Advancing Wireless and Edge AI Processing
by Kalar Rajendiran on 03-25-2025 at 6:00 am

Cellular Evolution

Ceva recently unveiled its XC21 and XC23 DSP cores, designed to revolutionize wireless communications and edge AI processing. These new offerings build upon the Ceva-XC20 architecture, delivering unmatched efficiency, scalability, and performance for 5G-Advanced, pre-6G, and smart edge applications. As demand grows … Read More


Cut Defects, Not Yield: Outlier Detection with ML Precision

Cut Defects, Not Yield: Outlier Detection with ML Precision
by Kalar Rajendiran on 03-20-2025 at 10:00 am

Part Average Testing

How much perfectly good silicon is being discarded in the quest for reliability? During high-volume chip manufacturing, aggressive testing with strict thresholds may ensure quality but reduces yield, discarding marginal chips that could function flawlessly. On the other hand, prioritizing yield risks allowing defective… Read More


CEO Interview with Dr. Thang Tran of Simplex Micro

CEO Interview with Dr. Thang Tran of Simplex Micro
by Daniel Nenni on 03-18-2025 at 10:00 am

ThangTran SimiWiki

Dr. Thang Tran is an innovator in modern computing, drawing inspiration from pioneers like Seymour Cray, Thornton, and Tomasulo. His work leverages the simplicity of the RISC-V ISA to advance microprocessor efficiency, integrating vector processing and scoreboarding principles foundational to early supercomputing. Thang… Read More


Semidynamics adds NoC partner and ONNX for RISC-V AI applications

Semidynamics adds NoC partner and ONNX for RISC-V AI applications
by Don Dingee on 03-18-2025 at 6:00 am

Baya x Semidynamics teaming up on RISC-V AI applications

When Semidynamics added support for int4 and fp8 data types to their RISC-V processors, it clearly indicated their intent to target AI inference with hundreds or perhaps thousands of concurrent threads running in their advanced caching and pipelining scheme. Two recent announcements around Embedded World 2025 reinforce their… Read More


RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs

RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs
by Jonah McLeod on 03-12-2025 at 6:00 am

Security Article Intro ART

Because of its open and modular nature, RISC-V has faced recognizable security challenges stemming from fragmentation, performance inefficiencies, and inherent vulnerabilities. Fragmentation across implementations leads to inconsistencies, making it difficult to enforce uniform security measures. Performance… Read More


S2C: Empowering Smarter Futures with Arm-Based Solutions

S2C: Empowering Smarter Futures with Arm-Based Solutions
by Daniel Nenni on 03-07-2025 at 8:00 am

S2c EDA ARM 2025

The tech world is sprinting toward a future where your fridge orders groceries, your car avoids traffic before you hit it, and security cameras don’t just watch—they understand. But behind these innovations lies a messy truth: building the brains for these smart systems is complicated.

Fresh off the 2024 Arm Tech Symposia… Read More


The Double-Edged Sword of AI Processors: Batch Sizes, Token Rates, and the Hardware Hurdles in Large Language Model Processing

The Double-Edged Sword of AI Processors: Batch Sizes, Token Rates, and the Hardware Hurdles in Large Language Model Processing
by Lauro Rizzatti on 02-27-2025 at 10:00 am

Accelerated,Computing, ,Parallel,Processing,To,Speed,Up,Work,On

Unlike traditional software programming, AI software modeling represents a transformative paradigm shift, reshaping methodologies, redefining execution processes, and driving significant advancements in AI processors requirements.

Software Programming versus AI Modeling: A Fundamental Paradigm Shift

TraditionalRead More