Last month, Lj Ristic delivered an invited talk on MEMS technology as a driving force at the Laser Display and Lighting Conference 2025, held at Trinity College Dublin. His talk included a review of some major successes of MEMS industry. We used that occasion to talk to him and discuss some major achievements and the status of MEMS… Read More
Semiconductor Intellectual Property
WEBINAR: Edge AI Optimization: How to Design Future-Proof Architectures for Next-Gen Intelligent Devices
Edge AI is rapidly transforming how intelligent solutions are designed, from smart home devices to autonomous vehicles, healthcare gadgets, and industrial IoT. Yet, architects, chip designers, and product managers frequently grapple with a common and daunting challenge: creating efficient, high-performance AI solutions… Read More
WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs
In today’s data-driven systems—from cloud storage and AI accelerators to automotive logging and edge computing—every byte counts. The exponential growth in data volumes, real-time processing demands, and constrained bandwidth has made efficient, lossless data compression a mission-critical requirement. Software-based… Read More
Siemens EDA Unveils Groundbreaking Tools to Simplify 3D IC Design and Analysis
In a major announcement at the 2025 Design Automation Conference (DAC), Siemens EDA introduced a significant expansion to its electronic design automation (EDA) portfolio, aimed at transforming how engineers design, validate, and manage the complexity of next-generation three-dimensional integrated circuits (3D ICs).… Read More
Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo
Dan is joined by Andrea Gallo, CEO of RISC-V International, the non-profit home of the RISC-V instruction set architecture standard, related specifications, and stakeholder community. Prior to joining RISC-V International, Gallo worked in leadership roles at Linaro for over a decade. He built Linaro’s server engineering… Read More
Flynn Was Right: How a 2003 Warning Foretold Today’s Architectural Pivot
In 2003, legendary computer architect Michael J. Flynn issued a warning that most of the industry wasn’t ready to hear. The relentless march toward more complex CPUs—with speculative execution, deep pipelines, and bloated instruction handling—was becoming unsustainable. In a paper titled “Computer Architecture … Read More
Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping System
Qualifying an AI-class RISC-V SoC demands proving that wide vectors, deep caches, and high-speed I/O operate flawlessly long before tape-out. At the recent Andes RISC-V Conference, Andes Technology and S2C showcased this by successfully booting a lightweight large language model (LLM) inference on a single S2C Prodigy™ S8-100… Read More
Arteris at the 2025 Design Automation Conference #62DAC
Key Takeaways:
- Expanded Multi-Die Solution: Arteris showcases its foundational technology for rapid chiplet-based innovation. Check out the multi-die highlights video.
- Ecosystem compatibility: Supported through integration with products from major EDA and foundry partners, including Cadence, Synopsys, and global
Arteris Expands Their Multi-Die Support
I am tracking the shift to multi-die design, so it’s good to see Arteris extend their NoC expertise, connecting chiplets across an interposer. After all, network connectivity needs don’t stop at the boundaries of chiplets. A multi-die package is at a logical level just a scaled-up SoC for which you still need traffic routing and… Read More
Agile Analog at the 2025 Design Automation Conference #26DAC
See Agile Analog at DAC in the EE Times Chiplet Pavilion (Booth 2308, Level 2)
Learn how to enhance security and performance with our customizable analog IP
Agile Analog is delighted to announce that we will be back exhibiting at the Design Automation Conference (DAC). Come join us in the EE Times Chiplet Pavilion (booth 2308) to … Read More
Can RISC-V Help Recast the DPU Race?