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Pairing RISC-V cores with NoCs ties SoC protocols together

Pairing RISC-V cores with NoCs ties SoC protocols together
by Don Dingee on 10-05-2023 at 6:00 am

An architecture pairing RISC-V cores with NoCs

Designers have many paths for differentiating RISC-V solutions. One path launches into various RISC-V core customizations and extensions per the specification. Another focuses on selecting and assembling IP blocks in a complete system-on-chip (SoC) design around one or more RISC-V cores. A third is emerging: interconnecting… Read More


Transformers Transforming the Field of Computer Vision

Transformers Transforming the Field of Computer Vision
by Kalar Rajendiran on 10-03-2023 at 10:00 am

The Structure of a Transformer: Attention

Over the last few years, transformers have been fundamentally changing the nature of deep learning models, revolutionizing the field of artificial intelligence. Transformers introduce an attention mechanism that allows models to weigh the importance of different elements in an input sequence. Unlike traditional deep learning… Read More


Fast Path to Baby Llama BringUp at the Edge

Fast Path to Baby Llama BringUp at the Edge
by Bernard Murphy on 09-26-2023 at 10:00 am

Baby Llama min

Tis the season for transformer-centric articles apparently – this is my third within a month. Clearly this is a domain with both great opportunities and challenges: extending large language model (LLM) potential to new edge products and revenue opportunities, with unbounded applications and volumes yet challenges in meeting… Read More


Cadence Tensilica Spins Next Upgrade to LX Architecture

Cadence Tensilica Spins Next Upgrade to LX Architecture
by Bernard Murphy on 09-21-2023 at 6:00 am

Xtensa LX8 processor

When considering SoC architectures it is easy to become trapped in simple narratives. These assume the center of compute revolves around a central core or core cluster, typically Arm, more recently perhaps a RISC-V option. Throw in an accelerator or two and the rest is detail. But for today’s competitive products that view is a … Read More


Hyperstone Webinar – There’s More to a Storage System Than Meets the Eye

Hyperstone Webinar – There’s More to a Storage System Than Meets the Eye
by Mike Gianfagna on 09-19-2023 at 10:00 am

Hyperstone Webinar There's More to a Storage System Than Meets the Eye

Founded in 1990, Hyperstone is a fabless NAND flash memory controller company enabling safe, reliable and secure storage systems. The company designs, develops and delivers high-quality, innovative semiconductor solutions to enable its customers to produce world-class products for industrial, embedded, automotive and… Read More


Inference Efficiency in Performance, Power, Area, Scalability

Inference Efficiency in Performance, Power, Area, Scalability
by Bernard Murphy on 09-19-2023 at 6:00 am

AI graphic

Support for AI at the edge has prompted a good deal of innovation in accelerators, initially in CNNs, evolving to DNNs and RNNs (convolutional neural nets, deep neural nets, and recurrent neural nets). Most recently, the transformer technology behind the craze in large language models is proving to have important relevance at… Read More


The TSMC OIP Backstory

The TSMC OIP Backstory
by Daniel Nenni on 09-18-2023 at 6:00 am

TSMC OIP 2023

This is the 15th anniversary of the TSMC Open Innovation Platform (OIP). The OIP Ecosystem Forum will kick off on September 27th in Santa Clara, California and continue around the world for the next two months in person and on-line in North America, Europe, China, Japan, Taiwan, and Israel. These are THE most attended semiconductor… Read More


CEO Interview: Koen Verhaege, CEO of Sofics

CEO Interview: Koen Verhaege, CEO of Sofics
by Daniel Nenni on 09-15-2023 at 6:00 am

CEO Interview Koen Verhaege, CEO of Sofics

Koen Verhaege, CEO of Sofics (“Solutions for ICs”), has developed his career first as an engineer, later as a business leader and entrepreneur, working on IP development and valorisation. Koen’s technical accomplishments, publications and patents are in the field of on-chip ESD protection design.

Today, Koen… Read More


Deeper RISC-V pipeline plows through vector-scalar loops

Deeper RISC-V pipeline plows through vector-scalar loops
by Don Dingee on 09-14-2023 at 10:00 am

Atrevido 423 + V16 Vector Unit with its deeper RISC-V pipeline technology, Gazillion

Many modern processor performance benchmarks rely on as many as three levels of cache staying continuously fed. Yet, new data-intensive applications like multithreaded generative AI and 4K image processing often break conventional caching, leaving the expensive execution units behind them stalled. A while back, Semidynamics… Read More


Successful Inter-Op Verification of Enterprise Flash Controller with ONFI 5.1 PHY IP

Successful Inter-Op Verification of Enterprise Flash Controller with ONFI 5.1 PHY IP
by Kalar Rajendiran on 09-14-2023 at 6:00 am

Mobiveil EFC

In an era defined by digital transformation and data-intensive applications, the solid-state device (SSD) market has emerged as a critical player in reshaping storage solutions. While there are several types of non-volatile memories, each with its own unique characteristics and use cases, Flash memory is increasingly overtaking… Read More