For all the raving and ranting and hand-wringing about the iPhone 5, the centerpiece of the device – the new A6 SoC – is proving to be a marvelous piece of engineering.… Read More
Hand-crafted for horsepower: Apple A6 SoC
Semiconductor Intellectual Property
Samsung going vertical Qualcomm cry CEVA laugh
These last days have been full of Apple related stories; maybe it’s time to discuss a new topic? Like for example Samsung, direct competitor for Apple in the smartphone market, and take a look at the company move toward more vertical integration. Everybody working in the SC industry knows that Samsung is ranked #2 behind Intel, even… Read More
iPhone 5: Boost to semiconductor market?
The release of Apple’s iPhone 5 has led to much speculation on its impact on the economy. An analyst at J.P. Morgan estimated the iPhone 5 could add $3.2 billion to U.S. GDP in the fourth quarter, adding ¼ to ½ point to the GDP growth rate.
Analysts’ estimates for total iPhone sales in 4Q 2012 are in the range of 46 million to 50 million units.… Read More
CEVA DSP Technology Symposium Series 2012
You are cordially invited to register to attend the CEVA DSP Technology Symposium Series 2012, which will take place in Taiwan, October 16th, China, October 18th and Israel, November 1st.
CEVA’s industry-leading experts and engineers will present a full day of lectures and seminars where you will learn about the latest technological… Read More
SAME 2012 Conference on October 2-3 in Sophia is coming soon!
This is the 15[SUP]th[/SUP] anniversary for the SAME Conference, dedicated to innovation on Microelectronics. Sophia-Antipolis is not only close to Mediterranean sea, but also at the heart of Telecom valley in south of France, with Texas Instruments design center dedicated to Application Processor design (OMAP), Cadence… Read More
Virtual Prototype your SoC including Arteris FlexNoC and optimize architecture using CPAK from Carbon
I have talked about Virtual Prototyping a SoC including FlexNoC Network on Chip IP from Arteris by using Carbon Design Systems set of tools in a previous post. A blog, posted on Carbon’ web, is clearly explaining the process to follow to optimize a fabric (FlexNoC) successively using the different tools from Carbon. Bill Neifert,… Read More
2nd International Workshop on Resistive RAM at Stanford
A Veritable who’s who of ReRAM researchers will be present at the 2nd International Workshop on Resistive RAM at Stanford in the beginning of October. Sponsored by IMEC and Stanford’s NMRTI (Non-Volatile Technology Research Initiative), the program features two days of talks, panel sessions and no doubt lots of… Read More
ReRAM Based Memory Buffers in SSDs
In a paper at the VLSI meeting in Hawaii, Professor Ken Takeuchi described using an ReRAM buffer with an SSD. He points to some major performance gains that one can expect from such a configuration in terms of energy, speed and lifetime. Is this an opportunity for ReRAM that could spur development of the technology? Read more in a post… Read More
High Speed PHY Interfacing with SSIC, UFS or PCI express in Smartphone, Media tablet and Ultrabook at Lower Power
We have recently commented the announcement from MIPI Alliance and PCI-SIG, allowing PCI Express to be used in martphone, Media tablet and Ultrabook, while keeping decent power consumption, compatible with these mobile devices. The secret sauce is in the High Speed SerDes function selected to interface with these high data … Read More
ARM, Intel, Apple: It’s Mobile Week
As Dan wrote here, we got invited by Intel to IDF and by ARM to a cheeky little party that they organized the day before. I asked ARM if they were announcing anything and they said basically that it would be foolish to make any announcement the week of their biggest competitors big show. Well, that wasn’t a rule that Apple felt like… Read More
Rapidus, IBM, and the Billion-Dollar Silicon Sovereignty Bet