The move to SSD storage for enterprise use brings with it the need for difficult to design enterprise capable SSD controller SOC’s. The benefits of SSD in hyperscale data centers are clear. SSD’s offer higher reliability due to the elimination of moving parts. They have a smaller foot print, use less power and offer much better performance.… Read More
Semiconductor Intellectual Property
Mentor ARM subscription signals ecosystem shift
Since creating the landmark “all-you-can-eat” license with Samsung in 2002, ARM has inked several subscription deals with chipmakers and EDA firms. The latest ARM subscriber license deal just announced is for Mentor Graphics. What makes their strategy unique?… Read More
SoC power management a study in transition latency
Apple’s recent bout with ‘Batterygate’ highlighted just how important dynamic power management can be. Our last Sonics update looked at using their NoC to manage power islands; this time, we look at their research progress on architectural measures for power management.… Read More
How to handle petabyte-scale traffic growth?
If you search the web for IP traffic growth, you will find many graphics, but the common result is that IP traffic is growing with high CAGR for many years and will again continue to grow with such high CAGR for the next five years. For example the global mobile data traffic is expected to grow with 53% CAGR 2015-2020… even if the smartphone… Read More
New CEVA X baseband architecture takes on multi-RAT
What we think of as a “baseband processor” for cellular networks is often comprised of multiple cores. Anecdotes suggest to handle the different signal processing requirements for 2G, 3G, and 4G networks, some SoC designs use three different DSPs plus a control processor such as an ARM core. That’s nuts. What is the point of having… Read More
Exploring USB Type-C DRP to USB Type-C DFP connection using USB C-Thru
In a USB Type-C environment configuration process between a DRP and a DFP is as follows:
- DRP to DFP attach/detach detection
- Plug orientation detection
- Initial DRP to DFP and power relationship detection
- USB Type-C VBus current detection and usage
Reconfigurable redefined with embedded FPGA core IP
On November 1, 1985, before anyone had heard the phrase field programmable gate array, Xilinx introduced what they called a “new class of ASIC” – the XC2064, with a whopping 1200 gates. Reconfigurable computing was born and thrived around the RAM-based FPGA, whose logic and input/output pins could be architected into a variety… Read More
ARM POPs Another One!
ARM announced a new POP deal with UMC 28nm last week. POP stands for Processor Optimized Package meaning physical IP libraries (logic and memory) are customized for ARM processor cores and mainstream EDA tools creating a platform for optimized chip design. POP is a much bigger deal than most people realize so let’s get into a little… Read More
Low end LTE UE categories seeing more action
Most of our attention goes toward the higher end of the LTE UE categories – ones designed for moving large amounts of multimedia data from smartphones and tablets concurrently with voice traffic. An equally interesting discussion is taking shape at the low end of the LTE UE categories targeting M2M and IoT devices with power-efficient,… Read More
IP Vendor Nabs Top Talent from Semiconductor Industry
The growth of mobile and IoT have helped increase the demand for One Time Programmable Non Volatile Memory (OTP NVM) as a solution for on-chip storage. To continue to meet this demand and grow with it, industry leading Sidense has recently brought on board seasoned semiconductor executive Ken Wagner as VP of Engineering. He was … Read More
AI RTL Generation versus AI RTL Verification