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RISC-V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation

RISC-V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation
by Mike Gianfagna on 12-19-2023 at 8:00 am

RISC V Summit Buzz – Launchpad Showcase Highlights Smaller Company Innovation

One of the goals of the recent RISC-V Summit was to demonstrate that the RISC-V movement is real – major programs by large organizations committing to development around the RISC-V ISA. I would say this goal was achieved. Many high-profile announcements and aggressive, new architectures based on RISC-V were presented. On day … Read More


IEDM: TSMC Ongoing Research on a CFET Process

IEDM: TSMC Ongoing Research on a CFET Process
by Paul McLellan on 12-18-2023 at 6:00 am

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I attended the recent International Electron Devices Meeting (IEDM) last week. Many of the sessions are too technical and too far away from high volume manufacture to make good topics for a blog post. As a Fellow from IBM said about 5nm at and earlier IEDM, “none of these ideas will impact 5nm. It takes ten years for a solution to from… Read More


An Insider’s View of the 2023 Global Semiconductor Alliance’s (GSA) Annual Awards

An Insider’s View of the 2023 Global Semiconductor Alliance’s (GSA) Annual Awards
by Daniel Nenni on 12-14-2023 at 10:00 am

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My beautiful wife and I attended the annual Global Semiconductor Alliance (GSA) Awards event last week. Usually this is a solo event but since my wife is CFO of SemiWiki I was able to get her an invite. I go every year and she wanted to see what all of the excitement was about. She also knows quite a few industry people from attending the… Read More


WEBINAR: FPGA-Accelerated AI Speech Recognition

WEBINAR: FPGA-Accelerated AI Speech Recognition
by Don Dingee on 12-14-2023 at 6:00 am

Cloud ASR demo on Speedster 7t FPGA

The three-step conversational AI (CAI) process – automatic speech recognition (ASR), natural language processing, and text-to-synthesized speech response – is now deeply embedded in the user experience for smartphones, smart speakers, and other devices. More powerful large language models (LLMs) can answer more queries… Read More


WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems

WEBINAR: Joint Pre synthesis RTL & Power Intent Assembly flow for Large System on Chips and Subsystems
by Daniel Nenni on 12-11-2023 at 10:00 am

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Nowadays, low power design requirements are key for large SoCs (system on chips) for different applications: AI, Mobile, HPC, etc. Power intent management early in the design flow is becoming crucial to help facing PPA (Power Performance Area) design challenges.

WEBINAR REGISTRATION

With the increasing complexity of such … Read More


IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation
by Mike Gianfagna on 12-10-2023 at 2:00 pm

IEDM Buzz – Intel Previews New Vertical Transistor Scaling Innovation

For more than 65 years, the IEEE International Electron Devices Meeting (IEDM) has been the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. As I post this, the conference is underway in San Francisco… Read More


Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?

Webinar: “Navigating our AI Wonderland” … with humans-in-the-Loop?
by Richard Curtin on 12-06-2023 at 8:00 am

AIeverywhere EETimes

AI is here, there, and absolutely everywhere – now and forever.

The electronics industry, and the world at-large, have experienced an overwhelming amount of AI coverage this year, with no letup in store for 2024. Both EE Times and Silicon Catalyst have recently staged events around artificial intelligence:

  • AI Everywhere” delivered
Read More

RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®

RISC-V Summit Buzz – Axiomise Accelerates RISC-V Designs with Next Generation formalISA®
by Mike Gianfagna on 12-04-2023 at 6:00 am

RISC V Summit Buzz – Axiomise Accelerates RISC V Designs with Next Generation formalISA®

If the recent RISC-V Summit proved one thing it’s that open-source hardware design, and particularly the RISC-V instruction set architecture (ISA) has entered the mainstream. It is a design methodology and architecture to watch closely. Across a broad range of applications from data center, to automotive, to IoT, RISC-V processors… Read More


RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization

RISC-V Summit Buzz – Semidynamics Founder and CEO Roger Espasa Introduces Extreme Customization
by Mike Gianfagna on 11-30-2023 at 10:00 am

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Founded in 2016 and based in Barcelona, Spain, Semidynamics™ is the only provider of fully customizable RISC-V processor IP.  The company delivers high bandwidth, high performance cores with vector units and tensor units targeted at machine learning and AI applications. There were some recent announcements from Semidynamics… Read More


WEBINAR : Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques

WEBINAR : Avoiding Metastability in Hardware Software Interface (HSI) using CDC Techniques
by Daniel Nenni on 11-28-2023 at 10:00 am

Agnisys Mux Synchronizer

This webinar looks at the challenges a Design Engineer could face, such as when various IP blocks within an SoC are required to work in different clock domains to satisfy the power constraints.

Abstract:
Various IP blocks within an SoC are often required to work in different clock domains in order to satisfy the power constraints.… Read More