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DAC 2021 – Taming Process Variability in Semiconductor IP

DAC 2021 – Taming Process Variability in Semiconductor IP
by Daniel Payne on 12-27-2021 at 10:00 am

process node variability min

Tuesday at DAC was actually my very first time attending a technical session, and the presentation from Nebabie Kebebew, Siemens EDA, was called, Mitigating Variability Challenges of IPs for Robust Designs. There were three presentations scheduled for that particular Designer, IP and Embedded Systems track, but with the COVID… Read More


DAC 2021 – Siemens EDA talks about using the Cloud

DAC 2021 – Siemens EDA talks about using the Cloud
by Daniel Payne on 12-21-2021 at 10:00 am

Craig Johnson

My third event at DAC on Monday was all about using EDA tools in the Cloud, and so I listened to Craig Johnson, VP EDA Cloud Solutions, Siemens EDA. Early in the day I heard from Joe Sawicki, Siemens EDA, on the topic of Digitalization.

Why even use the Cloud for EDA? That’s a fair question to ask, and Craig had several high-level… Read More


DAC 2021 – Joe Sawicki explains Digitalization

DAC 2021 – Joe Sawicki explains Digitalization
by Daniel Payne on 12-13-2021 at 10:00 am

semiconductor content min

Monday at DAC this year started off on a very optimistic note as Joe Sawicki from Siemens EDA presented in the Pavilion on the topic of Digitalization, a frequent theme in the popular press because of the whole Work From Home transition that we’ve gone through during the pandemic. Several industries are benefiting from the… Read More


System Technology Co-Optimization (STCO)

System Technology Co-Optimization (STCO)
by Daniel Payne on 11-30-2021 at 10:00 am

An early package prototype

My first exposure to seeing multiple die inside of a single package in order to get greater storage was way back in 1978 at Intel, when they combined two 4K bit DRAM die in one package, creating an 8K DRAM chip, called the 2109. Even Apple used two 16K bit DRAM chips from Mostek to form a 32K bit DRAM, included in the Apple III computer, circa… Read More


Siemens EDA will be returning to DAC this year as a Platinum Sponsor.

Siemens EDA will be returning to DAC this year as a Platinum Sponsor.
by Daniel Nenni on 11-29-2021 at 10:00 am

Siemens EDA DAC

The 38th Design Automation Conference is next week and this one is for the record books. Having been virtual the last two years, next week we will meet live once again. I think we may have all taken for granted the value of live events but now we know how important they are on both a professional and human level, absolutely.

“The… Read More


Machine Learning Applied to IP Validation, Running on AWS Graviton2

Machine Learning Applied to IP Validation, Running on AWS Graviton2
by Daniel Payne on 11-22-2021 at 10:00 am

Solido Variation Designer on Neoverse N1 CPU min

I recall meeting with Solido at DAC back in 2009, learning about their Variation Designer tool that allowed circuit designers to quickly find out how their designs performed under the effects of process variation, in effect finding the true corners of the process. Under the hood the Solido tool was using Machine Learning (ML) techniques… Read More


Siemens EDA Automotive Insights, for Analysts

Siemens EDA Automotive Insights, for Analysts
by Bernard Murphy on 11-16-2021 at 6:00 am

Siemens auto electronics min

There is a classical approach to EDA marketing, and semiconductor marketing at times, which aims exclusively at technical customers and the businesspeople immediately around those experts. The style is understandable and necessary. Those folks are the direct influencers and buyers of the products we are promoting, so we must… Read More


Tessent Streaming Scan Network Brings Hierarchical Scan Test into the Modern Age

Tessent Streaming Scan Network Brings Hierarchical Scan Test into the Modern Age
by Tom Simon on 11-15-2021 at 10:00 am

Streaming Scan Network

Remember when you had to use dial up internet or parallel printer cables connected directly to the printer to print something? Well even if you don’t remember these things, you know that now there is a better way. Regrettably, the prevalent methods used for hierarchical Design for Test (DFT) still look at lot like this – SoC level … Read More


Minimizing MCU Supply Chain Grief

Minimizing MCU Supply Chain Grief
by Bernard Murphy on 11-11-2021 at 6:00 am

Siemens AUTOSAR min

I doubt there is anyone who hasn’t felt the impact of supply chain problems, from late ecommerce deliveries (weeks) to kitchen appliances (up to 6 months or more). Perhaps no industry has been more affected than auto makers, whose cars are now critically dependent on advanced electronics. According to a white paper recently released… Read More


Back to Basics in RTL Design Quality

Back to Basics in RTL Design Quality
by Bernard Murphy on 11-03-2021 at 6:00 am

Deming min

Harry Foster waxes philosophical in a recent white paper from Siemens EDA, in this case on the origins of bugs and the best way to avoid them. Spoiler alert, the answer is not to make them in the first place or at least to flush them out very quickly. I’m not being cynical – that really is the answer though practice often falls short of ideal.… Read More