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EDA

Electronic Design Automation

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Wally’s u2u keynote

Wally’s u2u keynote
by Paul McLellan on 04-27-2011 at 3:25 pm
Categories: EDA, Siemens EDA

I was at Wally’s u2u (Mentor user group) keynote yesterday. The other keynote was by Ivo Bolsens of Xilinx and is here. He started off by looking at how the semiconductor industry has recovered and silicon area shipments are now back on trend after a pronounced drop in 2009 and revenue has followed. Finally the semiconductor… Read More

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Semiconductor RTL Power Analysis: the sweet spot

Semiconductor RTL Power Analysis: the sweet spot
by Paul McLellan on 04-26-2011 at 4:20 pm
Categories: Ansys, Inc., EDA

Power has become the strongest driver of semiconductor design today, more important than area, more important than timing. Whether the device is handheld, like a wireless phone, or tethered, like a router, complex power and energy requirements must be met. Shrinking geometries continue to impose new challenges as power management… Read More

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How Avnera uses Hardware Configuration Management with Virtuoso IC Tools

How Avnera uses Hardware Configuration Management with Virtuoso IC Tools
by Daniel Payne on 04-21-2011 at 12:12 pm
Categories: Cadence, Cliosoft, EDA

Introduction
Here in the Silicon Forest (Oregon) we have a venture-backed, fabless analog semi company called Avnera that has designed over 10 Analog System on Chips (ASoC). Their chips are used in consumer products for both wireless audio and video applications.

 

James Rollins is the director of physical design at Avnera… Read More

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Transistor-Level Electrical Rule Checking

Transistor-Level Electrical Rule Checking
by Daniel Payne on 04-20-2011 at 11:19 am
Categories: EDA, Siemens EDA

Introduction
Circuit designers work at the transistor level and strive to get the ultimate in performance, layout density or low power by creating crafty circuit topologies in both schematics and layout. Along with this quest comes the daunting task of verifying that all of your rules and best practices about reliability have… Read More

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Semiconductor Virtual Platform Models

Semiconductor Virtual Platform Models
by Paul McLellan on 04-19-2011 at 3:38 pm
Categories: EDA

Virtual platforms have been an area that has some powerful value propositions for both architectural analysis and for software development. But the fundamental weakness has been the modeling problem. People want fast and accurate models but this turns out to be a choice.

The first issue is that there is an unavoidable tradeoff… Read More

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Chip-Package-System (CPS) Co-design

Chip-Package-System (CPS) Co-design
by Paul McLellan on 04-14-2011 at 5:13 pm
Categories: Ansys, Inc., EDA

I can still remember the time, back in the mid-1980s, when I was at VLSI and we first discovered that we were going to have to worry about package pin inductance. Up until then we had been able to get away with a very simplistic model of the world since the clock rates weren’t high enough to need to worry about the package and PCB as… Read More

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Who Needs a 3D Field Solver for IC Design?

Who Needs a 3D Field Solver for IC Design?
by Daniel Payne on 04-07-2011 at 4:53 pm
Categories: EDA, Siemens EDA

Inroduction
In the early days we made paper plots of an IC layout then measured the width and length of interconnect segments with a ruler to add up all of the squares, then multiplied by the resistance per square. It was tedious, error prone and took way too much time, but we were rewarded with accurate parasitic values for our SPICE… Read More

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DRC/DFM inside of Place and Route

DRC/DFM inside of Place and Route
by Daniel Payne on 03-31-2011 at 10:19 am
Categories: EDA, Siemens EDA

Intro
Earlier this month I drove to Mentor Graphics in Wilsonville, Oregon and spoke with Michael Buehler-Garcia, Director of Marketing and Nancy Nguyen, TME, both part of the Calibre Design to Silicon Division. I’m a big fan of correct-by-construction thinking in EDA tools and what they had to say immediately caught my… Read More

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Andrew Yang’s presentation at Globalpress electronic summit

Andrew Yang’s presentation at Globalpress electronic summit
by Paul McLellan on 03-30-2011 at 3:15 pm
Categories: Ansys, Inc., EDA

Yesterday at the Globalpress electronic summit Andrew gave an overview of the Apache product line, carefully avoiding saying anything he cannot due to the filing of Apache’s S-1. From a financial point of view the company has had 8 years of consecutive growth, is profitable since 2008, and has no debt. During 2010 when the… Read More

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2011 Semiconductor Design Forecast: Partly Cloudy!

2011 Semiconductor Design Forecast: Partly Cloudy!
by Daniel Nenni on 03-29-2011 at 11:39 am
Categories: EDA, Synopsys

This was my first SNUG (Synopsys User Group) meeting as media so it was a ground breaking event. Media was still barred from some of the sessions but hey, it’s a start. The most blog worthy announcement on day 1 was that Synopsys signed a deal with Amazon to bring the cloud to mainstream EDA!

Even more blog worthy was a media roundtable… Read More