A new look at fault localization and repair in debug using learning based on deep semantic features. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.
Electronic Design Automation
Why Secure Ethernet Connections?
While web browsing I constantly glance for the padlock symbol to indicate that the site is encrypting any of my form data by using the https prefix, which means that an SSL (Secure Sockets Layer) certificate is being used by the web hosting company. I have peace of mind knowing that my credit card information cannot be easily stolen… Read More
Chiplet Interconnect Challenges and Standards
For decades now I’ve watched the incredible growth of SoCs in terms of die size, transistor count, frequency and complexity. Instead of placing all of the system complexity into a single, monolithic chip, there are now compelling reasons to use a multi-chip approach, like when the maximum die size limit is reached, or it’s… Read More
IP Lifecycle Management for Chiplet-Based SoCs
Chiplet-based System-on-Chips (SoCs) are becoming increasingly popular in the semiconductor industry due to their potential to improve design efficiency, increase performance, and reduce costs. While chiplets are seen as a way to reduce the cost of innovation, they introduce a lot of challenges too. Packaging, interconnect… Read More
CEO Interview: Issam Nofal of IROC Technologies
Issam Nofal is the CEO of IROC Technologies and has held various positions with the company for over 23 years as Product Manager, Project Leader, and R&D Engineer. He has authored several papers on test and reliability of Integrated Circuits. He holds a PhD in Microelectronics from Grenoble INP.
What is IROC Technologies’
… Read MoreDriving the Future of HPC Through 224G Ethernet IP
The need for speed is a never-ending story when it comes to data communications. Currently there are a number of trends such as cloud computing, artificial intelligence, Internet of Things (IoT), multimedia applications and consumer expectations driving this demand. All of these trends are accelerating the growth in high-performance-computing… Read More
US giant swoops for British chipmaker months after Chinese sale blocked on national security grounds
According to UK based The Telegraph Pulsic is a chip maker and Cadence is a swooping US giant. I guess you have to stretch the truth to get those precious clicks these days. Even so this is a strategic acquisition for Cadence.
Pulsic is a 20+ year old EDA software company that offers chip planning and implementation software for custom… Read More
Chiplet Q&A with John Lee of Ansys
At the recent Synopsys Users Group Meeting (SNUG) I had the honor of leading a panel of experts on the topic of chiplets. One of those panelists was John Lee, Head of Electronics, Semiconductors and Optics at Ansys.
How is the signoff flow evolving and what is being done to help mitigate the growing signoff complexity challenge?
With… Read More
Opinions on Generative AI at CadenceLIVE
According to some AI dreamers, we’re almost there. We’ll no longer need hardware or software design experts—just someone to input basic requirements from which fully realized system technologies will drop out the other end. Expert opinions in the industry are enthusiastic but less hyperbolic. Bob O’Donnell, president, founder… Read More
Ansys Acquires Another!
The headline is: Ansys Signs Definitive Agreement to Acquire Diakopto, Expands Multiphysics Simulation Portfolio for Semiconductor Designers. The acquisition complements Ansys’ existing signoff solutions and enables integrated circuit (IC) designers to detect problems earlier in the design flow.
Which is certainly… Read More
Rethinking Multipatterning for 2nm Node