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Electronic Design Automation
Ground. It’s that little downward-pointing triangle that somehow works miracles on every schematic. It looks very simple until one has to tackle modern power distribution network (PDN) design on a board with high speed and high power draw components, and you soon discover ground is a complicated fairy tale with a lot of influences.… Read More
Accuracy, ease of use and performance have always been paramount for electromagnetic analysis software. Historically, it has been hard to find all three of these qualities in one tool. The result is that many high speed analog and RF designers resort to using multiple, often overlapping, tools to get the job done.
Lorentz Solution… Read More
Risks and Rewards of Engaging with EDA Startups:The Hunger Games!
Doing business with EDA startups comes with both risks and rewards. The Hogan’s Heroes panel at DAC 2013 features key decision makers from fabless, startup and vc firms sharing candid opinions on this risk/reward equation, and the financial and technical issues… Read More
In EDA we often talk about how fast a SPICE circuit simulator is, or about capacity and accuracy compared to silicon measurements. Yes, speed, capacity and accuracy are important, however when talking to actual transistor-level circuit designers you discover something quite different, most of their time is spent doing debugging,… Read More
The conference program for DAC is now live here including the conference itself, keynotes, some other special tracks, the pavilion panels and more. And the must-see panel is on emulation at 4pm on Tuesday afternoon moderated by…well, that would be me so I’m a bit biased.
TSMC will host their annual technology symposium at several locations in the U.S. on April 9th in San Jose, April 16th in Austin, and April 23rd in Boston. TSMC will discuss the market outlook, design enablement, and technology for high-speed computing, mobile communications, connectivity and storage, CIS, embedded flash, … Read More
When Cadence acquired Sigrity in 2012, two motives were involved: get more competitive in state of the art signal integrity analysis, and grab a foothold into the other vendor’s PCB flows in an area that is developing as a real sore spot for digital designers.
Just as the days where PCB tape-out meant actually using tape are over, … Read More
Cliff Hou of TSMC gave the keynote today at SNUG on Collaborate to Innovate: a Foundry’s Perspective. Starting around 45nm the way that a foundry has to work with its ecosystem fundamentally changed. Up until then, each process generation was similar enough to the previous one, apart obviously from size, that it could be … Read More
If I had a nickel for every time I heard the term “FinFET” at the 2013 SNUG (Synopsys User Group) Conference I could buy a dozen Venti Carmel Frappuccinos at Starbucks (my daughter’s favorite treat). In the keynote, Aart de Geus said FinFET 14 times and posed the question: Will FinFETs Yield at 14nm? So that was my mission, ask everybody… Read More
So, you dropped that piece of complex IP you just licensed into an SoC design, and now it is time to fire up the simulator. How do you verify that it actually works in your design? If you didn’t get verification IP (VIP) with the functional IP, it might be a really long day.
Compliance checking something like a PCIe interface block is a … Read More
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Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools