As one of the world’s leading chip foundries, Samsung occupies a vital position in the semiconductor value chain. The annual Samsung Advanced Foundry Ecosystem (SAFE™) Forum is a must-go event for semiconductor and electronic design automation (EDA) professionals. Ajei Gopal, President and CEO of Ansys, has the honor of delivering… Read More
Electronic Design Automation
Requirements for Multi-Die System Success
Chiplets continue to be a hot topic on SemiWiki, conferences, white papers, webinars and one of the most active chiplet enabling vendors we work with is Synopsys. Synopsys is the #1 EDA and #1 IP company so that makes complete sense.
As you may have read, I moderated a panel on Chiplets at the last SNUG which we continue to write about.
S2C Accelerates Development Timeline of Bluetooth LE Audio SoC
S2C has been shipping FPGA prototyping platforms for SoC verification for almost two decades, and many of its customers are developing SoCs and silicon IP for Bluetooth applications. Prototyping Bluetooth designs before silicon has yielded improved design efficiencies through more comprehensive system validation, and… Read More
An Automated Method to Ensure Designs Are Failure-Proof in the Field
I don’t know about you, but when I think of mission-critical applications, I immediately think of space exploration or military operations. But in today’s world, mission-critical applications are all around us. Think about the cloud and how data is managed, analyzed, and shared to execute any number of tasks that have safety … Read More
WEBINAR: Revolutionizing Chip Design with 2.5D/3D-IC Design Technology
In the 3D-IC (Three-dimensional integrated circuit) chip design method, chiplets or wafers are stacked vertically on top of each other and are connected using Through Silicon Vias (TSVs) or hybrid bonding.
The 2.5D-IC design method places multiple chiplets alongside each other on a silicon interposer. Microbumps and interconnect… Read More
CEO Interview: Dr. Sean Wei of Easy-Logic
Dr. Wei has served as CEO & CTO of Easy-Logic since 2020. Prior to this role, Dr. Wei served as CTO since 2014 where he constructed the core algorithm and the tool structure of EasyECO. As the CEO, Dr. Wei focuses on building a strong company infrastructure. In his CTO role he interfaces with strategic ASIC design customers … Read More
Getting the most out of a shift-left IC physical verification flow with the Calibre nmPlatform
Who first came up with this term shift-left ? I’d assumed Siemens EDA as they use it so widely. But their latest white paper on the productivity improvements possible with shift-left Calibre IC verification flows puts the record straight: a software engineer called Larry Smith bagged the naming rights in a 2001 paper (leapfrogging… Read More
Automotive IP Certification
The electrification of cars and the growth of EVs means that more semiconductor content is being added with every new vehicle model from suppliers around the globe. There are unique concerns for automotive IP in terms of reliability, security and safety over the lifetime of the vehicle. I had the pleasure to speak with Pawini Mahajan… Read More
WEBINAR: UCIe PHY Modeling and Simulation with XMODEL
Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog,… Read More
Rethinking Multipatterning for 2nm Node