ads mdx semiwiki building trust gen 800x100ai
WP_Term Object
(
    [term_id] => 157
    [name] => EDA
    [slug] => eda
    [term_group] => 0
    [term_taxonomy_id] => 157
    [taxonomy] => category
    [description] => Electronic Design Automation
    [parent] => 0
    [count] => 4280
    [filter] => raw
    [cat_ID] => 157
    [category_count] => 4280
    [category_description] => Electronic Design Automation
    [cat_name] => EDA
    [category_nicename] => eda
    [category_parent] => 0
    [is_post] => 
)

Circuit Simulation Update from Empyrean at #61DAC

Circuit Simulation Update from Empyrean at #61DAC
by Daniel Payne on 08-13-2024 at 10:00 am

Empyrean SPICE min

A familiar face in EDA, Greg Lebsack met with me in the Empyrean booth at DAC this year on opening day to provide an update on what’s new. I first met Greg when he was at Tanner EDA, then Mentor and Siemens EDA, so he really knows our industry quite well. The company was a Silver level sponsor of DAC this year, and Empyrean offers tools for… Read More


Podcast EP240: Challenges and Strategies to Address New Embedded Memory Architectures with Mark Han

Podcast EP240: Challenges and Strategies to Address New Embedded Memory Architectures with Mark Han
by Daniel Nenni on 08-09-2024 at 10:00 am

Dan is joined by Dr. Mark Han, Vice President of R&D Engineering for Circuit Simulation at Synopsys. Mark leads a team of over 300 engineers in developing cutting-edge advanced circuit simulation and transistor-level sign-off products, including characterization and static timing analysis. With 27 years of industry … Read More


Podcast EP239: The Future of Verification for Advanced Systems with Dave Kelf

Podcast EP239: The Future of Verification for Advanced Systems with Dave Kelf
by Daniel Nenni on 08-07-2024 at 8:00 am

Dan is joined by Dave Kelf, CEO of Breker Verification Systems, whose product portfolio solves challenges across the functional verification process for large, complex semiconductors. Dave has deep experience with semiconductor design and verification with management and executive level positions at Cadence, Synopsys,… Read More


The Future of Logic Equivalence Checking

The Future of Logic Equivalence Checking
by Bernard Murphy on 08-07-2024 at 6:00 am

LEC concept

Logic equivalence checking (LEC) is an automated process to verify that modified versions of a design evolving through implementation remain logically equivalent to the functionally signed-off RTL. This becomes important when accounting for retiming optimizations and for necessary implementation-stage ECOs which must… Read More


Aniah and Electrical Rule Checking (ERC) #61DAC

Aniah and Electrical Rule Checking (ERC) #61DAC
by Daniel Payne on 08-06-2024 at 10:00 am

Aniah #61DAC min

Visiting a new EDA vendor at #61DAC is always a treat, because much innovation comes from the start-up companies, instead of the established big four EDA companies. I met with Vincent Bligny, Founder and CEO of Aniah on Wednesday in their booth, to hear about what they are doing differently in EDA. Mr. Bligny has a background working… Read More


Writing Better Code More Quickly with an IDE and Linting

Writing Better Code More Quickly with an IDE and Linting
by Tom Anderson on 08-06-2024 at 6:00 am

Lightmatter

As a technical marketing consultant, I always enjoy the chance to talk to hands-on users of my clients’ electronic design automation (EDA) tools to “see how the sausage is made” on actual projects. Cristian Amitroaie, CEO of AMIQ EDA, recently connected me with Verification and Infrastructure Manager Dan Cohen and Verification… Read More


Mitigating AI Data Bottlenecks with PCIe 7.0

Mitigating AI Data Bottlenecks with PCIe 7.0
by Kalar Rajendiran on 08-05-2024 at 6:00 am

Mitigating AI Data Bottlenecks with PCIe 7.0 LinkedIn Event

During a recent LinkedIn webcast, Dr. Ian Cutress, Chief Analyst at More than Moore and Host at TechTechPotato, and Priyank Shukla, Principal Product Manager at Synopsys, shared their thoughts regarding the industry drivers, design considerations, and critical advancements in compute interconnects enabling data center… Read More


AI-Powered Transformation in EDA

AI-Powered Transformation in EDA
by Admin on 08-01-2024 at 5:00 pm

The integration of artificial intelligence (AI) into Electronic Design Automation (EDA) is revolutionizing chip design, addressing the critical shortage of skilled engineers and accelerating the development process. As Jeff Dyck, Senior Director of Engineering at Siemens EDA, explains in a recent DACtv presentation, … Read More


Visualizing Multi-Die Design: Ansys and NVIDIA’s Omniverse Collaboration

Visualizing Multi-Die Design: Ansys and NVIDIA’s Omniverse Collaboration
by Admin on 08-01-2024 at 4:00 pm

In a DACtv session on July 22, 2024, Rich Goldman from Ansys discussed the partnership with NVIDIA, focusing on accelerating engineering simulations and visualizing 3D IC designs in Omniverse. The collaboration, outlined in six pillars defined by NVIDIA CEO Jensen Huang, leverages NVIDIA’s GPUs and Grace CPUs to enhance… Read More


Easy-Logic and Functional ECOs at #61DAC

Easy-Logic and Functional ECOs at #61DAC
by Daniel Payne on 08-01-2024 at 10:00 am

gtech min

I first visited Easy-Logic at DAC in 2023, so it was time to meet them again at #61DAC in San Francisco to find out what’s new this year. Steven Chen, VP Sales for North America and Asia met with me in their booth for an update briefing. Steven has been with Easy-Logic for six years now and earned an MBA from Baruch College in New York. This… Read More