BroncoAI DVCon100x800 FIX
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Mathematics are Hard – That is Why AI Needs Mathematics Hardware

Mathematics are Hard – That is Why AI Needs Mathematics Hardware
by Tom Simon on 01-29-2019 at 7:00 am

The field of artificial intelligence has relied on heavy inspiration from the world of natural intelligence, such as the human mind, to build working systems that can learn and act on new information based on that learning. In natural networks, neurons do the work, deciding when to fire based on huge numbers of inputs. The relationship… Read More


Accelerating 5G Design Innovation Through Simulation Workshop

Accelerating 5G Design Innovation Through Simulation Workshop
by Daniel Nenni on 01-22-2019 at 12:00 pm

DesignCon is coming up, kicking off the first of many industry conferences for the year. It’s at the Santa Clara Convention Center which is the best venue in Northern California. Not only is this a semiconductor crowd, it’s also a systems crowd covering chips, boards, and systems. More than 175 companies participate with an expected… Read More


At Last, Package and Chip integration for RF Design

At Last, Package and Chip integration for RF Design
by Tom Simon on 01-21-2019 at 7:00 am

It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More


Applying Generative Design to Automotive Electrical Systems

Applying Generative Design to Automotive Electrical Systems
by Daniel Payne on 01-15-2019 at 12:00 pm

Scanning headlines of technology news every day I was somewhat familiar with the phrase “Generative Design” and even browsed the Wikipedia page to find this informative flow-chart that shows the practice of generative design.


Generative design is an iterative design process that involves a program that will generateRead More


Specialized AI Processor IP Design with HLS

Specialized AI Processor IP Design with HLS
by Alex Tan on 01-14-2019 at 12:00 pm

Intelligence as in the term artificial intelligence (AI) involves learning or training, depending on which perspective it is viewed from –and it has many nuances. As the basis of most deep learning methods, neural network based learning algorithms have gained usage traction, when it was shown that training with deep neural network… Read More


Rapid Prototyping ARM Based Designs Webinar

Rapid Prototyping ARM Based Designs Webinar
by Daniel Nenni on 01-07-2019 at 7:00 am

While writing the definitive book on ARM history we could not have imagined a more different exit than the SoftBank acquisition, not even close. It is now very clear why SoftBank acquired ARM for $31B. It is also very clear why alternatives like RISC-V are trending on SemiWiki and will continue to do so, absolutely. No matter what … Read More


Designing a fully digitally controlled DC-DC buck converter

Designing a fully digitally controlled DC-DC buck converter
by Tom Simon on 12-31-2018 at 7:00 am

One of the unsung heroes of our digital world is the modest voltage converter. Batteries and wired power sources rarely match up with the supply needs for advanced ICs. Leading edge ICs have multiple voltage domains and very often, as in the case of processors, use dynamic voltage scaling to help conserve power. Looking at where … Read More


Tackling Manufacturing Errors Early with CMP Simulation

Tackling Manufacturing Errors Early with CMP Simulation
by Alex Tan on 12-28-2018 at 12:00 pm

CMP (Chemical Mechanical Planarization or also known as Chemical Mechanical Polishing) is a wafer fabrication step applied generally after a chemical deposition –intended to smoothen and to flatten (planarize) wafer surfaces with the combination of chemical and mechanical forces. Developed at IBM and since its introduction… Read More


Physical Verification with IC Validator

Physical Verification with IC Validator
by Alex Tan on 12-26-2018 at 7:00 am

If a picture worths a thousand words, a tapeout quality SoC design with billions of polygons would compose a good book. To proofread this final design transformation format requires a foundry driven DRC/LVS signoff solution that nowadays is becoming more complex with further process scaling and shrinking pitch dimension.

Despite… Read More