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Electronic Design Automation
A Network-on-Chip (NoC) IP addresses the challenges of interconnect complexity in SoCs by significantly reducing wiring congestion and providing a scalable architecture. It allows for efficient communication among numerous initiators and targets with minimal latency and high speed. A NoC facilitates design changes, enabling… Read More
When I was at DAC last month, I had the chance to talk with Chouki Aktouf and Bastien Gratréaux from Defacto and they told me about a new innovative solution to generate Arm-based System-on-Chips. I heard that this solution has now been released.
Defacto and Arm developed a joint SoC design flow to help Arm users cover all needed automation—from… Read More
As AI and 5G technologies burgeon, the rise of interconnected devices is reshaping everyday life and driving innovation across industries. This rapid evolution accelerates the transformation of the chip industry, placing higher demands on SoC design. Moore’s Law indicates that while chip sizes shrink, the number of… Read More
#61DAC was buzzing with discussion of chiplet-based, heterogeneous design. This new design approach opens new opportunities for applications such as AI, autonomous driving and even quantum computing. A critical enabler for all this to work is reliable, cost-effective advanced packaging, and that is the topic of this post.… Read More
An under-appreciated but critical component in signing off the final stage of chip design for manufacture is timing closure – aligning accurate timing based on final physical implementation with the product specification. Between advanced manufacturing processes and growing design sizes, the most important factors determining… Read More
Transistor-level circuit designers have long used SPICE for circuit simulation, mostly because it is silicon accurate and helps them to predict the function, timing, power, waveforms, slopes and delays in a cell before fabrication. RTL designers use digital simulators that have a huge capacity but are lacking analog modeling.… Read More
PCIe design complexity continues rising as the standard for intrasystem communication evolves. An urgent need for more system bandwidth drives PCIe interconnects to multi-lane, multi-link, multi-level signaling. Classical PCIe design workflows leave designers with most of the responsibility for getting the requisite… Read More
Part 1 of this 4-part series introduces the complexities of developing and bringing up the entire software stack on a System on Chip (SoC) or Multi-die system. It explores various approaches to deployment, highlighting their specific objectives and the unique challenges they address.
As the saying goes, it’s… Read More
#61DAC is evolving. The big get bigger and ultimately focus on other venues for customer outreach and branding. This is a normal evolution in any industry. For EDA, it was noticed by many that Cadence and Synopsys have downsized their booths at DAC. Everyone knows CDNLive and SNUG are very successful events for these companies and… Read More
RISC-V is clearly gaining momentum across many applications. That was quite clear at #61DAC as well. Breker Verification Systems solves challenges across the functional verification process for large, complex semiconductors. Its Trek family of products is production-proven at many leading semiconductor companies worldwide.… Read More
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CHIPS Act dies because employees are fired – NIST CHIPS people are probationary