WP_Term Object
(
    [term_id] => 18712
    [name] => Keysight EDA
    [slug] => keysight-eda
    [term_group] => 0
    [term_taxonomy_id] => 18712
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 34
    [filter] => raw
    [cat_ID] => 18712
    [category_count] => 34
    [category_description] => 
    [cat_name] => Keysight EDA
    [category_nicename] => keysight-eda
    [category_parent] => 157
    [is_post] => 
)
            
Keysight Quantum Bootcamp 800x100 Mar 2025
WP_Term Object
(
    [term_id] => 18712
    [name] => Keysight EDA
    [slug] => keysight-eda
    [term_group] => 0
    [term_taxonomy_id] => 18712
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 34
    [filter] => raw
    [cat_ID] => 18712
    [category_count] => 34
    [category_description] => 
    [cat_name] => Keysight EDA
    [category_nicename] => keysight-eda
    [category_parent] => 157
    [is_post] => 
)

Webinar: RF board design flow examples for co-simulating active circuits

Webinar: RF board design flow examples for co-simulating active circuits
by Don Dingee on 03-25-2025 at 10:00 am

Mesh domain optimization

In part one of this webinar series, Keysight and Modelithics looked at the use of 3D passive vendor component models supporting highly accurate, automated 3D EM-circuit co-simulation of high-frequency RF board designs. Part two continues the exploration of RF board design flows for simulating active circuits on boards, again… Read More


Webinar: RF design success hinges on enhanced models and accurate simulation

Webinar: RF design success hinges on enhanced models and accurate simulation
by Don Dingee on 02-19-2025 at 10:00 am

Modelithics 3D Library for RFPro increases the chances for RF design success

Traditional RF board design strategies based on circuit simulation worked at lower frequencies and relatively large spacing between components. Higher frequencies and densification dominate RF designs now, where corresponding wider bandwidths and tighter layouts with closely spaced components produce more complex 3D… Read More


Chiplets-Based Systems: Keysight’s Role in Design, Testing, and Data Management

Chiplets-Based Systems: Keysight’s Role in Design, Testing, and Data Management
by Kalar Rajendiran on 02-11-2025 at 6:00 am

Voltage Transfer Function Crrosstalk Limit

Keysight, with deep roots tracing back to Hewlett-Packard, has long been at the forefront of innovation in electronic design and testing. It manufactures electronics test and measurement equipment and software. The company also owns its own foundry and makes custom chips and packages for its instrumentation business. Many… Read More


Crosstalk, 2kAmp power delivery, PAM4, and LPDDR5 analysis at DesignCon

Crosstalk, 2kAmp power delivery, PAM4, and LPDDR5 analysis at DesignCon
by Don Dingee on 01-24-2025 at 8:00 am

Old way of crosstalk analysis

High-speed digital (HSD) designers have long tested the limits of realizable speed. GHz frequencies are now the norm, and multi-level signaling is pushing rates higher while the long-awaited transition to optical signaling and even higher rates looms ever closer. Power density is also climbing, and data-hungry applications… Read More


Chiplet integration solutions from Keysight at Chiplet Summit

Chiplet integration solutions from Keysight at Chiplet Summit
by Don Dingee on 01-15-2025 at 10:00 am

signal integrity of electrical layer in UCIe

Chiplets continue gaining momentum, fueled in large part by applications for AI and 5G/6G RFICs. Keysight has a strong presence at this year’s Chiplet Summit in Santa Clara, which includes Simon Rance in a super panel discussing “Chiplets: The Key to Solving the AI Energy Gap” and Nilesh Kamdar with a keynote… Read More


GaN HEMT modeling with ANN parameters targets extensibility

GaN HEMT modeling with ANN parameters targets extensibility
by Don Dingee on 11-18-2024 at 6:00 am

Modified ASM HEMT equivalent circuit for GaN HEMT modeling with ANN parameters

Designers choosing gallium nitride (GaN) transistors may face a surprising challenge when putting the devices in their context. While the Advanced SPICE Model for GaN HEMTs (ASM-HEMT) model captures many behaviors like thermal and trapping effects, it grapples with accuracy over a wide range of bias conditions. Foundries … Read More


Keysight EDA 2025 launches AI-enhanced design workflows

Keysight EDA 2025 launches AI-enhanced design workflows
by Don Dingee on 11-11-2024 at 6:00 am

Keysight ADS 2025 enables AI-enhanced design workflows

The upcoming Keysight EDA 2025 launch has three familiar tracks: RF circuit design, high-speed digital circuit design, and device modeling and characterization. However, this update features a common thread between the tracks – AI-enhanced design workflows. AI speeds modeling and simulation, opening co-optimization for… Read More


Webinar: When Failure in Silicon Is Not an Option

Webinar: When Failure in Silicon Is Not an Option
by Daniel Nenni on 10-10-2024 at 6:00 am

background (4)

If the thought of a silicon respin keeps you awake at night, you’re not alone. Re-fabricating a chip can cost tens of millions of dollars. An unplanned respin also risks a delay in getting a product to market, which adds tremendous costs in terms of lost business.

Undoubtedly, adding to your sleep loss is the recent rise in respins.… Read More


Keysight EDA and Engineering Lifecycle Management at #61DAC

Keysight EDA and Engineering Lifecycle Management at #61DAC
by Daniel Payne on 08-29-2024 at 10:00 am

Keysight EDA at 61DAC min

Entering the exhibit area of DAC on the first floor I was immediately faced with the Keysight EDA booth, and it was even larger than either the Synopsys or Cadence booths. They had a complete schedule of partners presenting in their theatre that included: Microsoft Azure, Riscure, Fermi Labs, BAE Systems, Alphawave, Intel Foundry,… Read More


PCIe design workflow debuts simulation-driven virtual compliance

PCIe design workflow debuts simulation-driven virtual compliance
by Don Dingee on 07-16-2024 at 6:00 am

PCIe classical workflow

PCIe design complexity continues rising as the standard for intrasystem communication evolves. An urgent need for more system bandwidth drives PCIe interconnects to multi-lane, multi-link, multi-level signaling. Classical PCIe design workflows leave designers with most of the responsibility for getting the requisite… Read More