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The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival

The $725 Million Chip Development: Why Execution Risk, Not IP Cost, Now Dictates Advanced-Node Survival
by Kalar Rajendiran on 11-05-2026 at 6:00 am

The Real Value of Predictable Execution

The philosophy of relying on a single, unified IP stack to lower your total cost of ownership is not a new concept invented just for the AI era. Semiconductor engineering teams have been weighing the trade-offs of piecemeal versus integrated intellectual property sourcing for decades. In previous process generations, veering… Read More


CTO Interview with Taylor Barton of Certus Semiconductor

CTO Interview with Taylor Barton of Certus Semiconductor
by Daniel Nenni on 11-04-2026 at 12:00 pm

Smaller footprint, greater possibility

Taylor Barton is a Lead Analog/Mixed-Signal and I/O IC Design Engineer at Certus Semiconductor, where he has worked since December 2022. He has designed more than 20 silicon-proven I/O and ESD libraries and has led analog and I/O IP projects, including ADC and SerDes designs. Taylor holds B.S. and M.S. degrees in Electrical Engineering… Read More


Ceva’s next NeuPro generation opens new possibilities across AI

Ceva’s next NeuPro generation opens new possibilities across AI
by Daniel Nenni on 11-03-2026 at 8:00 am

CEVA NEUPRO NPU portfolio

Ceva is broadening the possibilities for AI silicon with a new generation of its NeuPro neural processing unit portfolio, bringing a common architecture and unified software environment to applications spanning sensors, intelligent devices and cloud infrastructure.

Announced on October 28, the portfolio reflects an opportunity:… Read More


ML-Based Power Models for CPUs. Innovation in Verification

ML-Based Power Models for CPUs. Innovation in Verification
by Bernard Murphy on 10-29-2026 at 6:00 am

Innovation New

An effective learned power model for a CPU could be a significant advantage in early estimation of power performance against realistic workloads in complex architectures. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A)… Read More


CEO Interview with Lisa Spelman of Cornelis

CEO Interview with Lisa Spelman of Cornelis
by Daniel Nenni on 10-23-2026 at 6:00 am

Lisa Spelman The network as compute

Lisa Spelman is CEO of Cornelis, where she leads the company’s efforts to advance high-performance networking for AI and HPC infrastructure. She brings more than 20 years of experience across AI, cloud, enterprise infrastructure, data center operations, product strategy, and go-to-market leadership.

Before joining Cornelis,… Read More


From Sequential R&D to Trusted Co-Innovation: The EPIC Model for Semiconductor Innovation

From Sequential R&D to Trusted Co-Innovation: The EPIC Model for Semiconductor Innovation
by Kalar Rajendiran on 10-22-2026 at 10:00 am

Gary Dickerson on the Stage

The semiconductor industry has long depended on collaboration between technology developers, equipment suppliers and manufacturers. But as artificial intelligence reshapes computing, established ways of working together may no longer be sufficient. The next wave of innovation will depend not just on what companies develop,… Read More


SEMICON West’s Autonomous Fab Vision Needs a Decision-Escalation Design

SEMICON West’s Autonomous Fab Vision Needs a Decision-Escalation Design
by Admin on 10-22-2026 at 8:00 am

Human approval in an AI cleanroom

By Gleb Tsipursky

SEMICON West 2026’s smart-manufacturing agenda connected digital twins, agentic AI, physical AI, and increasingly autonomous factory operations. The final day included a session on automation and equipment for autonomous facilities. At its October CONNECT conference, PDF Solutions planned demonstrations… Read More


Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks

Arteris FlexGen Opens Up Multi-Die Traffic Management for Non-Coherent Networks
by Bernard Murphy on 10-21-2026 at 6:00 am

MultiDie FlexGen

Last year I wrote about Arteris’ introduction of multi-die support for coherent NoCs. This is a very big deal because hyperscalers and OEMs are now building large systems that depend on multi-chiplet architectures and require efficient traffic management between chiplets, in one case as many as 12 compute, fabric/cache and … Read More


The Industry Challenge: AI Is Forcing Semiconductor Innovation Beyond the Chip

The Industry Challenge: AI Is Forcing Semiconductor Innovation Beyond the Chip
by Kalar Rajendiran on 10-20-2026 at 10:00 am

Partners Photo Op scaled

Applied Materials President and CEO Gary Dickerson with the EPIC Center founding partners on October 12, 2026, in Sunnyvale, CA. (Tomas Ovalle/AP Content Services for Applied Materials, Inc.)The bottlenecks are becoming interconnected

Artificial intelligence is changing what the semiconductor industry must deliver. … Read More


Who Gets to Move the Recipe? How Autonomous Agents Earn Decision Authority in the Fab

Who Gets to Move the Recipe? How Autonomous Agents Earn Decision Authority in the Fab
by Admin on 10-20-2026 at 8:00 am

featured who gets to move the recipe

by Ajay Kumar Govindaram

There’s a question I’ve started asking at every agentic AI demo I sit through, and it has a clean answer in every fab on earth: who is allowed to change the recipe? In a semiconductor factory, that was settled decades ago. A person doesn’t touch a production recipe because they feel confident.… Read More