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CEO Interview with Madhulima Tewari of VerifAIX

CEO Interview with Madhulima Tewari of VerifAIX
by Daniel Nenni on 07-17-2026 at 10:00 am

MadhulimaTewariHeadshot

Madhulima Tewari is the CEO and founder of VerifAIX. After two decades building EDA tools, taping out chips, and working on distributed systems, cloud infrastructure, and enterprise AI applications, she teamed up with chip design and methodology leaders and university researchers to build an agentic AI system aimed at helping… Read More


TSMC’s Raises the Bar on CAPEX!

TSMC’s Raises the Bar on CAPEX!
by Daniel Nenni on 07-17-2026 at 6:00 am

TSMC CAPEX 2026 SemiWiki

On the latest investor call the big story was the increase in CAPEX for 2026 and the expected CAPEX for 2027. TSMC raised the CAPEX ceiling for 2026 from US$56 billion to US$64 billion. My guess would be US$64 billion will be spent if not more. We have been discussing this in the SemiWiki Forum and my guess for the 2027 TSMC CAPEX is an incredible… Read More


PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI Connectivity

PCIe 7 Switch IP with Time Division Multiplexing: Powering the Next Generation of AI Connectivity
by Kalar Rajendiran on 07-16-2026 at 6:00 am

PCIe7 Switch with TDM

PCI Express (PCIe), PCIe switches, Time Division Multiplexing (TDM), Network Interface Cards (NICs), and SmartNICs are all well-established technologies that have formed the backbone of computing and networking systems for years. More recently, SuperNICs have emerged as the next generation of networking devices optimized… Read More


Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?

Consolidation and Competition: Who is Winning the $4.5 Billion Interface IP Race?
by Kalar Rajendiran on 07-09-2026 at 2:00 pm

2025 TSMC Revenue by Platform

The semiconductor landscape is currently undergoing a structural transformation as the “Data-Centric Shift” moves the industry’s center of gravity from smartphones toward High-Performance Computing (HPC) and AI infrastructure.

This transition is clearly validated by TSMC’s 2025 filings, which show… Read More


Beyond Workflow Agents: Toward Design Intelligence in Analog EDA

Beyond Workflow Agents: Toward Design Intelligence in Analog EDA
by ChandraM on 07-09-2026 at 6:00 am

ChandraM LongPost AgenticStack

Over the last year, the EDA industry has started using a new vocabulary: agents, super agents, mental models, native skills, playbooks, RAG, MCP, autonomous workflows, and AI-first design.

The language is new, but the motivation is familiar to anyone who has worked in chip design.

Design complexity keeps increasing. The number… Read More


IP Lifecycle Management in the AI Era

IP Lifecycle Management in the AI Era
by Bernard Murphy on 07-08-2026 at 6:00 am

designer trying to find best IP options in a tangle of choices

Large design enterprises have multiple concurrent activities around IP of various types: software/firmware, blocks defined in RTL or HLS, verification IPs of multiple different types, physical implementations, scripts/files for timing, power management, etc., etc. Each of these continues to evolve and branch to serve … Read More


The Accidental Infrastructure: How Crypto Miners Built the Foundation of the AI Boom

The Accidental Infrastructure: How Crypto Miners Built the Foundation of the AI Boom
by Jonah McLeod on 07-06-2026 at 2:00 pm

shutterstock 772693789

Most crypto forty-niners died broke in a warehouse full of their computing rigs. Former Ethereum miner CoreWeave took its gold to Wall Street. On June 22, 2026, it joined the Nasdaq-100 — fifteen months after its IPO, nine years after its founders assembled their first GPU rig in a New Jersey office.

The people who built the physical… Read More


WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools

WEBINAR: Defacto is Boosting Front-end SoC Design With AI-Powered EDA tools
by Daniel Nenni on 07-02-2026 at 2:00 pm

webinar square AI 2026 v2

The real promise of AI in EDA is not to replace EDA tools or reinvent design flows, it is to help engineers accomplish existing tasks even more complex design tasks faster, more safely, and with far less tool expertise than was previously required.

The webinar explores what a truly effective AI-powered EDA tool should look like, … Read More


Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late

Webinar: Caspia Shows You How to Fix Security Flaws Before It’s Too Late
by Mike Gianfagna on 07-02-2026 at 10:00 am

Webinar Caspia Shows You How to Fix Security Flaws Before It’s Too Late FINAL V2

Chip-level vulnerability is becoming an existential threat for virtually all systems. The time to ensure your chip designs are resistant to these attacks is now. Caspia presented a webinar recently that provides important information on how to build attack-resistant chips. If you missed it, don’t worry. A replay link is coming.… Read More


Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test

Why Real-Time Intelligence is the Next Differentiator in Semiconductor Test
by Mike Gianfagna on 07-02-2026 at 6:00 am

Why Real Time Intelligence is the Next Differentiator in Semiconductor Test

Even with advances in AI, automation, and advanced process technology, many semiconductor test operations still rely on reports generated hours after production has occurred. This creates a significant and growing problem. By the time engineers discover a yield excursion, parametric drift, tester issue, or an increase in… Read More