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From Two Dimensional Growth to Three Dimensional DRAM

From Two Dimensional Growth to Three Dimensional DRAM
by Admin on 08-06-2025 at 10:00 am

Microsoft Word JAP25 AR 00479 art

Epitaxial stacks of silicon and silicon germanium are emerging as a key materials platform for three dimensional dynamic random access memory. Future DRAM will likely migrate from vertical channels to horizontally stacked channels that resemble the gate all around concept in logic. That shift demands a starter material made… Read More


Synopsys Webinar – Enabling Multi-Die Design with Intel

Synopsys Webinar – Enabling Multi-Die Design with Intel
by Mike Gianfagna on 08-04-2025 at 6:00 am

Synopsys Webinar – Enabling Multi Die Design with Intel

As we all know, the age of multi-die design has arrived. And along with it many new design challenges. There is a lot of material discussing the obstacles to achieve more mainstream access to this design architecture, and some good strategies to conquer those obstacles. Synopsys recently published a webinar that took this discussion… Read More


CoPoS is a Bigger Canvas for Chiplets and HBM

CoPoS is a Bigger Canvas for Chiplets and HBM
by Admin on 08-03-2025 at 10:00 am

Chip on Panel on Substrate, often shortened to CoPoS, extends the familiar idea of chip on carrier packaging by moving the redistribution and interposer style structures from circular wafers to large rectangular panels. The finished panel assembly is then mounted on an organic or glass package substrate. This shift from round

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AI-Driven Verification: Transforming Semiconductor Design

AI-Driven Verification: Transforming Semiconductor Design
by Admin on 08-01-2025 at 8:00 am

DAC 62 Systems on Chips

In a DACtv session on July 9, 2025, Abhi Kolpekwar, Vice-President & General Manager at Siemens EDA, illuminated the transformative role of artificial intelligence (AI) in addressing the escalating challenges of semiconductor design verification. The presentation underscored the limitations of traditional methods… Read More


cHBM for AI: Capabilities, Challenges, and Opportunities

cHBM for AI: Capabilities, Challenges, and Opportunities
by Kalar Rajendiran on 07-31-2025 at 6:00 am

cHBM Panelists at Synopsys Executive Forum

AI’s exponential growth is transforming semiconductor design—and memory is now as critical as compute. Multi-die architecture has emerged as the new frontier, and custom High Bandwidth Memory (cHBM) is fast becoming a cornerstone in this evolution. In a panel session at the Synopsys Executive Forum, leaders from AWS, Marvell,… Read More


Enabling the Ecosystem for True Heterogeneous 3D IC Designs

Enabling the Ecosystem for True Heterogeneous 3D IC Designs
by Kalar Rajendiran on 07-28-2025 at 10:00 am

The Shift to System Technology Co Optimization

The demand for higher performance, greater configurability, and more cost-effective solutions is pushing the industry toward heterogeneous integration and 3D integrated circuits (3D ICs). These solutions are no longer reserved for niche applications—they are rapidly becoming essential to mainstream semiconductor design.… Read More


Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC

Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC
by Mike Gianfagna on 07-24-2025 at 6:00 am

Scaling 3D IC Technologies – Siemens Hosts a Meeting of the Minds at DAC

3D IC was a very popular topic at DAC. The era of heterogeneous, multi-chip design is here.  There were a lot of research results and practical examples presented. What stood out for me was a panel at the end of day two of DAC that was hosted by Siemens. This panel brought together an impressive group of experts to weigh in on what was really… Read More


Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 Roadmap

Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 Roadmap
by Daniel Nenni on 07-22-2025 at 6:10 am

Alchip TSMC N2 announcement SemiWiki

Alchip Technologies, a global leader in high-performance computing (HPC) and AI infrastructure ASICs, has officially launched its 2nm Design Platform, marking a major advancement in custom silicon design. The company has already received its first 2nm wafers and is collaborating with customers on the development of high-performance… Read More


Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD Modeling

Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD Modeling
by Kalar Rajendiran on 07-10-2025 at 10:00 am

What is SimLab

The semiconductor industry is rapidly moving beyond traditional 2D packaging, embracing technologies such as 3D integrated circuits (3D ICs) and 2.5D advanced packaging. These approaches combine heterogeneous chiplets, silicon interposers, and complex multi-layer routing to achieve higher performance and integration.… Read More


Dual Strategy of Electroless Metal Deposition and Surface Silylation Toward Scalable Low-Temperature Hybrid Bonding for Advanced Packaging Applications

Dual Strategy of Electroless Metal Deposition and Surface Silylation Toward Scalable Low-Temperature Hybrid Bonding for Advanced Packaging Applications
by Admin on 07-09-2025 at 8:00 am

Hybrid Bonding for Advanced Packaging

In extreme ultraviolet lithography (EUVL) systems, the collector mirror is a critical optical component that gathers and directs EUV light from the source toward the projection optics. Over time, the collector surface accumulates contaminant films — primarily tin (Sn) debris from the laser-produced plasma (LPP) source, … Read More