ARM and a LEG

ARM and a LEG
by Paul McLellan on 11-01-2012 at 5:09 pm

I went to Warren East’s keynote speech at ARM Techcon today. There had been some hints earlier in the week that some significant announcements would be made and, while they were not earth-shattering, I think that they will be significant in the long term.

One interesting thing that Warren pointed out is that the ARM partner… Read More


IBM Tapes Out 14nm ARM Processor on Cadence Flow

IBM Tapes Out 14nm ARM Processor on Cadence Flow
by Paul McLellan on 10-30-2012 at 7:33 pm

An announcement at the ARM conference was of a joint project to tape out an ARM Cortex-M0 in IBM’s 14nm FinFET process. In fact they taped out 3 different versions of the chip using different routing architectures to see the impact on yield.

This was the first 14nm ARM tapeout, it seems. I’m sure Intel has built plenty … Read More


ARM 64-bit

ARM 64-bit
by Paul McLellan on 10-30-2012 at 6:56 pm

AMD announced yesterday that they would be building 64-bit ARM-based chips intended for use in servers. What was unclear is what the processors would be like. Although ARM had announced that they would move into 64-bit processors they didn’t have any that they had actually announced as being available for licensing.

At … Read More


Apple and Samsung Take All the Profit

Apple and Samsung Take All the Profit
by Paul McLellan on 10-29-2012 at 4:07 pm

I’ve talked before about how Apple and Samsung make most of the money in the handset business (and also about how Nokia…er…doesn’t). Now there is a report from Canaccord Genuity makes it clear just how much of the profit they make: 106%. And that is down from second quarter when they made 108%.

How can they… Read More


Jasper Property Synthesis Apps

Jasper Property Synthesis Apps
by Paul McLellan on 10-29-2012 at 7:00 am

Jasper restructured JasperGold so that it could deliver its formal technology more flexibly by having a base system and a porfolio of apps. This would also make it easier to upgrade capabilities by creating new apps. Today, Jasper announced two new apps:

  • JasperGold Structural Property Synthesis (SPS)
  • JasperGold Behavioral
Read More

Brian Bailey Interviews Kathryn Kranen

Brian Bailey Interviews Kathryn Kranen
by Paul McLellan on 10-25-2012 at 6:23 pm

Brian Bailey at EETimes has an interesting interview with Kathryn Kranen. He says that the interview will be published in installments but the first one is up here. This first installment is mostly about how long-lived EDA companies (and others) have become since it takes a long time to build up enough revenue to be able to IPO.

She… Read More


Model Driven Development

Model Driven Development
by Paul McLellan on 10-25-2012 at 5:50 pm

Mentor has a webinar on Model Driven Development (MDD) for Systems Engineering, presented by Bill Chown. It is actually the first of 15 webinars. This first one is just over 30 minutes long and I assume the others will be too. The webinar focuses on embedded system development, which historically has largely been validated using… Read More


A Brief History of Semiconductors

A Brief History of Semiconductors
by Paul McLellan on 10-25-2012 at 3:00 pm

In the last few decades, electronics has become more and more central to our lives. When I was a child the only electronics in the house was the radio and the television, both of which contained tubes. Two big things happened that upended that world: the invention of the transistor and the invention of the integrated circuit. A modern… Read More


CDNLive Call For Papers

CDNLive Call For Papers
by Paul McLellan on 10-24-2012 at 6:44 pm

The Silicon Valley CDNLive, the Cadence user conference, will be on March 12-13th 2013 in Santa Clara. But the heart of CDNLive are customer presentations and the call for papers is now open. The deadline is December 4th (at 5pm PST for people who really like to come down to the wire). At this point only an abstract is required.

There… Read More


Power and Reliability Challenges

Power and Reliability Challenges
by Paul McLellan on 10-23-2012 at 12:38 pm

Last week I attended the Ansys/Apache seminars on “Dimensions of Electronic Design.” The two big challenges as we go down to 28nm and 20nm and below are keeping power manageable and keeping reliability up.

The big challenge with power is that we can put so much stuff on a die and clock it so fast that the power is exceeding… Read More