The Universal Chiplet Interconnect Express™ (UCIe™) 1.0 specification was announced in early 2022 and a UCIe 1.1 update was released on August 8, 2023. This open standard facilitates the heterogeneous integration of die-to-die link interconnects within the same package. This is a fancy way of saying the standard opens the door… Read More
Author: Mike Gianfagna
Intel and Cadence Collaborate to Advance the All-Important UCIe Standard
Analog Bits Momentum and a Look to the Future
Analog Bits is aggressively moving to advanced nodes. On SemiWiki, Dan Nenni covered new IP in 3nm at DAC here. I covered the new Analog Bits 3nm IP presented at the TSMC Technology Symposium here. And now, there’s buzz about 2nm IP to be announced at the upcoming TSMC OIP event in September. I was able to get a briefing from the master… Read More
A Closer Look at Conquering Clock Jitter with Infinisim
As voltages go down and frequencies increase, the challenges in chip design become increasingly complex and unforgiving. Issues that once seemed manageable now escalate, while new obstacles emerge, demanding our attention. Among these challenges, clock jitter stands out as a formidable threat. At its core, clock jitter is… Read More
CAST Advances Lossless Data Compression Speed with a New IP Core
Data compression is a critical element of many systems. Thanks to trends such as AI and highly connected systems there is more data to be stored and processed every day. Data growth is staggering. Statista recently estimated that 90% of the world’s data was generated in the last two years. Storing and processing all that … Read More
Weebit Nano is at the Epicenter of the ReRAM Revolution
It’s well known that flash is the embedded non-volatile memory (NVM) incumbent technology. As with many technologies, flash is bumping into limits such as power consumption, speed, endurance and cost. It is also not scalable below 28nm. This presents problems for applications such as AI inference engines that require embedded… Read More
proteanTecs Introduces a Safety Monitoring Solution #61DAC
At #61DAC it was quite clear that semiconductors have “grown up”. The technology has taken its place in the world as a mission-critical enabler for a growing list of industries and applications. Reliability and stability become very important as this change progresses. An error of failure is somewhere between inconvenient… Read More
CAST, a Small Company with a Large Impact on Many Growth Markets #61DAC
Semiconductor IP has continued to grow as a market, and it was clearly a star performer at #61DAC. We all know the large suppliers of IP for semiconductors, but the market is actually quite diverse, with many players supporting many applications. I had a chance to meet with two executives from CAST, a company with a remarkably … Read More
Samtec Simplifies Complex Interconnect Design with Solution Blocks
The development of cost effective, high-performance silicon to silicon interconnect at the system level can be a vexing problem. So many choices, which one will work best? Ease of use and customer support are woven into the DNA of Samtec. Almost four years ago I explored the company’s focus on putting the customer first here. Fast-forward… Read More
IROC Introduces an Upgraded Solution for Soft Error Analysis and Mitigation #61DAC
#61DAC Is the place to go for the latest ideas, technology and products for semiconductor design and manufacturing. Between the exhibit floor and the technical program, you can get a vast education on almost any topic. In this post, I will focus on a unique company and a new version of a unique solution. IROC Technologies specializes… Read More
How Sarcina Revolutionizes Advanced Packaging #61DAC
#61DAC was buzzing with discussion of chiplet-based, heterogeneous design. This new design approach opens new opportunities for applications such as AI, autonomous driving and even quantum computing. A critical enabler for all this to work is reliable, cost-effective advanced packaging, and that is the topic of this post.… Read More
Unlocking the cloud: A new era for post-tapeout flow for semiconductor manufacturing