The SPIE Advanced Lithography + Patterning Symposium recently concluded. This is a popular event where leading researchers gather. Challenges such as optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications are all covered. This… Read More
Author: Mike Gianfagna
Synopsys Explores AI/ML Impact on Mask Synthesis at SPIE 2026
Qnity and Silicon Catalyst Light a Path to Success at the Chiplet Summit
The Chiplet Summit recently concluded. Multi-die heterogeneous design is a hot topic these days and chiplets are a key enabler for this trend. The conference was noticeably larger this year. There were many presentations and exhibits that focused on areas such as how to design chiplets, what standards are important, how to integrate… Read More
Perforce and Siemens Collaborate on 3DIC Design at the Chiplet Summit
The recent Chiplet Summit at the Santa Clara Convention Center was buzzing with many enabling technologies for chiplet-based design. Collaboration was also on display during many parts of the show. A presentation in the Siemens booth was a perfect example of both of those trends. In the Siemens booth, Perforce presented an excellent… Read More
The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years
The Electronic System Design Alliance (ESDA) has been at the center of the EDA industry through its many changes over the years. It occurred to me that an update on this organization would be useful. ESDA is a technology community within SEMI and is managed primarily by a team of three who coordinate all its activities along with a … Read More
What is the 3nm Pessimism Wall and Why is it An Economic Crisis?
Chip design is getting more difficult as technology advances. Everyone knows that. A lot of the discussion around these issues tends to focus on the demands posed by massive AI workloads and the challenges of shifting to heterogeneous multi-die design. While these create real problems, there is an underlying effect that is making… Read More
Samtec Ushers in a New Era of High-Speed Connectivity at DesignCon 2026
As I’ve discussed before, Samtec has a way of dominating every trade show the company participates in. The upcoming DesignCon event is no exception. At the show, Samtec will be discussing data rates up to 448 Gbps and signals up to 130 GHz. Beyond a rich set of demonstrations in the company’s booth, Samtec engineers will be participating… Read More
The Risk of Not Optimizing Clock Power
Clock power is rarely the issue teams expect to limit advanced-node designs. Yet in many chips today, over-driven clock networks quietly consume disproportionate power, reduce thermal headroom, and can constrain achievable frequency. And all while passing traditional sign-off checks and often remaining locked in through… Read More
Taming Advanced Node Clock Network Challenges: Jitter
Clock jitter rarely fails in obvious ways. In advanced-node designs, its impact is often indirect, emerging through subtle timing uncertainty, interaction with power delivery noise, and compounding effects across large clock networks. These behaviors can quietly erode margin and predictability, even when conventional… Read More
Taming Advanced Node Clock Network Challenges: Duty Cycle
As process nodes advance, circuit behavior becomes progressively more challenging to analyze and predict. Few systems reflect this challenge more clearly than the clock network. These large, complex networks no longer behave as ideal digital signals. Instead, they operate as distributed electrical systems shaped by non-linear… Read More
Siemens EDA Illuminates the Complexity of PCB Design
As heterogeneous multi-die design becomes more prevalent, the focus on advanced analysis has predictably shifted in that direction. While these challenges are important to overcome, we shouldn’t lose sight of how complete systems are built. Short and long reach communication channels, system-level power management and … Read More
TSMC Technology Symposium 2026 Overview