Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC Tools

Synopsys Brings Multi-Die Integration Closer with its 3DIO IP Solution and 3DIC Tools
by Mike Gianfagna on 12-10-2024 at 6:00 am

Synopsys Brings Multi Die Integration Closer with its 3DIO IP Solution and 3DIC Tools

There is ample evidence that technologies such as high-performance computing, next-generation servers, and AI accelerators are fueling unprecedented demands in data processing speed with massive data storage, lower latency, and lower power. Heterogeneous system integration, more commonly called 2.5 and 3D IC design, … Read More


A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design

A Master Class with Ansys and Synopsys, The Latest Advances in Multi-Die Design
by Mike Gianfagna on 12-04-2024 at 6:00 am

A Master Class with Ansys and Synopsys, The Latest Advances in Multi Die Design

2.5D and 3D multi-die design is rapidly moving into the mainstream for many applications. HPC, GPU, mobile, and AI/ML are application areas that have seen real benefits. The concept of “mix/match” for chips and chiplets to form a complex system sounds deceptively simple. In fact, the implementation and analysis techniques required… Read More


How Breker is Helping to Solve the RISC-V Certification Problem

How Breker is Helping to Solve the RISC-V Certification Problem
by Mike Gianfagna on 12-02-2024 at 10:00 am

How Breker is Helping to Solve the RISC V Certification Problem

RISC-V cores are popping up everywhere. The growth of this open instruction set architecture (ISA) was quite evident at the recent RISC-V summit. You can check out some of the RISC-V buzz on SemiWiki here. While all this is quite exciting and encouraging, there are hurdles to face before true prime-time, ubiquitous application… Read More


MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO

MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO
by Mike Gianfagna on 11-27-2024 at 10:00 am

MZ Technologies is Breaking Down 3D IC Design Barriers with GENIO

3D-IC design can be both exciting and frustrating. It’s exciting because it opens a new world of innovation possibilities – opportunities that aren’t constrained by the rules of monolithic chip scaling. It can be frustrating because of the large array of complex technical challenges that must be overcome to make this new paradigm… Read More


One Thousand Production Licenses Means Silicon Creations PLL IP is Everywhere

One Thousand Production Licenses Means Silicon Creations PLL IP is Everywhere
by Mike Gianfagna on 11-25-2024 at 10:00 am

Spread Spectrum Modulator RTL IP provides industry standard and custom modulation patterns for Silicon Creations fractional N PLLs

If you sell sneakers, 1,000 pair is called a humble beginning. On the other hand, selling 1,000 licenses for specialized analog IP is a home run.  Silicon Creations celebrated a home run for a critical piece of analog IP that finds its way into a diverse array of applications. Succeeding in so many markets is noteworthy, and I want … Read More


Silicon Creations is Fueling Next Generation Chips

Silicon Creations is Fueling Next Generation Chips
by Mike Gianfagna on 11-21-2024 at 6:00 am

Silicon Creations is Fueling Next Generation Chips

Next generation semiconductor design puts new stress on traditionally low-key parts of the design process. One example is packaging, which used to be the clean-up spot at the end of the design. Thanks to chiplet-based design, package engineers are now rock stars. Analog design is another one of those disciplines.

Not long ago,… Read More


Alchip is Paving the Way to Future 3D Design Innovation

Alchip is Paving the Way to Future 3D Design Innovation
by Mike Gianfagna on 11-19-2024 at 6:00 am

Alchip is Paving the Way to Future 3D Design Innovation

At the recent TSMC OIP Ecosystem Forum in Santa Clara, there was an important presentation that laid the groundwork for a great deal of future innovation. Alchip and its IP and EDA partner Synopsys presented Efficient 3D Chiplet Stacking Using TSMC SoIC. The concept of 3D, chiplet-based design certainly isn’t new. SemiWiki maintains… Read More


Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit
by Mike Gianfagna on 11-14-2024 at 6:00 am

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

AI is exploding everywhere. We’ve all seen the evidence. The same thing is happening with AI conferences. The conference I will discuss here began in 2018 as the AI Hardware Summit. The initial venue was the Computer History Museum in Mountain View, CA. Like most things AI, this conference has grown substantially in a relatively… Read More


My Conversation with Infinisim – Why Good Enough Isn’t Enough

My Conversation with Infinisim – Why Good Enough Isn’t Enough
by Mike Gianfagna on 11-12-2024 at 6:00 am

My Conversation with Infinisim – Why Good Enough Isn’t Enough

My recent post on a high-profile chip performance issue got me thinking. The root cause of the problem discussed there had to do with a clock tree circuit that was particularly vulnerable to reliability aging under elevated voltage and temperature. Chip aging effects have always got my attention. I’ve lived through a few of them… Read More


PQShield Demystifies Post-Quantum Cryptography with Leadership Lounge

PQShield Demystifies Post-Quantum Cryptography with Leadership Lounge
by Mike Gianfagna on 10-31-2024 at 6:00 am

PQShield Demystifies Post Quantum Cryptography with Leadership Lounge

Post-Quantum Cryptography, or PQC provides a technical approach to protect encrypted data and connections when quantum computers can cost-effectively defeat current approaches. Exactly when this will occur is open to much discussion, but the fact is this day is coming, some say in ten years. One of the imperatives is to deploy… Read More