Transistor-Level Static Checking for Better Performance and Reliability

Transistor-Level Static Checking for Better Performance and Reliability
by Daniel Payne on 05-04-2021 at 10:00 am

power intent checks min

My first transistor-level IC design job was with Intel, doing DRAM designs by shrinking the layout to a smaller process node, and it also required running lots of SPICE runs with manually extracted parasitics to verify that everything was operating OK, meeting the access time specifications and power requirements across PVT … Read More


Small EDA Company with Something New: SoC Compiler

Small EDA Company with Something New: SoC Compiler
by Daniel Payne on 04-26-2021 at 10:00 am

Defacto SoC Compiler

I read the semiconductor press, LinkedIn and social media (Twitter, Facebook) every morning along with an RSS feed that I setup, staying current on everything related to using EDA tools to make the task of SoC design a bit easier for design teams. A recent press release announced a tool called SoC Compiler, so my curiosity was piqued… Read More


Addressing SoC Test Implementation Time and Costs

Addressing SoC Test Implementation Time and Costs
by Daniel Payne on 04-20-2021 at 10:00 am

testmax flow

In business we all have heard the maxim, “Time is Money.” I learned this lesson early on in my semiconductor career when doing DRAM design, discovering that the packaging costs and time on the tester were actually higher than the fabrication costs. System companies like IBM were early adopters of Design For Test (DFT)… Read More


Single HW/SW Bill of Material (BoM) Benefits System Development

Single HW/SW Bill of Material (BoM) Benefits System Development
by Daniel Payne on 02-23-2021 at 10:00 am

Perforce - IP

Most large electronics companies take a divide and conquer approach to projects, with clear division lines set between HW and SW engineers, so quite often the separate teams have distinct methodologies and ways to design, document, communicate and save a BoM. This division can lead to errors in the system development process,… Read More


A Brief History of Perforce

A Brief History of Perforce
by Daniel Payne on 01-28-2021 at 10:00 am

helix core workflow min

In 2020 Perforce acquired Methodics, a provider of IP Lifecycle Management (IPLM) tools, and Daniel Nenni blogged about that in July 2020, but a lot has happened since Perforce was founded in 1995. In the beginning Christopher Seiwald founded Perforce in his Alameda basement based on his background as a software developer, and… Read More


CES 2021 and all things Cycling Technology

CES 2021 and all things Cycling Technology
by Daniel Payne on 01-17-2021 at 6:00 am

bowflex® velocore™ bike 940455

It’s January so time to give you another summary of what I’ve found at CES 2021 about new cycling products that have electronic content. During the pandemic in 2020 we’ve seen a surge in sales for bicycles, e-bikes, spin bikes and trainers as people wanted a simple way of getting around town running errands, or… Read More


Conference: Embedded DevOps

Conference: Embedded DevOps
by Daniel Payne on 01-07-2021 at 6:00 am

embedded devops min

The catchy phrase DevOps is defined by Agile advocates as, “The practice of operations and development engineers participating together in the entire service lifecycle, from design through the development process to production support.

I’ve been developing software since the stone ages, which means… Read More


Analysis of Curvilinear FPDs

Analysis of Curvilinear FPDs
by Daniel Payne on 12-31-2020 at 6:00 am

FPD voltage distribution analysis min

This area of automating the design of Flat Panel Displays (FPD) is so broad that it has taken me three blogs to cover all of the details, so in brief review the first two blogs were:

My final blog covers five areas:

  • DRC/LVS for curvilinear layout
  • Circuit
Read More

Curvilinear FPD Layout and Schematics

Curvilinear FPD Layout and Schematics
by Daniel Payne on 12-03-2020 at 10:00 am

layout ladder min

You are likely reading this blog using a Flat Panel Display (FPD), because they are so ubiquitous in our desktop, tablet and smart phone devices. Today I’m following up from a previous article. A quick recap of the unique design flow for FPD is shown below:

What follows is the second part of a Q&A discussion with Chen Zhao… Read More


Third Generation of IP Lifecycle Management Launched

Third Generation of IP Lifecycle Management Launched
by Daniel Payne on 11-17-2020 at 10:00 am

Methodics and Perforce

Back in July I first read the news that Perforce had acquired Methodics, and wasn’t too surprised, because many of the EDA vendors that we blog about do get acquired or merge with similar sized companies in order to be part of a bigger offering. When Methodics announced a webinar introducing IPLM 3.0 (IP Lifecycle Management),… Read More