Wearables at Linley Mobile: Diverging views

Wearables at Linley Mobile: Diverging views
by Daniel Nenni on 05-08-2014 at 11:30 pm

The Linley Mobile Conference last week initiated a lot of discussion about emerging technologies and markets, especially wearables. Jessica Lipsky’s EE Times article captured some of the sentiments in her article, “Wearables Need Tailored SoCs.” But the conference covered a lot more ground than wearables, including mobile… Read More


Get that Smartphone Chip out of my Wearable!

Get that Smartphone Chip out of my Wearable!
by Daniel Nenni on 05-08-2014 at 11:30 am

Last week, I had the pleasure to present at the Linley Group Mobile Conference. My presentation was part of the Wearable Device Session, which examined wearables from several different angles including software, sensor, processor, and IP.

As the smartphone market is maturing and the pace of innovation generally slowing, there… Read More


Intel is Still Missing Mobile!

Intel is Still Missing Mobile!
by Daniel Nenni on 05-07-2014 at 9:00 am

Paul McLellan was on assignment in Hong Kong last week so I attended the Linley Mobile Conference and was not surprised Intel did not present. During the networking sessions I asked more than a dozen people why and the answers were pretty focused on “Intel still does not play well with others” and “Intel’s current mobile offerings… Read More


New Method for Metrology with sub-10 nm Lithrography

New Method for Metrology with sub-10 nm Lithrography
by Daniel Nenni on 05-06-2014 at 6:00 pm

NewPath Research will describe their new method for nanoscale carrier profiling in semiconductors on May 19[SUP]th[/SUP] at the Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) in Saratoga Springs, NY. This new method is intended to fill the gap that has been addressed in the Roadmaps for the semiconductor… Read More


TSMC Updates: 20nm, 16nm, and 10nm!

TSMC Updates: 20nm, 16nm, and 10nm!
by Daniel Nenni on 05-05-2014 at 2:30 pm

*Spoiler Alert: The Sky is Not Falling*
The TSMC Technology Symposium last month provided a much needed technology refresh to counter aging industry experts (they make their living selling reports) who have been somewhat negative on the future of the fabless semiconductor ecosystem. If the sky wasn’t falling who would… Read More


The Number One ASIC Racing Team!

The Number One ASIC Racing Team!
by Daniel Nenni on 05-04-2014 at 9:45 am

This weekend I was in the pits for the Flying Lizard Motorsports team at the Monterey Grand Prix. It was an auction item (donated by eSilicon) at EDA’s 50[SUP]th[/SUP] Anniversary party last year, and let me tell you it was an amazing experience and a very interesting story, absolutely. But first let me tell you that if you get a “Hot… Read More


Aldec is Celebrating 30 Years @ #51DAC!

Aldec is Celebrating 30 Years @ #51DAC!
by Daniel Nenni on 05-02-2014 at 8:00 am

Dr. Stanley Hyduke founded Aldec in 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Today, Aldec … Read More


Kurt Shuler: Arteris Presentation at EDPS 2014

Kurt Shuler: Arteris Presentation at EDPS 2014
by Daniel Nenni on 04-30-2014 at 9:00 am

The Electronic Design Process Symposium is an annual workshop run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation. I presented there because it’s devoid of product marketing pitches, and is two days of discussion on technical and process issues in SoC design. My slides are here:… Read More


Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance

Tanner EDA Helps Customer Productivity Engineering Increase Efficiency and Lower Cost with No Compromise in Performance
by Daniel Nenni on 04-29-2014 at 10:00 am

Tanner EDA is making waves at their customer’s sites as the mixed-signal design suite from Tanner EDA, Incentia Design Systems, Inc. and Aldec, Inc. helps ASIC Design House lower cost and increase efficiency with no compromise in performance. In today’s ‘always on’, Internet of Things connected world, the demand for high-performance,… Read More


Carey Robertson: Reliability Checks in Advanced Nodes

Carey Robertson: Reliability Checks in Advanced Nodes
by Daniel Nenni on 04-28-2014 at 8:30 pm

Last week I had the pleasure of presenting at the Electronic Design Process Symposium (EDPS) workshop. This was my first time attending and I was very impressed. There were good presentations but I learned as much from the Q&A and the side conversations before/after/breakfast/lunch/etc. If you have the opportunity to attend,… Read More