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112G56G SerDes Select the right PAM4 SerDes for your application

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. Not all SerDes are the same. The presentation covered here, from Cadence, discusses the various flavors of LR, MR/VSR and XSR high speed SerDes and where they fit best. When it comes to 112G/56G SerDes, you really need to select the right PAM4 SerDes for your application.

The presentation was given by Wendy Wu, product marketing director at Cadence. Wendy has also worked in marketing and applications engineering at NetLogic Microsystems, Broadcom and Cavium. Wendy speaks with strong authority on the topic. She began her talk discussing a semiconductor law that is somewhat less know than Moore’s Law, but very relevant. Rent’s rule is based on internal memoranda at IBM from 1960. It basically says that the number of I/O pins tracks the number of gates/transistors. So, functionality increase requires I/O bandwidth to increase. This is why the topic is inherently important.

Wendy then discussed how high-speed interconnect is the backbone of cloud data centers. Higher throughput with lower latency and flat power describe the challenge. Wendy shared an interesting statistic – 85% of the traffic in a typical data center is between compute nodes in that data center.  Data communications is clearly a key item for continued growth in this huge market.

Looking at AI requirements for high-speed comms, 7nm and 5nm are the preferred nodes today, with 3nm around the corner. We are at the cutting edge here. Wendy then discussed the various applications for 56G and 112G SerDes. She touched on four areas:

Long reach: backplane applications – between processors and racks. Drive, performance and signal loss are key parameters here.

Medium reach: chip-to-chip and mid-range backplanes.

Very short reach: chip to module applications.

Extra short reach: die-to-die, system in package applications.

With regard to die-to-die communications, three methods were discussed. This technology is also an enabler for the growing chiplet market. There is the previously discussed PAM4 SerDes approach. NRZ serial interface is another approach. Finally, a parallel interface can be considered, similar to what is used for HBM stacks with a silicon interposer. Each of these approaches has its strengths and weaknesses.

Next, Wendy examined analog vs. digital equalizer architectures. An analog solution delivers better density and lower power but is susceptible to channel noise and can equalize up to 20db of loss. Analog-to-digital, DSP-based approaches are more stable and reliable. They can equalize up to 40db of loss. Traditionally, these solutions have been higher power than analog. Starting at 7nm and below, the power requirements of digital solutions are very similar to analog. With all this background, what is the best approach?  Clearly that depends on the application. Wendy provided a good overview of where each technology fits. This is captured in the diagram below.

Architecture comparison of LR MR VSR abd XSR

Wendy then discussed the 56G and 112G offerings from Cadence, built by a best-in-class engineering team that is strong in both analog and digital techniques. The IP is fully compliant with relevant industry standards. She also pointed out that Cadence works with connector, cable and optical module suppliers to ensure good interoperability. Both 56G and 112G parts are proven with multiple test chips. She explained that the portfolio can support requirements from LR to XSR. These points are illustrated by the graphic at the top of this post.

Wendy went into some detail on the Cadence 112G-LR DSP SerDes. The key advantages are summarized in the figure below.

Cadence 112G LR SerDes Advantages

Wendy concluded with a discussion of the Cadence UltraLink D2D PHY IP. This IP can connect two designs through a multi-chip module or an organic substrate. The figure, below, summarizes the performance parameters of this IP.

Cadence UltraLink D2D PHY IP

You can learn more about  how to select the right PAM4 SerDes for your application and the Cadence IP portfolio here.

[post_title] => 112G/56G SerDes - Select the Right PAM4 SerDes for Your Application [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => 112g-56g-serdes-select-the-right-pam4-serdes-for-your-application [to_ping] => [pinged] => [post_modified] => 2020-09-22 11:06:40 [post_modified_gmt] => 2020-09-22 18:06:40 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291100 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [1] => WP_Post Object ( [ID] => 290720 [post_author] => 16 [post_date] => 2020-09-24 06:00:14 [post_date_gmt] => 2020-09-24 13:00:14 [post_content] => SSD memory is enjoying a new resurgence in datacenters through NVMe. Not as a replacement for more traditional HDD disk drives, which though slower are still much cheaper. NVMe storage has instead become a storage cache between hot DRAM memory close to processors and the “cold” HDD storage. I commented last year on why this has become important for the hyperscalers. Cloud throughput and therefore revenues are heavily impacted by storage latencies, which makes fast storage cache a high priority. Which creates implications for verifying warm memory - proving your solution will deliver what it promises. You start to wonder what other operations you could offload into storage. SQL serving for example. Database operations work on lots of data which can dominate latency (and power) if you first have to drag it all over to the processor. It’s faster and lower power to do the bulk of the heavy lifting right in the NVMe unit. I’ve even seen a recent suggestion that linear algebra could be moved into SQL, from which it would be a short jump to push it into NVMe. Another paper suggests an architecture to accelerate big data computation using this kind of approach. Verifying warm memory

Architecture complexity

It seems there is no limit to what we can do with computation close to storage, when we put our minds to it. All of which makes that NVMe memory much more powerful. The downside is that verifying warm memory implementations, already complex, becomes even more complex. First there’s the architecture complexity. One of these devices may service multiple hosts and many I/O queues. It must provide a similar level of security to that offered by the hosts including at least encryption, perhaps a hardware root of trust and other features to harden the device against attacks.

Implementation complexity

Then there’s the implementation complexity. It must deal with the NVMe interface, encryption, logical to physical address mapping, wear-leveling, garbage collection, interface with local DRAM through DDR (to store data while it’s doing garbage collection) and so on. This is a full-blown processor in its own right.  As if that weren’t enough, you can’t just model the flash as perfect memory. Reading a bit can return a soft error to which the controller must adapt. According to the Mentor Veloce folks, design teams need to model flash bit behavior down to this level of accuracy in order to have full confidence in their system-level testing. Mentor provide soft models for NAND, NOR and DDR to represent these components.

Traffic complexity

Finally, there’s traffic complexity. A verification plan must also model traffic with all the variations you might expect to see in those loads from the host (one or more servers), connected through a PCIe interface. For benchmarking this requires running a standard I/O load like IOmeter, FIO or CrystalMark. Measuring throughput, latencies, all the factors you are aiming to improve through use of warm memories. Put all of this together and you have a big verification task – virtual host and an SSD simulation model which you have to run in emulation to deliver the kind of throughput you need for this volume of verification. Ben Whitehead, Storage Products Specialist at Mentor, has written a white-paper, “Virtual Verification of Computational Storage Devices”, to describe the Veloce solution they have assembled to address this need. With a bunch of application-specific features for measurement, checking and debug.  An interesting read for anyone working in this hot domain. [post_title] => Verifying Warm Memory. Virtualizing to manage complexity [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => verifying-warm-memory-virtualizing-to-manage-complexity [to_ping] => [pinged] => [post_modified] => 2020-09-10 14:02:45 [post_modified_gmt] => 2020-09-10 21:02:45 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=290720 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [2] => WP_Post Object ( [ID] => 291157 [post_author] => 28 [post_date] => 2020-09-23 10:00:42 [post_date_gmt] => 2020-09-23 17:00:42 [post_content] => Mentor Graphics, a Siemens Business, has completed their acquisition of EDA company Avatar Integrated Systems.  I recently spoke with Joe Sawicki, Executive VP of the Mentor IC EDA segment, about the acquisition strategy and IC Design platform goals for integration of the Avatar products. Avatar (formerly ATopTech) focused on physical implementation tools for complex, digital SoC designs – e.g., floorplanning, placement, clock-tree synthesis, routing, and ECO flows.  Specifically, the foundation of the Aprisa Product was to build their physical algorithms on a route-centric, hierarchical data model.  The right-hand side of the figure below highlights the Avatar strategy. route centric architecture mentor avatar The Aprisa SAPR input data is a simple LEF/DEF design model from a (physical-aware) logic synthesis toolset.  From the synthesis netlist, Aprisa applies optimizations that focus on ensuring subsequent routability – e.g., congestion avoidance, pin access, adherence to multipatterning decomposition coloring.  An internal physical DRC verification engine is applied.  A diverse set of clock tree design styles are available, including useful clock skew timing optimizations throughout. aprisa architecture mentor avatar An internal synthesis engine allows for further optimization.  The input netlist placement assumptions may not accurately reflect the route impact of congestion, R*C delays, and clock skews.  Logic restructuring based on the routing model may be needed.  The tool incorporates static timing, noise, IR, and EM analysis algorithms to guide placement and route assignment decisions. internal synthesis Joe indicated, “Designers of complex SoCs at advanced nodes are seeking the following from their APR flow – better synthesis-to-post route timing correlation, no coupling noise issues, no DRC violations, in short, fewer APR iterations and faster time to closure.  We benchmarked Aprisa, and found the PPA results to be excellent.  The learning curve was extremely quick.  We had competitive evaluation data within a few weeks.”  pre to post route correlation The figure above illustrates the pre-route (Steiner estimate) to post-route timing correlation on the Mentor benchmarks at the 7nm node. Joe then described the IC Design product strategy.  “The Nitro-SoC platform will be supported through the 16/14nm node.  Going forward, Aprisa will be the SAPR solution for 7nm and below.  The DRC engine that was internal to Aprisa will be replaced by Calibre InRoute.” InRoute flow Joe continued, “The strength of the combined engineering and support teams will offer roadmap stability and continuity to customers, who may have been anxious given the relatively small size of Avatar’s team.  Mentor will leverage its relationship with the foundries to extend the Aprisa product certification for advanced process nodes.” With regards to the competitive position of the new offering, relative to the integrated platforms available for physical implementation, Joe said, “Designers want an APR tool that is feature-rich and easy to use.  The route-centric data model and optimization algorithms in Aprisa provide faster closure and signoff accurate results.  The use of a physical-aware (placement-centric) synthesis flow is a good start, but the set of optimizations available is a key differentiator, specifically route-aware logic re-synthesis.  Refinement is where you get considerable value.  We’ve already flipped customers from other products.”  It will be interesting to track how Aprisa emerges in the reference flow certification from the foundries, and how the route-centric with logic re-synthesis methodology evolves as a point tool solution.  Mentor’s acquisition of Avatar expands the scope and future development of SAPR offerings.  More competition among EDA providers is always a good thing for the IC design community. [post_title] => Update on Mentor’s Acquisition of Avatar Integrated Systems [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => update-on-mentors-acquisition-of-avatar-integrated-systems [to_ping] => [pinged] => [post_modified] => 2020-09-24 11:37:29 [post_modified_gmt] => 2020-09-24 18:37:29 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291157 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [3] => WP_Post Object ( [ID] => 291182 [post_author] => 28 [post_date] => 2020-09-23 06:00:57 [post_date_gmt] => 2020-09-23 13:00:57 [post_content] => Ansys Ideas 1On the eve of the Innovative Designs Enabled by Ansys Semiconductor (IDEAS) Forum I spoke with Vic on a range of topics including his opening keynote: Accelerating Moore and Beyond Moore with Multiphysics. You can register here Vic Kulkarni is Vice President and Chief Strategist, Semiconductor Business Unit, Ansys, San Jose. CA. Vic is responsible for steering the business, technology, go-to-market and product strategy, connecting the dots from chip-package-system design solutions with ANSYS multi-physics simulation technology to address challenges faced by multiple verticals, including 5G, AI, HPC, mobile and autonomous. He drives strategic customer executive relationships and acquisitions with Ansys leadership team. Q: What are the key trends which are shaping your business? Hi-tech sector remains strong. We are witnessing a renaissance in semiconductor and electronic systems. We see an emerging duality between Moore’s Scaling Law and the Beyond Moore trend. On the one hand, compute-intensive demands by a range of markets - including HPC, cloud, storage, autonomous vehicles, 5G, and ML/AI - are driving scaling feature sizes down to 5à4à and now 3nm as Tier-1 semis and hyper-scalers continue to invest in semiconductors. This is due to increased workloads of HPC cloud compute, networking storage, 5G, AI training and inferencing chips like Google TPU. At the same time, there is an accelerating trend to go Beyond Moore with 2.5/3D ICs, chiplets, and other multi-die configurations driven by edge compute, 3D intelligent sensors for autonomous, and high-bandwidth, low-latency, power, area and cost-sensitive applications. We believe that pervasive multiphysics simulation and analysis in all phases of the design cycle from ideation to lifecycle management will be an important enabler to accelerate innovation and achieve silicon-to-system success. Q: How are customers responding to the pandemic? Despite COVID-19, we kept focusing on our customer support excellence delivery and achieved significant success in pre sales campaigns, customer design tape-outs and customer technical collaboration. A few cash-poor startups are affected by COVID-19, but that's a small fraction of our business. We see a great momentum of our RedHawk-SC flagship PI-SI signoff product in China. We completed 9 evaluations and have several ongoing/planned product evaluations. Automotive electronics remains on track, as these companies continue to invest in R&D that enable autonomy. Final Vic Opening Keynote Ideas 15mins video 091220 Q: Tell me more about your upcoming opening keynote for the IDEAS Digital Forum. Vic took me through his presentation which is a great set-up for the first day. He starts with a brief overview of the Ansys Multiphysics Simulation Platform and moves into the benefits of a simulation-driven design from Concept to Design to Validation and the resulting savings. ANSYS has a broad range of customers so these numbers are VERY impressive. Vic then talks about custom chips by systems companies for differentiation and faster TTM, semiconductor megatrends and technology challenges. The airplane graphic above explains it quite well (ANSYS tools are on the wings). Bottom line: ANSYS is an important part of the leading edge semiconductor ecosystem for simulation, AI/ML, HPC, 5G, hardware security and autonomous vehicles. And while I miss the ANSYS live events (great food and networking) the ANSYS virtual events are must attend, absolutely. ANSYS IDEAS Banner [post_title] => Executive Interview: Vic Kulkarni of ANSYS [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => executive-interview-vic-kulkarni-of-ansys-2 [to_ping] => [pinged] => [post_modified] => 2020-09-24 11:39:08 [post_modified_gmt] => 2020-09-24 18:39:08 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291182 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [4] => WP_Post Object ( [ID] => 291098 [post_author] => 11830 [post_date] => 2020-09-22 10:00:33 [post_date_gmt] => 2020-09-22 17:00:33 [post_content] =>

AIML SoCs Get a Boost from Synopsys IP on TSMCs 7nm and 5nm

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. The presentation covered here from Synopsys focuses on the unique needs of training and inference for AI/ML engines. The algorithms implemented by these designs have very specific requirements. Meeting those requirements demands specialized IP. These special needs and the optimized Synopsys DesignWare IP are discussed to illustrate how AI/ML SoCs get a boost from Synopsys IP on TSMC's 7nm and 5nm processes.

The presentation was given by Faisal Goriawalla, senior product marketing manager at Synopsys. Faisal has over 18 years of engineering and marketing experience in embedded physical IP libraries and non-volatile RAM. He started his career developing embedded SRAM memory compilers and before Synopsys held various technical and marketing positions for memories, standard cells and I/O libraries at ARM. Faisal’s strong background inspires confidence.

Faisal began his presentation focusing on the unique requirements of deep learning and convolutional neural networks (CNNs). He explained that CNNs create a mathematical graph of a problem and train it with a data set of known values. The process begins with training the network, which is compute intensive and then proceeds to inference, where the trained model is deployed. He went into a very good explanation of the requirements of various AI problems with regard to performance, model compression and power. The diagram below summarizes this discussion.

Unique requirements of AI segments

He then explained some of the aspects of a CNN and how it is used to process two-dimensional data. This segment of the presentation provides a very good overview of AI algorithms. I recommend watching it if this is of interest.

Faisal then discussed some of the design challenges for AI chips. Of course, power and area are key items, along with a predictable schedule. He pointed out that an application-aware approach is needed to meet these goals. Some of the items to consider with an approach like this include:

  • Choosing the right mix of VTs-Lg-tracks
  • Converging on an optimal floorplan
  • Managing congestion in multiply-accumulate blocks (MACs)
  • Navigating the RTL to GDSII flow
  • Achieving PPA targets

Faisal went into some detail on these points. The discussion then turned to application-aware IP, what is needed, and what the benefits will be. From an IP component point of view, what is needed to achieve PPA targets includes:

  • Low power memories, especially for Read
  • Low power combo cells to reduce internal energy
  • Complex combinational cells to reduce switching power
  • Special clock gates with lower internal power
  • Granular delay cells to reduce the area and power cost of hold fix
  • Multi-bit flops to reduce active power

From a methodology point of view, what is needed includes:

  • Choice of VT-Lg to give a good starting point on PPA
  • Power recovery post-route to reduce leakage
  • Flow stage correlation never adds >10% to any metric

Faisal then discussed some of the DesignWare IP solutions from Synopsys to address these requirements:

HPC Kit Enhanced for AI Applications

This package includes IP for object detection and recognition. There are special cells to reduce CNN power consumption up to 39%. Tradeoff tuning enables a 7% frequency boost with 28% lower power. The figure below summarizes some of the benefits of the HPC Kit. This IP is typically used for ADAS applications.

Synopsys HPC Kit Benefits

Memory Architectures

The benefits of customizing memory architectures to optimize PPA for AI designs was also discussed. Synopsys offers a wide range of architectures, bitcells, VTs and PVTs here, including:

  • Ultra-high density, high density and high speed
  • Small (128Kb) range register file
  • Large (>1Mb) range SRAM
  • UHD 2-port memories provide FIFO functionality with smaller area & lower leakage at slower speeds
  • Configurable multi-port memories

GPIO Libraries

AI designs are typically core limited (as opposed to pad limited). Inline I/O libraries with a less height and more width form factor are optimal to reduce SoC area for this situation. Synopsys offers DesignWare IO Libraries with:

  • High (up to 250MHz) performance and high drive strengths for additional margin while supporting longer trace lengths
  • Support for 1.8V, 2.5V and 3.3V I/O supplies (technology dependent) for other interfaces on an AI/ML SoC

DFT

The ability to integrate an on-chip test and repair engine is important for reducing area and power in AI applications. The Synopsys STAR Memory System provides this support. Total core area can be reduced by ~7% and dynamic power can be reduced by ~12%.

Conclusion

Faisal concluded by explaining that the IP discussed is silicon-proven in volume at TSMC 7nm and test silicon proven at TSMC 5nm. You can learn more about Synopsys DesignWare IP for AI here. You can access the TSMC OIP presentations here. AI/ML SoCs truly get a boost from Synopsys IP on TSMC's 7nm and 5nm.

[post_title] => AI/ML SoCs Get a Boost from Synopsys IP on TSMC's 7nm and 5nm [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => ai-ml-socs-get-a-boost-from-synopsys-ip-on-tsmcs-7nm-and-5nm [to_ping] => [pinged] => [post_modified] => 2020-09-21 08:20:19 [post_modified_gmt] => 2020-09-21 15:20:19 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291098 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [5] => WP_Post Object ( [ID] => 290760 [post_author] => 16 [post_date] => 2020-09-22 06:00:13 [post_date_gmt] => 2020-09-22 13:00:13 [post_content] => A checker tripped in verification. Is there a bug trace minimization technique to simplify manual debug? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series to highlight all the great research that’s out there in verification. Feel free to comment. Bug Trace Minimization

The Innovation

This month’s pick is Simulation-Based Bug Trace Minimization With BMC-Based Refinement. We found this paper in IEEE Transactions on CAD, 2005. The authors are/were from the University of Michigan. This is an old paper but still intriguing. Debug, tracing back from an identified bug to the root cause, is  the biggest time-sink in verification. Any contribution to reducing that time will have high value. The authors’ approach starts with a waveform trace from a simulation or semi-formal analysis. It aims to reduce the trace to a much shorter trace that still triggers the bug, an easier starting point for manual debug. The paper describes four simulation-based and one BMC-based technique to reduce traces. They first reduce traces by removing cycles, re-simulating each time to check the bug still reproduces. At first glance this looks very unscalable, requiring O(N2) runs for a trace of N cycles. They greatly reduce this complexity first by hashing the circuit state at each cycle. They then watch for hash matches between the original trace and a re-simulation of a candidate reduced trace. If a previously hashed state is hit during re-simulation, they know that the bug can be reached from that hashed state. They can abort the simulation since it can still trigger the bug, i.e. the reduction is proven viable. Through this process they look for any variant trace which triggers the check sooner, which becomes a new and shorter reference trace. Alternatively it may hit a state already seen in an earlier analysis at a later clock cycle. Then this trace can skip ahead, also leading to a shorter reference trace. In a final high-effort simulation step, they also look for opportunities to drop input events (rather than whole cycles), as shown in table 3. Using common datapath functions, FPU, DES and a picoJava engine as benchmarks, the authors show impressive reductions in cycle lengths, better than 98% in most cases and better than 99% in all cases in removing unnecessary inputs. Runtime on most tests was under a minute. The most complex (picoJava) was 10hrs for 30k cycles. Reduced traces were mostly under 10 cycles.

Paul’s view

This reminds me of an earlier paper we discussed “Using AI to locate a fault”. Both combine multiple methods in fault tracing, getting more out of the combination than out of any one method alone. This approach combines five methods, four simulation-based and one BMC-based. The results, e.g. in figure 12, clearly show how different techniques have different impact on different testcases. Which underlines that you really need all these methods. For a commercial vendor this looks very practical, a fusion of methods rather than a single super-method. Tables 5 and 6 show the bulk of reduction coming from simulation methods and a smaller incremental benefit from BMC. Also encouraging for commercial mass deployments given scalability considerations for model-checking. Intuitively the method makes a lot of sense. State hashing and looking for matches will almost certainly be very effective on randomized simulations. It’s the classic computer science random walk problem where the drunken man walking randomly is going to do a lot of circling relative to the amount of actual useful distance moved. All these circles quickly prune away by looking for state hash matches, which should massively reduce practical runtimes. In their experiments picoJava (around 140k gates) ran in 10 hours. That was running a 1GHz Sun blade (2005 remember). Now 3GHz servers are typical, so you’re looking at 500K gates in 10 hours for a single CPU job on a modern server farm. The algorithm is also very parallelizable, so can be scaled up by just farming re-simulation jobs out to multiple servers, sharing the same state hash database. Which makes it very commercially interesting.

Jim’s view

Moving this into the cloud seems a great way to speed up and reach for larger designs. Thinking about it, 10 hours is an overnight run. You could slipstream these runs in behind regression runs. By the time the verification team had a chance to look at them, most or all of those traces would already be reduced. On investment, this naturally fits into the verification suite, so it’s not an independent product. A bit of a challenge is that this is speeding up something engineers already do rather than making something possible that wasn’t possible before. Can it in some way show a huge improvement in productivity? Maybe add an AI angle for 100X improvement over time? That could enhance appeal for an investor.

My view

First, while a lot of good ideas come from software verification, it’s nice to see some coming from hardware verification. Second, I had been looking mostly for recent papers. Paul pushed me to look at some older papers as well. Good intuition! Click HERE to see the previous Innovation blog [post_title] => Bug Trace Minimization. Innovation in Verification [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => bug-trace-minimization-innovation-in-verification [to_ping] => [pinged] => [post_modified] => 2020-09-12 13:07:35 [post_modified_gmt] => 2020-09-12 20:07:35 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=290760 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [6] => WP_Post Object ( [ID] => 290909 [post_author] => 3 [post_date] => 2020-09-21 10:00:25 [post_date_gmt] => 2020-09-21 17:00:25 [post_content] => Oh, our semiconductor industry just loves acronyms, and the title of my blog packs three of the most popular acronyms together at once. I attended a webinar hosted by Aldec last week on this topic, "UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV". Verification engineers have been adopting the Universal Verification Methodology in order to make their verification results more robust, in less time. RISC-V continues to grow in importance as an open source, Instruction Set Architecture (ISA), and at the dac.com site there are some 3,110 search results for RISC-V. I just expect this trend to continue, because engineers often want to customize aspects of their SoC for a specific purpose or domain. A big question then arises on how do you actually verify a RISC-V project. Google has created a SV/UVM based instruction generator for RISC-V processor verification, then posted it on GitHub. There have been some 765 commits, so this is an actively supported instruction generator. There are many RISC-V core projects around the world to choose from, and Ibex is a small, 32-bit RISC-V core, also available on Github with 1,860 commits to date. Using Riviera-PRO Aldec simulates the UVM testbench with the Google DV random instruction generator and Ibex RISC-V core. [caption id="attachment_290910" align="alignnone" width="1256"]UVM Testbench RISC-V Source: https://ibex-core.readthedocs.io/en/latest/verification.html[/caption] In the testbench SV classes are blocks with rounded corners, while SV modules are shown as square corners, finally the code to be run is depicted in blue with folded corners. Random commands come from the Google DV generator, and the testbench also has random interrupts during testing. The co-simulation flow has both an ISS and RTL loaded with test binaries, simulations are run, then the results are compared by a Python script. You can have the same verification experience if you assemble all of the pieces:
  • SystemVerilog simulator that supports UVM (i.e. Riviera-PRO)
  • Instruction Set Simulator (Spike or OVPsim)
  • RISC-V toolchain
Here's the flow of tools and files used for verification: RISC V tool flow The second half of the webinar was showing an actual, live demo of this verification flow in action, running the makefiles, scripts, simulators and comparison on a Linux platform. Batch mode verification was shown first verifying the Ibex core, then GUI mode was run next, and in both cases there were zero mismatches between the ISS and Riviera-PRO simulator results. The GUI for Riviera-PRO had multiple windows: Source code, Classes, Assertions, Messages. In the upper right is the Classes Window, showing instances and hierarchy, methods, properties, derived classes and base classes. Riviera PRO A very useful documentation feature was how a UVM graph could be auto-generated within Riviera-PRO, as it showed memory interface agents, one interrupt agent, connections, and then stepped into instances for more details to understand connectivity. UVM graph An assertions window showed all assertions in one place, without having to look at multiple files, while seeing any failures, passes, and the time when it last happened, quite useful for debugging. Next, the waveform viewer was invoked after restarting simulation, and they added waveforms from the DUT. waveform viewer Finally, they showed the RTL code coverage after simulation had finished, then generated an HTML cumulative summary. code coverage

Summary

RISC-V is one of the biggest topics of 2020 for the electronics industry, and the ecosystem continues to grow each day, but verification can be a burden. Aldec showed in this webinar how their SystemVerilog simulator along with other tools could be used in verifying a RISC-V core called Ibex. I've included links to each open source tool on Github, so go explore on your own and save some verification time, instead of starting from scratch. To watch the archived webinar, visit here.

Related Blogs

[post_title] => WEBINAR: UVM RISC-V and DV [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => uvm-risc-v-and-dv [to_ping] => [pinged] => [post_modified] => 2020-09-21 08:52:24 [post_modified_gmt] => 2020-09-21 15:52:24 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=290909 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [7] => WP_Post Object ( [ID] => 290691 [post_author] => 28 [post_date] => 2020-09-21 06:00:28 [post_date_gmt] => 2020-09-21 13:00:28 [post_content] => MuriloPessatti PhotoMurilo Pilon Pessatti is an Electrical Engineer with a MSEE in Analog IC design. He studied in Brazil at São Paulo University (USP) and earned a masters at Campinas State University (UNICAMP). Murilo then moved to Lisbon in Europe to work for ChipIdea, in the early 2000's when the smartphone era was just taking off. "I had the distinct pleasure to work in one of the first first Analog IP companies, where I had the chance to learn a lot and very fast about Power Management for portable devices. I came back to Brazil and after spending 2 years in a public semiconductor company and decided to start Chipus." Please tell me about Chipus Chipus is a mixed-signal IC design company. We have strong analog expertise, mixed up with significant know-how in digital state-of-the-art technologies. We help our customers to develop the next generation of key IoT, Industrial, Sensors, AI and RF/Optical Communication ASICs. In these almost 12 years since we started the company we had the opportunity to develop almost 400 IPs in mixed-signal areas, tapeout lots of projects, develop very interesting full turn-key ASICs and have a lot of fun working with very challenging and smart customers -- something that really motivates us! What problems does Chipus solve?  Chipus was born with the power-aware mindset. Since the beginning in 2009 when we started building our IP portfolio, we pushed the limits to deliver the lowest power IPs and ASICs. So definitely, when the whole IoT and AI wave hit the market, we were very well positioned to solve all the power related problems based on the IPs and experience we accumulated in the last decade. The key approach and differentiation we have is based on our solid expertise and know-how in operating transistors in weak and moderate inversion. We have both practical ( many tape-outs our team have done dealing with very low power circuits) and solid theoretical experience and background in this field (we are lucky to have a group of researchers in the university very close to us that has developed one of the most accurate charge-based physical models operating in all-region). Adding all of this on top of the portfolio of IPs we have created in the last decade put Chipus in the lead position to solve key power-related problems in IoT and AI to the edge systems and ASICs. We started back in early 2009 building our IP portfolio and as we start gaining credibility from the market by licensing our IPs, our customers start to ask us to help them integrate ours and 3rd Party IPs in their SoCs. We end up not only helping them but also start providing a kind of differentiated design services for customers that really need a high quality team working very close and collaboratively with their SoC architects. At the same time, we start expanding our IP offering, to the point that nowadays we also have high-speed and high-precision building block IPs. Because all these IPs and SoCs had also significant digital blocks, we also built a very experienced digital team that gained a lot of traction in the recent years providing full RTL-to-GDSII flow in state-of-the-art technologies. Last but not least, it was very natural in the last years for Chipus to extend our high quality integration IP services to a complete full ASIC offer, that we start to see a big momentum in different market segments, not only in IoT, industrial but also RF/optical communication. How has the market changed for Chipus in the past 10 years? I see all of the high dynamics in the semiconductor M&A area as a big opportunity to Chipus. But the most important thing for us is to continue doing our high quality work for our customers, even when these customers are merged or acquired by other companies, most of the time we keep working with them, and sometimes our business even grows as they merge with other bigger companies. We are always searching for new challenges and to find out how we can give the best support to our customers, so that all of this market consolidation did not really affect our business and goals as a company. I do believe that IoT, AI to the edge and optical communication are very promising market segments. It is easy to understand: more and more all these "things" are portable and more functionalities need to be done on the edge to be real time. On the other hand, all those things end up putting lots of bits on the internet, which simply cannot afford to use copper anymore. All of this with just some "pico-joules" of energy to make sure batteries last long. That is for me a big opportunity to solve key problems. What type of customers does Chipus look for? We have all types of customers, we never give up to offer the best quality, does not matter the size of the customer, we will be there. We have worked with some small start-ups that end up having very significant exits and become part of big companies. Sometimes we have customers that we license some IPs, sometimes we have customers that need help in a key project in which we come in and increase their capability to solve problems, and sometimes we have customers that want us to develop a full turn-key ASIC. The common point is that in almost all the cases, those customers come back and ask us again for our support. We have some long term customers for who we work constantly and for a long term period. We always see our customers and the business as a relationship and not as a transaction. We expect for a typical customer the same. Time-to-market, first-time-right and price are for sure a big concern from customers. Especially when we have the first interactions with the customers these requirements are more prominent. As far we start the engagement and the trust is developed, things tend to go more smoothly and the most important thing is to be lined up with the long term objectives and goals of the customers. We usually work in very close relationships with our customers long term goals. About Chipus Chipus Microelectronics (ISO 9001:2015 certified) is a semiconductor company focused on the development of mixed-signal ASICs, intellectual property (IP) blocks and IC design services. The company has more than 200 analog IP blocks in process nodes from 22nm to 0.35um of various foundries. Since its foundation in 2008, Chipus has worked with customers worldwide (South and North America, Europe, and Asia) with firm commitment and flexible client support. Besides analog and mixed-signal expertise, Chipus also offers custom digital IC design services having successfully delivered designs in 7nm from RTL to backend. Headquartered in Florianópolis, Brazil, Chipus has a US subsidiary in Silicon Valley and sales teams in both USA and Europe. For additional information on Chipus or its services, please contact us here. [post_title] => CEO Interview: Murilo Pilon Pessatti of Chipus Microelectronics [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => ceo-interview-murilo-pilon-pessatti-of-chipus-microelectronics [to_ping] => [pinged] => [post_modified] => 2020-09-24 11:28:21 [post_modified_gmt] => 2020-09-24 18:28:21 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=290691 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [8] => WP_Post Object ( [ID] => 291115 [post_author] => 29972 [post_date] => 2020-09-20 10:00:46 [post_date_gmt] => 2020-09-20 17:00:46 [post_content] => Moortecs Law No-one likes being put on the spot and yet we all like a forecast…and as we all know, the only guarantee with a forecast is that it is wrong. Sports commentators have carved out a special niche for themselves with the ‘commentators curse’, just as they extol the virtues of an individual or a team, the sporting gods prove them wrong in spectacular fashion! Governments are no better…economic forecasts don’t usually hold for more than a quarter, which is what makes Gordon Moore’s prediction all the more impressive. I’m sure everyone in our industry is familiar with Moore’s Law… while at Fairchild Semiconductor in 1965 he was asked to contribute to the 35th anniversary Electronics Magazine with a prediction for the future of the semiconductor components industry over the next 10 years…his response was ‘the number of transistors in a ‘dense IC’ would double every two years’! What a prediction, it was correct for the next 50 years and is only now starting to ‘fade’, surely the SWAG* to beat all SWAGs?! So what has Moore’s Law got to do with Moortec? Broadly speaking he predicted that over time transistor density would increase, so more could be put on anyone device…and predictably devices would grow. This wasn’t really an issue in the early days, when geometries were measured in micrometres, in fact all the way down to 40nm there weren’t any major issues, it was the transition from planar to FinFET technology where things started to change. The bit Gordon wasn’t too explicit on was the change in leakage current as we ride the geometry wave, leakage current starts to become an issue in FinFET and is just plain ugly sub 7nm, add to which the chip sizes grow significantly as the applications of the day try to maximise the benefits of these plentiful transistors. Ok, big deal…chips get bigger, leakage increases, power density is now also increasing with the ‘end’ of Dennard Scaling, you don’t need to be Nostradamous to predict that things will start to warm up a little. Yet that isn’t the only effect you’ll be seeing, temperature is a first order effect…as the heat rises so data throughput drops, power consumption increases and so the cycle builds on itself.  Second order effects then come into play, the silicon starts to age, reliability takes a hit and can have knock-on effects into your system reliability and overall performance. Great man though he was, Gordon didn’t mention any of that. So here is where Moortec’s Law comes in (just for the record, I’m not claiming it will last 50 years!)…‘the number of sensors used in a ‘dense IC’ will (at least) double per geometry shrink’. There is a second Law (as with Gordon, he too had a second, less well known Law), ‘the number of sensors used in individual designs will rise exponentially as engineers appreciate the information they can divulge in mission mode’! The proliferation of sensors in SoCs will not only be driven by better understanding of the value of the data they provide, but also a deeper appreciation of the type of data they can provide in different areas of a design. Imagine baking a souffle in an oven without a glass door, you are blind to what is happening inside. You’ve followed a recipe and yet you can’t be sure the eggs were a uniform size or the flour was a consistent strength or that the oven holds it’s temperature evenly throughout the cooking process…until you open the oven door, you don’t know what to expect…open it too soon and it will sink, too late and it will have burnt! SoCs are no different, except the cost of failure is many orders of magnitude greater, that ‘mission mode’ visibility the glass door provides is no different from having 10s, 100s or even 1000s of sensors in your device. *Scientific Wild-Ass Guess In case you missed any of Moortec’s previous “Talking Sense” blogs, you can catch up HERE. WEBINAR: Addressing the Challenges of Hyper-scaling within Data Centers with Advanced Node Embedded Sensing Fabrics [post_title] => From Moore’s Law to Moortec’s Law! [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => from-moores-law-to-moortecs-law [to_ping] => [pinged] => [post_modified] => 2020-09-24 11:30:30 [post_modified_gmt] => 2020-09-24 18:30:30 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=291115 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) [9] => WP_Post Object ( [ID] => 290251 [post_author] => 30784 [post_date] => 2020-09-20 06:00:51 [post_date_gmt] => 2020-09-20 13:00:51 [post_content] => Protocol in Depth Ethernet Many times i notice people "kind of afraid" of some protocol, trying to avoid the usage because "it's complicated", I decide to go in-depth in one and show that maybe it's not so complicated after all. First challenge is choosing the protocol and decide about the Ethernet, because this protocol has many challenges in my mind, and it's well-known, old, has many standards, have misconceptions that another protocol, like USB or HDMI don't. WARNING I'll try to show the protocol in low-level (bit level) in few words possible, many things will be missing in this text, so don't use this text to do any ethernet work related. The Ethernet was started in 1973, but only in 1990 was released the standards IEEE 802.3i that is known as Ethernet 10BASE-T or "10Mbit Ethernet", and the first point is that there were some standards before, like the DIX Ethernet, StarLAN and LattisNET. I don't think theses protocols are used today, so I'll ignore them and focus only on the IEEE 802.3i, that I'll call "Ethernet". Other point is the IEEE 802.3 standard, is a collection of standard so, we have Ethernet over Coax cable, twisted pair, Fiber-Optic, and many other options. Again the focus is the 10BASE-T (10 is refer of 10Mbit, the BASE refer signaling BASE or BROAD and T refer twisted pair). The ethernet standard 802.3i will cover only the physical and data link of the OSI model, but in the data link layer will be divided into MAC (media access control) and LLC (logical link control), the 802.3i only cover the MAC layer, don't cover the LLC layer, this is cover in 802.2. For a designer that want to include the ethernet in your project (Considering a IC Designer) you will need design theses. Physical layer (Mostly Analog IC Designer) All communication is transmitted by a differential driver and will have the deal with some encoded data in and out as the control in and out. All data will be encoded in Manchester encode and will communicate in full-duplex or half-duplex. Media Access Control Layer (Digital IC Designer) Uses CSMA/CD control access and will receive and send a frame that will be describe below: 1 - Preamble 2 - SFD 3 - Destination Address 4 - Source Address 5 - Length/Type 6 - MAC Client data / PAD (Payload) 7 - Frame Check Sequence 8 - Extension (optional) 1 - Preamble is a 7 bytes(56 bit) that is sent to allow the PHY layer reaches a steady state, these bytes is: 10101010 10101010 10101010 10101010 10101010 10101010 10101010 2 - SFD is the Start Frame Delimiter show the start of the frame, this is one byte (8 bit): 10101011 3 and 4 - Destination and Source Address, both is an 6 bytes (48 bit), that theoretically represent a unique identifier for each equipment. 5 - This can represent two types of data, in 2 bytes (16 bits) the length or type of the following data. 6 - This is the data to be sent, or message, can be 46 to 1500 bytes long (368 to 12000 bits) and at the end is included a PAD. Any other protocol will be in it. 7 - This is a CRC calculation of the Destination and source address, length/type field and data/pad field, and is attached in the end of data/pad field, that has 4 bytes (32 bits) long. 8 - It's not transmitted in half-duplex mode, is transmitted until complete the time frame. There are many controls and processes that the MAC Layer will execute, but i don't think this will very interesting to show in this post. And there is no way that i can show every detail of the standard in some small internet post. But as you can see, isn't complicated to implement, sometimes it's hard to get some information if it's old, or maybe pay for the standard and understand it. It's totally possible to a designer implement any standard, the most complicated is understand the standard that is written not in a very practical way, this need practice to understand it. [post_title] => Protocol in Depth - Ethernet [post_excerpt] => [post_status] => publish [comment_status] => open [ping_status] => open [post_password] => [post_name] => protocol-in-depth-ethernet [to_ping] => [pinged] => [post_modified] => 2020-09-24 11:31:31 [post_modified_gmt] => 2020-09-24 18:31:31 [post_content_filtered] => [post_parent] => 0 [guid] => https://semiwiki.com/?p=290251 [menu_order] => 0 [post_type] => post [post_mime_type] => [comment_count] => 0 [filter] => raw ) ) [post_count] => 10 [current_post] => -1 [in_the_loop] => [post] => WP_Post Object ( [ID] => 291100 [post_author] => 11830 [post_date] => 2020-09-24 10:00:20 [post_date_gmt] => 2020-09-24 17:00:20 [post_content] =>

112G56G SerDes Select the right PAM4 SerDes for your application

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. Not all SerDes are the same. The presentation covered here, from Cadence, discusses the various flavors of LR, MR/VSR and XSR high speed SerDes and where they fit best. When it comes to 112G/56G SerDes, you really need to select the right PAM4 SerDes for your application.

The presentation was given by Wendy Wu, product marketing director at Cadence. Wendy has also worked in marketing and applications engineering at NetLogic Microsystems, Broadcom and Cavium. Wendy speaks with strong authority on the topic. She began her talk discussing a semiconductor law that is somewhat less know than Moore’s Law, but very relevant. Rent’s rule is based on internal memoranda at IBM from 1960. It basically says that the number of I/O pins tracks the number of gates/transistors. So, functionality increase requires I/O bandwidth to increase. This is why the topic is inherently important.

Wendy then discussed how high-speed interconnect is the backbone of cloud data centers. Higher throughput with lower latency and flat power describe the challenge. Wendy shared an interesting statistic – 85% of the traffic in a typical data center is between compute nodes in that data center.  Data communications is clearly a key item for continued growth in this huge market.

Looking at AI requirements for high-speed comms, 7nm and 5nm are the preferred nodes today, with 3nm around the corner. We are at the cutting edge here. Wendy then discussed the various applications for 56G and 112G SerDes. She touched on four areas:

Long reach: backplane applications – between processors and racks. Drive, performance and signal loss are key parameters here.

Medium reach: chip-to-chip and mid-range backplanes.

Very short reach: chip to module applications.

Extra short reach: die-to-die, system in package applications.

With regard to die-to-die communications, three methods were discussed. This technology is also an enabler for the growing chiplet market. There is the previously discussed PAM4 SerDes approach. NRZ serial interface is another approach. Finally, a parallel interface can be considered, similar to what is used for HBM stacks with a silicon interposer. Each of these approaches has its strengths and weaknesses.

Next, Wendy examined analog vs. digital equalizer architectures. An analog solution delivers better density and lower power but is susceptible to channel noise and can equalize up to 20db of loss. Analog-to-digital, DSP-based approaches are more stable and reliable. They can equalize up to 40db of loss. Traditionally, these solutions have been higher power than analog. Starting at 7nm and below, the power requirements of digital solutions are very similar to analog. With all this background, what is the best approach?  Clearly that depends on the application. Wendy provided a good overview of where each technology fits. This is captured in the diagram below.

Architecture comparison of LR MR VSR abd XSR

Wendy then discussed the 56G and 112G offerings from Cadence, built by a best-in-class engineering team that is strong in both analog and digital techniques. The IP is fully compliant with relevant industry standards. She also pointed out that Cadence works with connector, cable and optical module suppliers to ensure good interoperability. Both 56G and 112G parts are proven with multiple test chips. She explained that the portfolio can support requirements from LR to XSR. These points are illustrated by the graphic at the top of this post.

Wendy went into some detail on the Cadence 112G-LR DSP SerDes. The key advantages are summarized in the figure below.

Cadence 112G LR SerDes Advantages

Wendy concluded with a discussion of the Cadence UltraLink D2D PHY IP. This IP can connect two designs through a multi-chip module or an organic substrate. The figure, below, summarizes the performance parameters of this IP.

Cadence UltraLink D2D PHY IP

You can learn more about  how to select the right PAM4 SerDes for your application and the Cadence IP portfolio here.

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112G/56G SerDes – Select the Right PAM4 SerDes for Your Application

112G/56G SerDes – Select the Right PAM4 SerDes for Your Application
by Mike Gianfagna on 09-24-2020 at 10:00 am

112G56G SerDes Select the right PAM4 SerDes for your application

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. Not all SerDes are the same. The presentation covered here,… Read More


Verifying Warm Memory. Virtualizing to manage complexity

Verifying Warm Memory. Virtualizing to manage complexity
by Bernard Murphy on 09-24-2020 at 6:00 am

Verifying warm memory

SSD memory is enjoying a new resurgence in datacenters through NVMe. Not as a replacement for more traditional HDD disk drives, which though slower are still much cheaper. NVMe storage has instead become a storage cache between hot DRAM memory close to processors and the “cold” HDD storage. I commented last year on why this has become… Read More


Update on Mentor’s Acquisition of Avatar Integrated Systems

Update on Mentor’s Acquisition of Avatar Integrated Systems
by Daniel Nenni on 09-23-2020 at 10:00 am

route centric architecture

Mentor Graphics, a Siemens Business, has completed their acquisition of EDA company Avatar Integrated Systems.  I recently spoke with Joe Sawicki, Executive VP of the Mentor IC EDA segment, about the acquisition strategy and IC Design platform goals for integration of the Avatar products.

Avatar (formerly ATopTech) focused… Read More


Executive Interview: Vic Kulkarni of ANSYS

Executive Interview: Vic Kulkarni of ANSYS
by Daniel Nenni on 09-23-2020 at 6:00 am

Ansys Ideas 1

On the eve of the Innovative Designs Enabled by Ansys Semiconductor (IDEAS) Forum I spoke with Vic on a range of topics including his opening keynote: Accelerating Moore and Beyond Moore with Multiphysics. You can register here

Vic Kulkarni is Vice President and Chief Strategist, Semiconductor Business Unit, Ansys, San Jose.… Read More


AI/ML SoCs Get a Boost from Synopsys IP on TSMC’s 7nm and 5nm

AI/ML SoCs Get a Boost from Synopsys IP on TSMC’s 7nm and 5nm
by Mike Gianfagna on 09-22-2020 at 10:00 am

AIML SoCs Get a Boost from Synopsys IP on TSMCs 7nm and 5nm

This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. The presentation covered here from Synopsys focuses on the… Read More


Bug Trace Minimization. Innovation in Verification

Bug Trace Minimization. Innovation in Verification
by Bernard Murphy on 09-22-2020 at 6:00 am

innovation min

A checker tripped in verification. Is there a bug trace minimization technique to simplify manual debug? Paul Cunningham (GM, Verification at Cadence), Jim Hogan and I continue our series to highlight all the great research that’s out there in verification. Feel free to comment.

The Innovation

This month’s pick is Simulation-BasedRead More


WEBINAR: UVM RISC-V and DV

WEBINAR: UVM RISC-V and DV
by Daniel Payne on 09-21-2020 at 10:00 am

UVM Testbench RISC-V

Oh, our semiconductor industry just loves acronyms, and the title of my blog packs three of the most popular acronyms together at once. I attended a webinar hosted by Aldec last week on this topic, “UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV“. Verification engineers have been … Read More


CEO Interview: Murilo Pilon Pessatti of Chipus Microelectronics

CEO Interview: Murilo Pilon Pessatti of Chipus Microelectronics
by Daniel Nenni on 09-21-2020 at 6:00 am

MuriloPessatti Photo

Murilo Pilon Pessatti is an Electrical Engineer with a MSEE in Analog IC design. He studied in Brazil at São Paulo University (USP) and earned a masters at Campinas State University (UNICAMP). Murilo then moved to Lisbon in Europe to work for ChipIdea, in the early 2000’s when the smartphone era was just taking off.

“I… Read More


From Moore’s Law to Moortec’s Law!

From Moore’s Law to Moortec’s Law!
by Tim Penhale-Jones on 09-20-2020 at 10:00 am

Moortecs Law

No-one likes being put on the spot and yet we all like a forecast…and as we all know, the only guarantee with a forecast is that it is wrong. Sports commentators have carved out a special niche for themselves with the ‘commentators curse’, just as they extol the virtues of an individual or a team, the sporting gods prove them wrong in … Read More


Protocol in Depth – Ethernet

Protocol in Depth – Ethernet
by Luigi Filho on 09-20-2020 at 6:00 am

Protocol in Depth Ethernet

Many times i notice people “kind of afraid” of some protocol, trying to avoid the usage because “it’s complicated”, I decide to go in-depth in one and show that maybe it’s not so complicated after all. First challenge is choosing the protocol and decide about the Ethernet, because this protocol… Read More