Senior Hardware Design Verification Engineer F/H

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

Key Responsibilities:

• Definition, documentation, development, and execution of RTL verification test/coverage for extremely parametrized IPs in Python and C++ language, able to run on any available RTL simulator (Cadence, Synopsys, etc.).
• Maintain and enhance the verification flow, improve metrics, and increase automation.
• Implement verification components such as BFMs or monitors used in verification test benches

Experience Requirements / Qualifications:

• 7+ years of industry experience as a Verification engineer
• Understanding of Hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, SystemVerilog)
• Strong experience in using and developing verification methods and infrastructure (VIPs, UVM, test benches, EDA tools)
• Experience in formal proof verification methodology is a plus
• Shell scripting
• Knowledge of interconnect technology is a plus
• Understanding of Hardware communication protocols (AMBA, OCP, others)
• Good written and verbal communication skills in both French and English
• Curious, autonomous, rigorous, and delivery-oriented with a commitment to quality and a thorough approach to the work.
• Proven ability to work well within a team
• Bilingual in French and English

Education Requirements:

• Master’s degree Computer Science/Electronics