Junior RTL Design Engineer

Your role and responsibilities

Working in the Secure Silicon Engineering department, you will join a team of electronics and digital design engineers. You will be responsible of the development and delivery of IPs targeting FPGA and ASIC technologies.

You will be responsible of:

Maintenance and improvement activities:

• Increase competence in IP portfolio design;
• Migrate SVN IP repositories to GIT;
• Report and fix design bugs / validation;
• Enhance IP hardware scripts/environments;
• Enhance existing functionalities;
• Develop and maintain internal tools;
• Assist in the delivery of configurable or customized IPs;
• Customer support;

Design/verification activities:

• Participate in defining IP architecture;
• Analyze and write specifications and standards;
• RTL coding (VHDL/Verilog/SystemVerilog);
• Design verification (Testbench , UVM);
• Write internal and external documentation (doc, latex);
• Verify code quality;

Prototyping activities (emulation/FPGA):

• Develop synthesizable IP models for FPGA targets;
• Support the Software and Integration teams;

Education, Experience & Skills

• Master degree in electronics/microelectronics or equivalent;
• You have initial experience in a similar position (including internships and work-study programs);
• To join our multicultural environment, technical English is a must;
• You have skills in RTL IP design flow (VHDL or Verilog) for FPGA or ASIC targets.
• You have skills in coding scripts in a Linux environment (Makefile, python, shell, tcl…etc).
• Experience in security/cryptography is a plus
• Knowledge of UVM verification methodology is a plus

Secure-IC is committed to equal opportunity and diversity. Our positions are therefore open to people with disabilities. Only skills and motivation make a difference.