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MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO

MZ Technologies is Breaking Down 3D-IC Design Barriers with GENIO
by Mike Gianfagna on 11-27-2024 at 10:00 am

Key Takeaways

  • MZ Technologies is focused on tackling the complex challenges of 2.5D and 3D IC design through advanced EDA software, particularly with their product GENIO.
  • The upcoming roadmap for GENIO includes significant enhancements for 2025, specifically targeting thermal and mechanical stress issues in chip design.
  • MZ Technologies has established itself as a pioneer in the co-design tool market, reinforcing its commitment to continuous innovation in the EDA community.

MZ Technologies is Breaking Down 3D IC Design Barriers with GENIO

3D-IC design can be both exciting and frustrating. It’s exciting because it opens a new world of innovation possibilities – opportunities that aren’t constrained by the rules of monolithic chip scaling. It can be frustrating because of the large array of complex technical challenges that must be overcome to make this new paradigm accessible. MZ Technologies’ mission is to conquer 2.5D & 3D design challenges for next generation electronic products by delivering innovative, ground-breaking EDA software solutions and methodologies. MZ’s flagship product is GENIO, and the company recently announced a comprehensive roadmap for it. If 2.5 & 3D design are in your future, this is big news. Let’s examine how MZ Technologies is breaking down 3D-IC design barriers with GENIO.

What’s Coming

GENIO™ is an integrated chiplet/packaging co-design EDA tool. The announced roadmap calls for improvements to the product throughout 2025, starting with four significant additions that will be unveiled in mid-January.  Other new features will be added around the middle of the year and at year’s end.

The features coming at the beginning of the year address some truly difficult design challenges. The focus is thermal and mechanical stress. These enhancements will also include an improved and modernized user interface.  

These new features tackle next-generation 3D-IC design challenges head-on.  To provide some background, 3D heterogeneous devices suffer from thermal stress that comes from uneven heat distribution during operation, potentially leading to warping and even reliability failures. To address thermal challenges, robust management strategies are essential. Application of the right tools will minimize temperature differentials. The result is optimal performance and longevity of the chiplets used in the design.

Mechanical stress can result from processes such as thermal expansion mismatch and substrate flexing. These effects can cause interconnect failures and even delamination. A robust approach is needed to maintain structural integrity and performance across varying operational conditions and material interfaces. The new version of GENIO delivers enhanced capabilities in both areas. Mid-year, the company is expected to add additional thermal and interconnect features to GENIO.

Anna Fontanelli
Anna Fontanelli

These enhancements build on the momentum already achieved by GENIO. Anna Fontanelli, Founder and CEO of MZ Technologies commented, “MZ Technologies rolled out the first commercially available co-design tool three years ago and we feel an obligation to the EDA community to continue to innovate.”

What’s Already Here

MZ Technologies has already released several enhancements. GENIO 1.7 saves even more design time than the previous version thanks to its ability to track and classify potential design process issues.

Using a dedicated, always-on dock, the newest version alerts designers to a full list of problems classified by severity, scope, and category. This extensive check provides a real-time update after any operation and new violations are added to something called the Issues Dock. The user can select an issue in this dedicated dock and all errors and warning are highlighted with a severity-driven color across the GUI and the 2D/3D design views. The amount of data associated with 2.5 & 3D design is massive and this feature helps to manage that complexity.

The new version performs several categories of checks, including placement rules during floor planning to catch violations such as overlapping instances, out of boundary placement, and ignored keep-out zones. Other checks spot vertical routing connectivity issues such as broken nets and crossing fly lines. The graphic as the top of this post shows an example of this capability.

To Learn More

MZ Technologies provides automated solutions that facilitate the design and optimization of complex, heterogeneous IC systems. You can learn more about this unique company on SemiWiki here. You can read the full text of MZ Technologies roadmap announcement here. And you can find out more about GENIO here. And that’s how MZ Technologies is breaking down 3D-IC design barriers with GENIO.

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