Standard cell library developers are faced with a daunting task when it is time to create a library for a new process node. Porting an existing library can be a big help, but even then, manual modifications to 800 or more cells is still required. Each of those cells has many geometric elements are that affected by new design rules. All edits and changes have to be adjusted so that the results are DRC clean. In some cases, any advantage coming from reuse might be negated by the amount of effort required for porting.
I recently viewed a webinar by Silvaco on the topic of automating standard cell library porting. Their Cello tool helps with layout migration, layout optimization and standard cell layout creation. Because they use the same tools internally for their standard cell library development and porting services, Cello has evolved based on real world experience. The webinar pretty thoroughly shows how Cello is used to not just to port, but also used to modify cell libraries for specific requirements in areas like Automotive or DFM.
The webinar was hosted by Guilherme Schlinker, Director of Layout Automation at Silvaco. Guilherme made the point early on that in most standard cell libraries there are many cells that might not require special attention, and that there is a smaller set of critical cells that will require hand tuning. Cello frees up skilled library developers to work on the most critical cells while it handles the bulk of the porting effort. Cello has features that include an intuitive GUI cockpit, Tcl scripting, 2D compaction and spacing, built in macros, distributed jobs, and export to GDS, LEF, CDL and LPE. It is integrated with Virtuoso and Custom Complier, or users can use its native layout editor.
The process starts with a proportional scaling of the layout to the new feature size. This is followed by rule specific sizing to ensure that the output is DRC correct. This includes things like enclosure and spacing rules. Additionally, if needed, versions of the cells with increased enclosure can be easily produced for higher reliability applications such as automotive, etc.
Another important element of the porting process is ensuring that there is correct pin accessibility. Silvaco’s Cello takes a unique approach by adding virtual vias and then running DRC checks. In advanced processes via spacing rules can be more restrictive than metal spacing rules. It is painful to learn later that a seemingly DRC correct cell is not usable due to pin accessibility issues. Another interesting application for this technology is in looking at the effect of design rule changes on library performance. It’s relatively straightforward to apply library wide changes and then look at changes in cell or design characteristics.
Also during the webinar Guilherme talked about some of their migration projects. In one instance their Foundation IP Team used Cello to convert ~600 cells from 180nm to 130nm in only 5 days. This included review and fine tuning by a single engineer. He estimated that they benefited from a 10X speed up when compared to manual migration. It’s worth mentioning that Cello works equally well for FinFET processes or planar CMOS.
Fortunately, the webinar is archived on the Silvaco website and available for on-demand viewing. The video goes into much more detail about the user interface, geometry output and the features for controlling the results. I suggest taking a look to get a complete picture of Cello’s capabilities.