Modeling and Analysis of Single Event Effects (SEE)

Single Event Effects (SEE) are important because we depend upon our consumer, industrial and aerospace products to work reliably. Protons, electrons, neutrons, or alpha particles may perturb the MOS or bipolar device operation in either a destructive or non-destructive fashion. Galactic cosmic rays are one source of these particles and by the time they reach Earth we have 10’s of particles per square cm. Even packaging materials have alpha particles as sources for SEE.

Today I attended a webinar from Silvaco and presented by Dr. Christopher Nicklaw about the SEE topic. Dr. Nickaw is a chief engineer with 35 years experience working on radiation effects in materials and has earned a BS in Electrical Engineering, MS in Electrical Engineering, MBA and Ph.D.

Non-destructive events are:

• Single event transient
• Single bit upset
• Multi bit upset

Destructive events are:

• Single Event Latchup
• Single Event Gate Rupture (SEGR)
• Single Event Burnout

Here’s a picture to show how a charged particle strikes the IC surface at a PN junction and creates a temporary ionization trail:

Physicists have derived the Linear Energy Transfer (LET) equation to describe the stopping power of a material to absorb these particles.

LET approximates how the particles will penetrate into our silicon material. To calculate a Soft Error Rate (SER) you can create a model and use IC manufacturing numbers:

Analyzing SEE with TCAD tools can be done if you have access to the process technology, device info, compact models and SPICE circuit simulation.

Silvaco has a TCAD tool called Victory that can model SEE effects like SEGR:

In the research literature Beck has written about SEGR failure mechanisms starting back in 2008:

All of these SEE effects can now be modeled and simulated in the following Silvaco tool flow:

The Victorytool handles the TCAD process and device specification details, Utmost IVcreates compact models for SPICE simulation, Gatewayrepresent schematics, Experthandles IC layout geometries and SmartSpice is the SPICE circuit simulator. The combination of all six EDA tool capabilities are required to design and analyze for SEE effects.

Single Event Currents occur when an ION passes through a MOS device, creates a funnel, in turn causing a single event current.

To mitigate these SEE effects you can harden the process or use IC layout and circuit techniques.

As an example, consider a 22nm SRAM Cell designed with TCAD tools and then analyzed. Here’s the 3D layout and corresponding single event current simulation results.

In the Silvaco environment you can simulate the SEE effects by adding a .RAD statement to your SPICE netlist.

Webinar Q&A

Q: At what technology node does multi-bit show up?

About 130nm is where we first saw that effect, now it is increasing at each smaller node.

Q: Do I need to be a radiation engineer to understand this?

It’s best to know circuit design first, so you don’t have to become a radiation expert, you really just need to know how to simulate the effects. The reliability engineer should be your expert in SEE.

Q: Does a power device failing in a terrestrial setting matter?

Yes, with silicon carbide diodes for the power industry.

Q: What about SEL (Single Event Latchup) in detail?

This effect has mostly gone away with improved technology, this is no longer a dominant effect.

Q: What is the upset mechanism in SOI? Is it supported by Silvaco?

SEE is in Silvaco tools now for SOI technology.

Q: What about thermal neutrons and boron 10?

Yes, boron 10 is still around and these slow neutrons have some effect. Mostly it has gone away because fabs now use boron 11 instead.

Summary
SEE happens both in space and on earth to change the behavior of CMOS and Bipolar transistors, so to maintain high reliability you must account for SEE by using a tool flow that spans: TCAD, process level, device level, compact modeling, IC layout and SPICE circuit simulation. View the full 52 minute recorded webinar here.

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