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Perforce at the 2025 Design Automation Conference #62DAC

Perforce at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-16-2025 at 10:00 am
Categories: EDA, Events, Perforce

62nd DAC SemiWiki

Stop by the Perforce booth to learn about our new partnership with Siemens and get a demo of the latest enhancements in Perforce IPLM, P4, and VersIC. We’re eager to hear about your current challenges and how our semiconductor design and data management solutions can ease your design and development hurdles. Plus, you can try your hand at PLINKO to win some new Perforce swag and scan your badge for your chance to win a pair of Bose QuietComfort headphones!

Find Us at Booth #1227 in the First Floor Exhibitor Hall

Schedule a 1:1 Meeting

DAC attendees can skip the line by pre-scheduling a demo or Q&A session with a Perforce expert. To ensure we connect, schedule your meeting now:

Book my DAC session

Two Key Presentations

Vishal Moondhra, Perforce VP of Solutions Engineering, returns for two informative sessions on the future of chip design:

Building Trust in GenAI for Semiconductor Design: Addressing Data Provenance, Quality, and Traceability Challenges

Monday, June 23 | 3:30pm-4pm PDT | Exhibitor Forum, Level 1 Exhibit Hall

Learn how to establish a secure, compliant, and controlled approach to training AI models to ensure model reproducibility, reliability, and accountability. This session will offer solutions to the critical issues of IP provenance and traceability in order to mitigate risks and foster trust in AI adoption. Learn more

Engineering the Semiconductor Digital Thread

Wednesday, June 25 | 12:00pm-12:30pm PDT | Exhibitor Forum, Level 1 Exhibit Hall

Co-presented with Michael Munsey, VP of Semiconductors and Electronics, Siemens Digital Industries Software, this session will explore the concept of the Semiconductor Digital Thread—a holistic, integrated approach to managing the complete semiconductor lifecycle in the era of software-defined design. Learn more

Happy Hour Networking and Celebration

On Tuesday, June 24th  from 3:00pm to 5:00pm, join us for a beer or two to celebrate our new partnership with Siemens. Come by the Perforce booth thirsty for updates and libations. This is a great opportunity to meet our team, make new connections, and get your questions answered.

Additional Resources

For more about Perforce at DAC 62, visit our event page. On our website, you’ll also find webinars, white papers, and other resources to help you learn more about our unified solution for semiconductor design and data management.

DAC registration is open.

Also Read:

Video EP1: A Discussion of Meeting the Challenges to Implement Gen AI in Semiconductor Design with Vishal Moondhra

The Transformation Model for IP-Centric Design

Chiplets and IP and the Trust Problem

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Silvaco at the 2025 Design Automation Conference #62DAC

Silvaco at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-16-2025 at 8:00 am
Categories: EDA, Events, Silvaco

62nd DAC SemiWiki

Please join us at the Design Automation Conference 2025 where we will highlight the company’s wide range of EDA products and semiconductor IP  targeting, Power Devices, Automotive, Memory, Displays, HPC, 5G / 6G, and IoT applications.

When: June 23 – 25, 2025, Exhibit Hours: 10:00 AM PDT – 6:00 PM PDT

Where: Moscone Center West, Booth 2323, San Francisco, CA

Meet with Silvaco experts to learn about our latest developments and technologies in EDA tools for Analog Custom IC design analysis and verification, automated cell library creation and optimization, and our broad portfolio of design IP.

Theater Presentations

​​​​​​Stop by our booth and attend one of our technical presentations to learn more about our products. Everyone who attends one of our presentations will receive a free gift and a raffle ticket. Prizes include Apple AirPods and the JBL Go 4, an ultra-portable, waterproof, and dustproof Bluetooth speaker. Raffles are held twice daily, so don’t miss your chance to win!

AI Takes EDA to the Next Level – Presented by Dr. Walden “Wally” C. Rhines

Additional presentations by Silvaco experts covering:
– Advanced Memory Compiler Solutions for Your Next SoC
– Accelerate Your SPICE Simulator Performance with Jivaro Pro!
​​​- Boost Productivity with Automated Cell Library Creation and Optimization
– Accelerate Debug, Reduce Cycles with Viso
– Achieve Higher Yield with Smarter Variation Analysis

Click Here to View the Presentation

Schedule: https://go.silvaco.com/SilvacoDAC2025

To schedule a meeting with our experts please contact sales@silvaco.com

Silvaco is looking forward to seeing you at DAC 2025 !!

About Silvaco
Silvaco is a provider of TCAD, EDA software, and SIP solutions that enable semiconductor design and AI through software and innovation. Silvaco’s solutions are used for process and device development across display, power devices, automotive, memory, high performance compute, foundries, photonics, internet of things, and 5G/6G mobile markets for complex SoC design. Silvaco is headquartered in Santa Clara, California and has a global presence with offices located in North America, Europe, Brazil, China, Japan, Korea, Singapore, and Taiwan.

DAC registration is open.

Also Read:

TCAD for 3D Silicon Simulation

CEO Interview: Dr. Babak Taheri of Silvaco

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Silicon Creations at the 2025 Design Automation Conference #62DAC

Silicon Creations at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-16-2025 at 6:00 am
Categories: Events, IP, Silicon Creations

62nd DAC SemiWiki

Silicon Creations provides world-class IP for precision and general-purpose timing (PLLs and oscillators), high-performance multi-protocol and protocol-specific SerDes, high-speed I/Os, and accurate PVT sensors. Applications include high performance computing for AI, smart phones, wearables, consumer devices, network devices, automotive, IoT, and medical devices.

Majority of the world’s top 50 IC companies work with Silicon Creations. Nearly 2,000 chip designs contain the company’s IP, drawn from a portfolio of over 700 unique IP products. The company supports more than 150 production tape-outs annually and has worked with over 500 customers globally. Its IP is in mass production down to 3nm, with N2 IP already taped out on several customer chips.

This year, Silicon Creations is celebrating another banner year of customer SoCs heading to mass production. In 2024 alone, the company’s IP was deployed on 171 tape-outs, helping to produce nearly 1.8 million wafers in collaboration with TSMC, the world’s largest dedicated semiconductor foundry. Silicon Creations continues to expand its advanced portfolio to support GAAFET processes across TSMC, Intel, Samsung, and Rapidus.

Visit Silicon Creations at DAC 2025 Booth #2425

This year at DAC, Silicon Creations will highlight:

  • Innovative temperature sensor IP available in TSMC 3nm and 2nm, with expansion to other nodes underway
  • PCIe SerDes solution
  • Die-to-die PLLs for UCIe PHYs from 2nm and up
  • Reference clock generator PLLs for 112/224G Ethernet and PCIe5/6/7 PHYs
  • All-digital loop control, jitter-optimized LC PLL, now available from 2nm (Samsung) and 3nm (TSMC, Intel) up to 22nm (GF)

Be sure to stop by booth #2425 to see the latest demos and pick up a Silicon Creations wafer coaster. To schedule a private demo or meeting at DAC, reach out here.

You can explore the full lineup of Silicon Creations’ high-performance IP here.

About Silicon Creations

Silicon Creations is a self-funded, leading silicon IP developer with offices in the US and Poland, and sales representation worldwide. The company provides world-class silicon intellectual property (IP) for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance SerDes and high-speed differential I/Os for diverse applications including smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices. Silicon Creations’ IP is proven and/or in high-volume mass production in process technologies up to the most advanced available in the industry.

DAC registration is open.

Also Read:

Silicon Creations Presents Architectures and IP for SoC Clocking

2025 Outlook with Randy Caplan of Silicon Creations

One Thousand Production Licenses Means Silicon Creations PLL IP is Everywhere

Silicon Creations is Fueling Next Generation Chips

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Certus Semiconductor at the 2025 Design Automation Conference #62DAC

Certus Semiconductor at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-15-2025 at 10:00 am
Categories: Certus Semiconductor, Events, IP, TSMC

62nd DAC SemiWiki

Certus Semiconductor Brings High-Performance Custom I/O and ESD IP to DAC 2025

Certus Semiconductor, a trusted leader in custom I/O and ESD solutions, will exhibit at booth #1731 during DAC 2025, June 23–27 in San Francisco. Known for its robust, customer-proven IP tailored for challenging applications, Certus will highlight its extensive portfolio of high-speed, multi-voltage, and specialty I/O libraries that deliver seamless integration and outstanding protection across advanced nodes.

With over 16 years of experience, Certus specializes in developing custom I/O and ESD solutions for a wide range of high-performance interfaces—WiFi, Cellular, HDMI, LVDS, USB, XAUI, and up to 256Gb SerDes—while supporting harsh environments like automotive, industrial, and aerospace.

Certus recently joined the TSMC Open Innovation Platform® (OIP) IP Alliance, enabling the company to apply its custom I/O and ESD technology to TSMC’s advanced process nodes and deliver optimized, foundry-aligned IP to a broader base of SoC developers.

At DAC 2025, Certus will demonstrate how its IP portfolio supports:

  • Multi-protocol and multi-voltage I/O libraries for simplified integration across a wide voltage and protocol range
  • Combo GPIOs supporting interfaces like I²C/I³C/SPI/LVCMOS/HSTL/SSTL/eMMC
  • High-voltage and ultra-high-voltage (10V, 20V+) ESD protection on low-voltage CMOS for analog, RF, and MEMS applications
  • Custom die-to-die and high-speed SerDes I/O solutions with industry-leading low capacitance and robust ESD performance
  • Radiation-hardened and automotive-grade solutions across process nodes from 180nm down to 12nm

Certus’s IP is designed for performance, reliability, and ease of use—backed by expert technical support and a deep understanding of customer integration needs. Whether you’re working on ultra-low-power sensor interfaces or high-speed SoC interconnects, Certus offers IP that’s built to meet your design challenges head-on.

Visit Certus at DAC 2025 (booth #1731) to see how their cutting-edge custom I/O and ESD solutions can streamline your next chip design.

Learn more at www.certus-semi.com

DAC registration is open.

Also Read:

EP177: The Certus Approach to Meeting the Challenges of I/O and ESD with Stephen Fairbanks

The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries

CEO Interview: Stephen Fairbanks of Certus Semiconductor

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Easylogic at the 2025 Design Automation Conference #62DAC

Easylogic at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-15-2025 at 8:00 am
Categories: Easy-Logic, EDA, Events

Easylogic DAC 2025

EasylogicECO Provides Built-In Stage-Based Functional ECO Flows to Reduce Turnaround Time

HONG KONG — June 6, 2025 — EasyLogic proudly introduces a groundbreaking stage-based ECO design environment, built into the EasylogicECO tool, to meet the rapidly evolving functional ECO (Engineering Change Order) demands of today’s ASIC design industry.

These stage-based flows simplify functional ECO operations through built-in modules that address both functionality changes and alignment with the user’s ASIC design flow.  With the inclusion of these new features, EasylogicECO has demonstrated a reduction in ECO turnaround time by more than 50% compared to traditional approaches.

Dr. Sean Wei, CEO of EasyLogic Technology, emphasizes the importance of this new offering: “In any functional ECO scenario, designers face a layered challenge. First comes the complexity of implementing logic changes. Then, each design stage—synthesis, DFT, floorplanning, and place-and-route—requires its own variation of the ECO logic. Finally, every change must be verified before the flow can advance. These challenges accumulate quickly, threatening both the schedule and silicon quality.

By offering flexibility, speed, and deep flow integration, EasylogicECO turns ECO into a manageable, streamlined part of the ASIC design lifecycle — empowering teams to respond quickly to change without compromising quality or design intent.”

Figure 1: An example of the layered challenge in an ECO operation

With a stage-aware architecture designed to align with the user’s ASIC design process, EasylogicECO provides five built-in functional ECO flows, each designed to mirror a common ASIC flow scenario. Each stage in the ECO flow consists of an operation module with embedded functionality and configurable switches, and all modules in the same design flow are tightly integrated. This allows users to further control their ECO results based on specific application needs.

Figure 2: Stage-based ECO design modules built-in into EasylogicECO

From an application perspective, each built-in flow reflects a typical ASIC design flow scenario.  Examples include:

  • 1-stage ECO flow (Blue): Ideal for small digital circuitry, such as mixed-signal ASIC designs.  This flow supports fast-turnaround environments where ECO requests occur frequently but remain localized, and ECO windows are short.
  • 2-stage ECO flow (Green): Designed for streamlined handoffs between traditional front-end and back-end design teams, where the front-end covers RTL design, synthesis, and DFT phases.
  • 2-stage ECO flow (Yellow): This second variant of the two-stage flow supports designs that require an RTL handoff to the implementation team during the design process.
  • 3-stage ECO flow (Orange): Perfect for very large-scale digital ASICs, such as mobile application processors or network switches.  This flow targets a well-defined ECO process involving separate RTL design and DFT teams, as well as back-end implementation.  Result verification is performed at the synthesis and DFT stages before committing back-end changes to minimize risk.
  • 4-stage ECO flow (Purple): Tailored for ultra-large ASIC designs such as GPUs or AI server chips, this flow excels in environments where the chip comprises many replicated or hierarchical blocks. It includes a floorplanning step to adjust the patch logic before place and route (P&R) using physical guidance — particularly when the distance between blocks impacts patch timing.

EasyLogic will showcase its new functional ECO environment at DAC 2025, taking place June 22–25 in San Francisco (Booth # 2521). Visitors are encouraged to schedule detailed discussions in advance to explore how EasylogicECO can be seamlessly integrated into their design environments.  To get in touch, please use our Contact Us form at https://www.easylogiceda.com/en/contact.html.

DAC registration is open.

Also Read:

ECO Demo Update from Easy-Logic

CEO Interview: Dr. Sean Wei of Easy-Logic

 

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AMIQ EDA at the 2025 Design Automation Conference #62DAC

AMIQ EDA at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-15-2025 at 6:00 am
Categories: AMIQ EDA, EDA, Events

62nd DAC SemiWiki

AMIQ EDA is a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis. We’ve been attending DAC for many years now, and it remains one of our most important shows. We love catching up with old friends in the industry, and we always meet lots of engineers who are potential users. We also stay a few extra days before or after the event to meet with our current users at their offices.

DAC is also a great opportunity for us to show off all the new features we’ve added to our products since the last show. This year there’s a lot for us to discuss and demonstrate. The biggest addition to our Design and Verification Tools (DVT) IDE family is AI Assistant. As we discussed in an interview a few months back, this new feature leverages the knowledge in a large language model (LLM) and in our own design and testbench database to make it easier for users to generate, modify, and understand code.

We do have a chat option, but this is way more than a generic chatbot. Our database is specific to the user project and company, so we can use that information to yield better responses. Users can ask AI Assistant to explain or improve code, and to generate new code for desired functionality. All code can be checked for accuracy by the IDE and our Verissimo SystemVerilog Linter. We support whatever LLM the user chooses, and we take multiple steps to ensure that confidential project information does not leak to third-party LLMs.

We support the two major IDE platforms, and we’ve aligned DVT Eclipse IDE and DVT IDE for Visual Studio (VS) Code even closer in terms of functionality. We’ve added more than 30 new code checks within the IDE to ensure code quality. Beyond those big items, we’ve improved testbench elaboration time, expanded debug capabilities, and enhanced our support for power intent files. Although we’ve been shipping DVT IDE since 2008, there’s no shortage of new ideas from our users and our developers. It just gets even better every year.

Speaking of Verissimo, we also add features to our linter all the time. We include around 60 new rules each year, and we’ll be showing the 2024-2025 additions at DAC. We’ve also enabled fast incremental linting, since users want lint checks in addition to IDE checks whenever they add or edit code. They can check their code as they write it without having to open separate windows or jump back and forth. Finally, we’ve added an intuitive ruleset editor to make it easy to customize which rules to run when, including during incremental linting.

Our Specador documentation generator has some new improvements as well. We’ve integrated it more closely with DVT IDE, including the ability to preview the HTML page for a design or verification element interactively. AI Assistant can generate descriptions for user code, and Specador builds high-quality documents including those descriptions. We focus on this type of connection between our products, in addition to adding new features.  We want our users to have the best overall experience possible to produce better code more quickly and easily.

DAC will move to Long Beach next year, so this is a good opportunity to visit San Franscisco. We invite you to stop by our booth to say hello, ask questions, see a demo, or whatever you’d like. We look forward to seeing you there!

Contact AMIQ EDA

DAC registration is open.

Also Read:

2025 Outlook with Cristian Amitroaie, Founder and CEO of AMIQ EDA

Adding an AI Assistant to a Hardware Language IDE

Writing Better Code More Quickly with an IDE and Linting

Podcast EP291: The Journey From One Micron to Edge AI at One Nanometer with Ceva’s Moshe Sheier

Podcast EP291: The Journey From One Micron to Edge AI at One Nanometer with Ceva’s Moshe Sheier
by Daniel Nenni on 06-13-2025 at 10:00 am

Dan is joined by Moshe Sheier, Ceva’s vice president of marketing. Moshe brings with him more than 20 years of experience in the semiconductor IP and chip industries in both development and managerial roles. Prior to this position, Mr. Sheier was the director of strategic marketing at Ceva.

Dan explores the history of Ceva with Moshe and how that history has created a strong force in the industry. Moshe describes the many markets and application areas that Ceva supports for edge computing, including DSP, audio, radar, vision and motion in the sensing area and inference with its scalable NPU architecture. This flexible and scalable architecture allows Ceva to support many customers in the implementation of efficient workloads from low power to safety critical.

Moshe describes the experience Ceva has developed over 10 years with its scalable NPU development, delivering consistent performance and efficiency improvements while also ensuring its hardware and software are future-proof. Its self-contained hardware architecture and broadly adopted software allow Ceva to deliver end-to-end solutions across many markets and customers.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview with Krishna Anne of Agile Analog

CEO Interview with Krishna Anne of Agile Analog
by Daniel Nenni on 06-13-2025 at 6:00 am
Categories: Agile Analog, CEO Interviews, IP

Agile Analog Krishna Anne headshot photo

Krishna has over 30 years of expertise in the semiconductor industry, holding senior roles at Rambus, AMD and Broadcom. As a serial entrepreneur, he co-founded SCI Semi Ltd and previously established DataTrails and Secure Thingz.

 Tell us a bit about your career background. What are you most proud of?

Over the course of my 30 year career in the global semiconductor industry, I have been fortunate to work across a broad range of roles. My first job was as a digital circuit designer, then I gradually transitioned into marketing, business development and corporate management positions with major semiconductor players such as Rambus, AMD and Broadcom. I am proud of the fact that I have been able to draw on my extensive experience, network and industry knowledge to help establish cutting-edge companies, including SCI Semiconductor, DataTrails and Secure Thingz.

Why did you decide to join Agile Analog?

I was invited to advise Agile Analog on its product roadmap and Go-To-Market strategy. After spending time with the team and technology I was highly impressed by the capabilities of the Composa tool and the quality of IP generated through the automation platform. The strength of customer engagements and recent project deliveries further validated the company’s great potential. I am passionate about working with entrepreneurial teams, and Agile Analog represents a unique opportunity to leverage my experience in engineering, GTM and P&L management to help drive revenue growth and scale the business.

What key problem is Agile Analog solving?

The shortage of skilled analog engineers in the semiconductor industry is a significant problem. Composa addresses this gap by enabling the rapid automation, design and redesign of mixed-signal IP blocks – whether adapting to changing specifications or migrating across process nodes. This is a solution the industry has long been waiting for – helping to radically reduce the complexity, time and costs associated with traditional analog design.

What are your main focus areas and challenges over the next six months?

Agile Analog offers an expanding portfolio of IP across data conversion, power management, IC monitoring, security and always-on IP. Over the next six months, the focus will be on building strategic industry partnerships and delivering integrated subsystem level IP solutions. There is clear market demand for our customizable, process agnostic products. As a lean organization, our key challenge is prioritizing our roadmap and aligning our efforts with the industry verticals that present the greatest potential for scalable growth.

What markets and applications are the company’s strongest?

Agile Analog has secured business wins across a wide range of verticals and applications, including consumer, enterprise data centers, security, space and industrial sectors. Analog security IP and anti-tamper IP are a big focus for us at the moment. Security has become a critical consideration for every SoC being developed today and our security IP products are ideally suited to address this.

What new product developments are your team working on?

The Agile Analog team is working to expand our portfolio of security IP and anti-tamper IP beyond our existing voltage glitch detector and clock attack monitor IPs, in order to be able to detect a wider range of physical attacks. Another important area for us is developing our range of data conversion solutions to include higher resolution and higher sample rate solutions. We are seeing great interest in our existing products across process nodes and we are just about to start working on bringing our ADC to the latest TSMC node for one of our strategic customers.

What is the long-term vision for Agile Analog?

Agile Analog’s unique technology, Composa, is our key differentiator from other analog IP companies. With the power of automation, we can quickly deliver IP tailored to precise specifications and process nodes. Our vision is to become the leading provider of high-value analog subsystem IP and licensable automation tools that enable accelerated IP development.

Which industry events are Agile Analog attending this year and why?

2025 has already been a busy year for Agile Analog, with the team taking part in many of the major foundry events held by Intel, TSMC and Samsung. In late June we will be at DAC and then in the second half of the year we will be going to the GlobalFoundries events, as well as more TSMC events. It’s pretty full-on!

Contact Agile Analog

Also Read:

2025 Outlook with Christelle Faucon of Agile Analog

Overcoming obstacles with mixed-signal and analog design integration

Agile Analog Partners with sureCore for Quantum Computing

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Caspia Technologies at the 2025 Design Automation Conference #62DAC

Caspia Technologies at the 2025 Design Automation Conference #62DAC
by Mike Gianfagna on 06-12-2025 at 10:00 am
Categories: AI, Caspia Technologies, Events, Security

Caspia Technologies at the 2025 Design Automation Conference

Security will be an important topic at DAC this year. The hardware root of trust is the foundation of all security for complex systems implementing AI workloads. Thanks to new and sophisticated techniques the hardware root of trust is now vulnerable and must be protected. But adding deep security verification to existing design flows is challenging. Security experts are needed, and there just aren’t enough people with the requisite skills to make an impact.

Caspia is changing this by combining massive data about weaknesses and vulnerabilities with unique GenAI technology to deliver expert security verification to all teams and all design flows. You can learn more about Caspia’s ground-breaking approach to security verification at several events during DAC.

Sunday Workshop

Two of Caspia’s founders, Dr. Mark Tehranipoor and Dr. Farimah Farahmand, along with Dr. Hadi Mardani Kamali will host the Third AI/CAD for Hardware Security Workshop at DAC on Sunday, June 22, from 9:00am – 5:00pm in room 3001 on level 3 of Moscone West.

Building on the success of the first and second CAD for Security Workshops, this third workshop aims to embrace the transformative intersection of AI, CAD, and hardware security. The goal is to drive innovation at the intersection of AI-driven solutions and hardware design security.

Tuesday SKYTalk

Dr. Mark Tehranipoor, co-founder of Caspia Technologies will present an inspirational SKYTalk in the DAC Pavillion (second floor of Moscone West) on Tuesday, June 24 from 1:00 – 1:45pm entitled Opening a New Innovation Frontier with Large Language Models for SoC Security.

As complex SoCs become prevalent in virtually all systems, these devices also present a primary attack surface. The risks of cyberattacks are real, and AI is making them more sophisticated. As we also deploy AI into the SoC design process, it is imperative that secure design practices are incorporated as well.

Existing security solutions are inadequate to provide effective verification of complex SoC designs due to their limitations in scalability, comprehensiveness, and adaptability. Large Language Models (LLMs) are celebrated for their remarkable success in natural language understanding, advanced reasoning, and program synthesis tasks.

Recognizing this opportunity, Dr. Tehranipoor proposes leveraging the emergent capabilities of Generative Pre-trained Transformers (GPTs) to address the existing gaps in SoC security, aiming for a more efficient, scalable, and adaptable methodology. In this presentation he will offer an in-depth analysis of existing work, showcasing achievements, prospects, and challenges of employing LLMs in SoC security design and verification tasks

Meet with Caspia Executives and Technologists

Caspia will have senior architects and executives on hand to provide demos and discuss Caspia’s GenAI security capabilities at the InterContinental Hotel on June 23 and 24. On Monday, June 23 at 4:30 you can also meet with the company’s Chairman of the Board, Dr. Wally Rhines during a special happy hour event.

If you’re interested in reserving a spot for a discussion/demo or to attend the happy hour, drop a note to Caroline McCarthy at cmccarthy@caspiatechnologies.com. Please mention you saw the invitation on SemiWiki.

To Learn More 

You can learn more about Caspia’s ground-breaking security technology in this interview with the company’s CEO on SemiWiki. You can also visit the Caspia website here.  See you at DAC.

DAC registration is open.

Also Read:

CEO Interview with Richard Hegberg of Caspia Technologies

Podcast EP245: A Conversation with Dr. Wally Rhines about Hardware Security and Caspia Technologies

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Defacto at the 2025 Design Automation Conference #62DAC

Defacto at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-12-2025 at 8:00 am
Categories: Defacto Technologies, EDA, Events

62nd DAC SemiWiki

Defacto has been a leading provider of SoC integration tools for large-scale designs for years. Most major semiconductor companies already use their solutions, and several customers will be presenting how they leverage the Defacto solution (SoC Compiler) at the upcoming DAC conference.

This year, Defacto is announcing a major release of their tool: SoC Compiler 11.0. We just blogged about it—check it out here.

This new version reaches a new level of automation. The tool can now interoperate with IP configuration tools and auto-connect IPs to generate a complete SoC ready for both simulation and logic synthesis in minutes. Format complexity isn’t an issue for Defacto’s SoC Compiler, since it can digest and generate RTL (System Verilog, Verilog & VHDL), IP-XACT, UPF, and SDC formats.

With this major release, IP-XACT users will find compelling reasons to migrate to Defacto. The Defacto tool has reached a production level of maturity while covering all essential IP-XACT mechanisms including packaging, querying, linting, checking, assembling, editing using TGI, and reporting (memory maps, registers, etc.) – all while maintaining a strong link with RTL.

Another key differentiator of the Defacto tool is physical awareness of the generated RTL, pre-synthesis. Specifically, Defacto software can capture physical requirements to improve PPA by providing design refactoring and restructuring capabilities.

With this major release, Defacto demonstrates that very complex design hierarchy manipulations can be performed incredibly quickly.

At this year’s DAC, they’ll be presenting a poster jointly with Arm on Monday, June 23, where Arm will explain how they restructured an 18,000-instance design with millions of connections and multiple hierarchy levels in less than an hour.

They’ve even been selected to participate in the DAC Poster Gladiator competition (also on Monday, June 23).

The presentation title is: A New Methodology to Generate Multiple SoC Configurations Quickly

Last but not least, Defacto is unveiling AI-based capabilities at this DAC. They’ve built an AI assistant to help with tool usage, and more importantly, assist Defacto users to easily generate Tcl and Python scripts. They’ll be providing live demonstrations at their booth.

You should definitely stop by their booth on the first floor (booth #1527). They have delicious French chocolates to sample.

How do you find them at DAC? They typically have a giant ball floating above their booth—you can’t miss it on the first floor.

Make sure to contact them here to schedule a meeting at their booth. Hope to see you there!

DAC registration is open.

Also Read:

SoC Front-end Build and Assembly

Video EP8: How Defacto Technologies Helps Customers Build Complex SoC Designs

2025 Outlook with Dr. Chouki Aktouf of Defacto