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Perforce at DAC, Unifying Software and Silicon Across the Ecosystem

Perforce at DAC, Unifying Software and Silicon Across the Ecosystem
by Mike Gianfagna on 07-15-2025 at 6:00 am
Categories: AI, EDA, Events, Perforce

Perforce at DAC, Unifying Software and Silicon Across the Ecosystem

As the new name reflects, chip and system design were a major focus at DAC. So was the role of AI to enable those activities. But getting an AI-enabled design flow to work effectively across chip, subsystem and system-level design presents many significant challenges. One important one is effectively managing the vast amount of data used for these activities. There was one company at DAC that is quietly enabling these efforts. It’s reach is impressive. I had the opportunity to speak with two of the leaders at Perforce at DAC to see how the company is unifying software and silicon across the ecosystem.

The Big Picture

These folks provided a great overview of what Perforce is doing, with some important context about the impact of the work.

Vishal Moondhra

Vishal Moondhra, VP of Solutions Engineering at Perforce. Vishal has over 20 years of experience in digital design and verification. His career includes innovative startups like LGT and Montalvo, and large multinationals such as Intel and Sun. In 2008, Vishal co-founded Missing Link Tools, which built the industry’s first comprehensive Design Verification management solution, bringing together all aspects of verification management into a single platform. Missing Link was acquired by Methodics Inc. in 2012 and by Perforce in 2020.

 

Mike Dreyer

Mike Dreyer, Director, Partners and Alliances at Perforce. Mike has nearly 30 years of experience in sales and partner management across several companies and industries. He has been with the Perforce organization for 10 years. Prior to Perforce, he managed global strategic accounts at Mentor Graphics.

We began by discussing what’s involved in uniting software and silicon in the context of system design. A big issue is managing the vast amount of data generated by AI systems across the entire system development flow. Handling the sheer volume of information is one challenge. Keeping track of what metadata version belongs to what IP block version is another. Without solid version control, sophisticated AI algorithms could be making decisions with the wrong or inconsistent data sets, creating deep and hard-to-find problems.

Vishal and Mike explained that this is an area where Perforce is helping many design teams across many organizations with two key products.

Perforce IPLM provides a hierarchical data model that unifies software and semiconductor metadata. This provides immutable traceability from requirements through design to verification. When deployed across the enterprise, a foundation for an intelligent AI-powered platform capable of real-time data analytics to drive informed design decisions is created.  It was pointed out that IPLM can manage all kinds of IP across a system design, from an AND gate to an airline seat. The implications of unifying this much of the system design is quite significant.

Perforce P4 delivers high-performance data management and version control. P4 provides the infrastructure for fast, scalable, and secure collaboration across globally distributed teams. I’ve worked on large design projects across several countries, and I can tell you the most sophisticated design flow will simply fall apart if the data management backbone can’t keep up.

These capabilities are deployed today across a wide range of companies, design teams and projects. You could say that Perforce is quietly enabling the AI revolution. Citing names is always tricky in these discussions, but Vishal and Mike were able to share an impressive list of customers that includes Micron, Analog Devices, SK Hynix, Skyworks, and Cirrus Logic.

The Siemens Connection

There was another example of Perforce collaboration across the ecosystem in a press release leading up to DAC, Perforce Partners with Siemens for Software-Defined, AI-Powered, Silicon-Enabled Design.  Described as a “partnership to unify software and semiconductor development”, the release describes how Perforce Software, the DevOps company for global teams seeking AI innovation at scale, is partnering with Siemens Digital Industries Software to transform how smart, connected products are designed and developed. Siemens was part of many conversations at DAC related to system design and AI. I covered the company’s announcement of the Siemens EDA AI System on SemiWiki here.

The work announced in the Perforce press release provides important infrastructure to enable forward-looking efforts such as this. The press release provides a good perspective for the impact of this work as follows:

As software and semiconductor teams converge around shared tools and methodologies, there is a critical need for a cohesive platform for concurrent design, development, and verification. This approach enables greater agility in architectural decision-making, accelerates verification, and ensures full traceability from initial requirements through to implementation and validation. Perforce’s IPLM and P4 solutions provide the foundation for this unified development environment.

To Learn More

It is clear that chip design and system design are converging. It is also clear that AI will be a big part of that design revolution. If these trends are impacting your work, it is essential to understand how the pieces work together and where critical enabling technology fits. Perforce is a key supplier of that enabling technology. You can read the full text of the Siemens partnership press release here. And you can learn more about how Perforce IPLM and P4 work together here.  And that’s how Perforce is unifying software and silicon across the ecosystem.

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Double SoC prototyping performance with S2C’s VP1902-based S8-100

Double SoC prototyping performance with S2C’s VP1902-based S8-100
by Daniel Nenni on 07-14-2025 at 10:00 am
Categories: EDA, Prototyping, S2C EDA

pic 1

As AI, HPC, and networking applications demand ever-higher compute and bandwidth, SoC complexity continues to grow. Traditional 50M ASIC equivalent gate FPGA prototyping systems have become less effective for full-chip verification at scale. Addressing this challenge, S2C introduced the Prodigy S8-100 Logic system, powered by AMD’s Versal™ Premium VP1902, offering 2× performance and enhanced deployment efficiency for ultra-large SoC designs.

S8-100 vs. LX2 Benchmark

S2C ran a head-to-head benchmark using the Openpiton 192Core project—a highly complex, multi-core SoC design. This comparison evaluated the performance of the VP1902-based S8-100Q against the previous generation LX2 platform across key prototyping metrics:

Metric S8-100Q (4× VP1902) LX2 (8× VU19P) S8-100 Advantage

 
Design Size (Total) 268.74M gates

(based on usage)

 249.02M gates

(based on usage)

 ✔ Same design workload
Cut Size 25,002 54,990 ✔ Simplified topology
Post-PR Frequency (MHz) 9.4 4.6 ✔ 2× performance

Despite equivalent logic capacity, the S8-100Q achieved 2× higher operating frequency, reduced cascading complexity, and minimized design constraints—leading to faster bring-up and more efficient debug cycles.

Test Conditions:
  • S2C PlayerPro-CT 2024.2 via fully automated, timing-aware partitioning
  • Xilinx Vivado 2024.2 for synthesis and implementation
  • Global optimization techniques enabled, including TDM-awareness, clock domain balancing, and resource co-optimization
Performance Advantages

1) Architecture Enhancement

  • Delivers ~2× logic density
  • 2×2 die layout reduces longest possible signal path from 3 to 2 hops—improving timing closure

2) Streamlined Partitioning & Cascading

  • Higher per-FPGA capacity reduces chip-to-chip interconnects
  • Fewer SLR crossings minimize congestion and simplify routing

3) Low-Latency Interconnect Fabric

  • I/O latency is reduced by 36% of that in UltraScale+ systems
Smarter Prototyping with Integrated Toolchains

The S8-100 isn’t just powerful—it’s intelligently automated. S2C’s PlayerPro-CT toolchain tightly integrates with the hardware, offering:

  • One-click flow from RTL to bitstream
  • Optional manual refinement for advanced tuning
  • Timing and Architecture-aware optimizations

The combination of the S8-100 and new PlayerPro-CT features dramatically cuts setup time, boosts resource efficiency, and accelerates project time-to-market.

Field-Tested and Deployment-Ready

The S8-100 has been deployed in advanced-node SoC programs across AI acceleration, edge computing, and data center. Its proven performance, scalable architecture, and reduced engineering overhead make it a trusted choice for complex SoC projects.

With 2× logic density, simplified interconnects, and a tightly integrated toolchain, the S8-100 delivers a major leap forward in FPGA-based prototyping—empowering engineering teams to confidently prototype, validate, and iterate faster than ever before.

For more information, please visit: www.s2cinc.com.

About S2C

S2C is a global leader in FPGA prototyping solutions, providing scalable, reliable, and flexible hardware platforms that accelerate system validation and software development for semiconductor companies worldwide. For more information, visit www.s2cinc.com.

Also Read:

Enabling RISC-V & AI Innovations with Andes AX45MPV Running Live on S2C Prodigy S8-100 Prototyping System

Cost-Effective and Scalable: A Smarter Choice for RISC-V Development

S2C: Empowering Smarter Futures with Arm-Based Solutions

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Silicon Valley, à la Française

Silicon Valley, à la Française
by Lauro Rizzatti on 07-14-2025 at 6:00 am
Categories: AI

image001 (4)

Since the fall of the Roman Empire, France has played a defining role in shaping Western civilization. In the 9th century, Charlemagne—a Frank—united much of Europe under one rule, leaving behind a legacy so profound he is still remembered as the “Father of Europe.” While Italy ignited the Renaissance, it was 16th-century France that carried its torch across the continent, elevating the arts and laying the groundwork for broader cultural transformation.

The Age of Enlightenment and the subsequent Age of Reason, both rooted in French intellectual movements, revolutionized thinking across philosophy, science, and governance. The French Revolution helped dismantle aristocratic privilege and paved the way for the rise of the bourgeoisie. Even Napoleon, despite the chaos he unleashed across Europe, gifted the world the Napoleonic Code—an enduring foundation for modern legal systems.

In every domain—from science to medicine, philosophy to administration—France has left a deep and lasting imprint on the modern world.

So what happens when French intellectual rigor meets the fast-paced ecosystem of Silicon Valley?

That question was answered—quietly but impactfully—by a French disrupter headquartered in Velizy, just outside Paris. With no presence in the United States and no built-in connections to the Valley’s tightly knit circles, the company, VSORA, could have easily been left behind. But instead, it charted its own path—and in doing so, emerged as the only viable European competitor in the AI processors landscape.

Silicon Valley is a unique environment. It’s a place where innovation buzzes in the air, where information flows freely—not in the form of stolen secrets, but through subtle signals: a parking lot that suddenly gets packed, alerting you that something is happening, a recruiter’s call to pitch new job openings, a whisper at a coffee shop. It’s a network-driven ecosystem that rewards proximity and speed. Simply being there can offer a six-month head start compared to companies based overseas, who rely on trade publications and conferences to stay informed.

This constant, near-invisible stream of information means that companies in the Valley evolve together—each pivot triggering a cascade of similar moves by competitors. Keeping up isn’t optional. It’s survival.

And yet, VSORA managed to not only keep up but lead—despite operating 5,000 miles away. How? By staying true to its own process of innovation. Without the distraction of Silicon Valley’s echo chamber, the engineers in France developed a breakthrough hardware architecture to accelerate AI inference in data centers and at the edge that set them apart.

Ironically, it was their outsider status that became their strength.

However, recognizing the importance of proximity to the U.S. market and the advantages of the Valley’s information network, VSORA is anticipating the opening of a design center in Silicon Valley to provide the company with a critical foothold in the region while preserving its basic engineering in France.

The result: a hybrid model that leverages the best of both worlds.

But managing transatlantic teams comes with challenges. With a nine-hour time difference, coordinating workflows demands more than just good intentions. By adopting a range of collaborative tools, such as instant messaging, conference calls for complex discussions, wikis for shared documentation, and periodic in-person meetings VSORA plans to strengthen team cohesion and aligns strategic goals.

Technology can bridge time zones, but it cannot replace trust and shared purpose. And it certainly can’t replicate the magic of Silicon Valley—unless you know how to channel it from afar.

VSORA’s story shows that with discipline, vision, and a bit of French-inspired finesse, it’s possible not just to compete with Silicon Valley from the outside—but to thrive, lead, and even shape it.

Since the fall of the Roman Empire, France has played a defining role in shaping Western civilization. In the 9th century, Charlemagne—a Frank—united much of Europe under one rule, leaving behind a legacy so profound he is still remembered as the “Father of Europe.” While Italy ignited the Renaissance, it was 16th-century France that carried its torch across the continent, elevating the arts and laying the groundwork for broader cultural transformation.

The Age of Enlightenment and the subsequent Age of Reason, both rooted in French intellectual movements, revolutionized thinking across philosophy, science, and governance. The French Revolution helped dismantle aristocratic privilege and paved the way for the rise of the bourgeoisie. Even Napoleon, despite the chaos he unleashed across Europe, gifted the world the Napoleonic Code—an enduring foundation for modern legal systems.

In every domain—from science to medicine, philosophy to administration—France has left a deep and lasting imprint on the modern world.

So what happens when French intellectual rigor meets the fast-paced ecosystem of Silicon Valley?

That question was answered—quietly but impactfully—by a French disrupter headquartered in Velizy, just outside Paris. With no presence in the United States and no built-in connections to the Valley’s tightly knit circles, the company, VSORA, could have easily been left behind. But instead, it charted its own path—and in doing so, emerged as the only viable European competitor in the AI processors landscape.

Silicon Valley is a unique environment. It’s a place where innovation buzzes in the air, where information flows freely—not in the form of stolen secrets, but through subtle signals: a parking lot that suddenly gets packed, alerting you that something is happening, a recruiter’s call to pitch new job openings, a whisper at a coffee shop. It’s a network-driven ecosystem that rewards proximity and speed. Simply being there can offer a six-month head start compared to companies based overseas, who rely on trade publications and conferences to stay informed.

This constant, near-invisible stream of information means that companies in the Valley evolve together—each pivot triggering a cascade of similar moves by competitors. Keeping up isn’t optional. It’s survival.

And yet, VSORA managed to not only keep up but lead—despite operating 5,000 miles away. How? By staying true to its own process of innovation. Without the distraction of Silicon Valley’s echo chamber, the engineers in France developed a breakthrough hardware architecture to accelerate AI inference in data centers and at the edge that set them apart.

Ironically, it was their outsider status that became their strength.

However, recognizing the importance of proximity to the U.S. market and the advantages of the Valley’s information network, VSORA is anticipating the opening of a design center in Silicon Valley to provide the company with a critical foothold in the region while preserving its basic engineering in France.

The result: a hybrid model that leverages the best of both worlds.

But managing transatlantic teams comes with challenges. With a nine-hour time difference, coordinating workflows demands more than just good intentions. By adopting a range of collaborative tools, such as instant messaging, conference calls for complex discussions, wikis for shared documentation, and periodic in-person meetings VSORA plans to strengthen team cohesion and aligns strategic goals.

Technology can bridge time zones, but it cannot replace trust and shared purpose. And it certainly can’t replicate the magic of Silicon Valley—unless you know how to channel it from afar.

VSORA’s story shows that with discipline, vision, and a bit of French-inspired finesse, it’s possible not just to compete with Silicon Valley from the outside—but to thrive, lead, and even shape it.

Contact VSORA

Also Read:

The Journey of Interface Protocols: Adoption and Validation of Interface Protocols – Part 2 of 2

The Journey of Interface Protocols: The Evolution of Interface Protocols – Part 1 of 2

Beyond the Memory Wall: Unleashing Bandwidth and Crushing Latency

The Double-Edged Sword of AI Processors: Batch Sizes, Token Rates, and the

Hardware Hurdles in Large Language Model Processing

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CEO Interview with Dr. Maksym Plakhotnyuk of ATLANT 3D

CEO Interview with Dr. Maksym Plakhotnyuk of ATLANT 3D
by Daniel Nenni on 07-11-2025 at 6:00 pm
Categories: AI, CEO Interviews

Maksym Plakhotnyuk (1)

Dr. Maksym Plakhotnyuk, is the CEO and Founder of ATLANT 3D, a pioneering deep-tech company at the forefront of innovation, developing the world’s most advanced atomic-scale manufacturing platform. Maksym is the inventor of the first-ever atomic layer advanced manufacturing technology, enabling atomic-precision development of materials, devices, and microsystems. A scientist with a Ph.D. in Nanotechnology, he has deep expertise in nanotechnologies, renewable and exponential technologies, semiconductor processing, solid-state physics, and material science. A Fulbright scholar, Hello Tomorrow Grand Winner, and proud Ukrainian, Maksym has earned global recognition for his work.

Tell us about your company?

One day, it dawned on me how tired I was of sitting in a cleanroom! I began to wonder – why is there no atomic printer for semiconductor materials, which would allow us to directly print materials atom by atom without the need for multiple steps, masks and cleanrooms? It took a small village but we eventually created our micronozzle that can construct custom designs in this way. This was the culmination of work between myself and my key partners, Ivan Kundrata (a machine engineering expert) and Prof. Julien Bachmann (a chemistry expert), and ATLANT 3D came to fruition in 2018.

Today, ATLANT 3D is accelerating materials discovery by building materials and devices, atom by atom, through its direct atomic layer processing (DALP®) technology, which places precise amounts of materials exactly where needed. In a single step, the system creates complex structures for microelectronics, semiconductors, and advanced devices.

What problems are you solving?

By replacing traditional multi-step fabrication with direct atomic-scale manufacturing, this approach eliminates process complexity while reducing material waste by 90 percent. Research teams use DALP® technology to create what was previously impractical or impossible, from quantum computing components to devices that will operate in space. Our approach accelerates innovation across sectors by speeding up materials discovery while delivering a greener process.

What application areas are your strongest?

Our strongest application areas are materials innovation, advanced packaging for semiconductor manufacturing and AI, space exploration, optics and quantum computing. We are also increasingly targeting several sectors such as automotive, semiconductors, AI, communication and aerospace.

What keeps your customers up at night?

What keeps them up at night is wondering what they can accomplish with our technology. Materials discovery, or the process of finding new materials or discovering new applications for existing materials, is where we specialize, and it’s a very exciting space. Magic happens every day and the possibilities are endless!

What does the competitive landscape look like and how do you differentiate?

As discussed above, our approach accelerates innovation across sectors by speeding up materials discovery while delivering a greener process. With global demand for semiconductors showing no signs of abating, the industry remains somewhat of a paradox. On the one hand, semiconductors are vital to cutting-edge eco-friendly developments like electric cars and environmental sensors. But on the other, the current impact of the manufacturing process on the environment, and the size of its ecological footprint, are untenable.  Approaches like ATLANT 3D’s are uniquely designed to help reconcile this, once and for all.

Another one of our strategic differentiators worth highlighting is the fact that we offer a platform for natural resilience. Since President Trump highlighted the need for a robust domestic semiconductor manufacturing ecosystem during his first term, there have been more than 100 new semiconductor projects announced across 28 U.S. states. The U.S. is now on track to triple its chip manufacturing capacity by 2032 and command a sizable share of the world’s advanced chip production.

But winning the chip race worldwide will not be easy, and the U.S. must continue to bolster domestic chip production and advance innovation. We’re on the precipice of a major revolution in semiconductor manufacturing and companies like ATLANT 3D are leading the charge.

ATLANT 3D’s approach supports more semiconductor manufacturing in the U.S. because it moves away from the model of heavily offshoring production to a small handful of multi-billion dollar foundries, to leveraging universities, startups and industrial R&D based domestically to dramatically accelerate discovery and the entire lab-to-fab process, while keeping costs in check. By creating a platform for U.S. strategic resilience, ATLANT 3D is helping to reduce our country’s dependency on foreign supply chains by delivering a modular platform that supports research, prototyping, and manufacturing. Universities, startups, and industrial R&D firms across the U.S. can integrate our technology immediately into their existing architectures.

What new features/technology are you working on? 

Space exploration is a big focus area for us, and we’re working on the first space-compatible version of our technology that works in zero-gravity environments.  In late 2023, ATLANT 3D announced a collaboration with the European Space Agency (ESA) to enable on-demand production of next-generation devices, microelectronics, and more in space. The goal was to make on-demand repair, maintenance, and manufacturing of high-precision components while in orbit possible, in the microgravity and zero-gravity environment of space.

In March 2025 – about sixteen months later – ATLANT 3D and ESA announced they achieved a key milestone in their collaboration, a version of ATLANT 3D’s atomic layer deposition (ALD) system that can function in a real-world space deployment, called the NANOFABRICATOR ZERO-G System (zero G stands for “zero gravity”). Ultimately, this marks an important step towards fully autonomous deep space exploration and inhabitation, including the Moon and Mars. Next steps for ATLANT 3D include further technology validation, commercialization and partnerships – expanding collaborations with space agencies and private companies for integration into future missions.

How do customers normally engage with your company?

We work with customers in a variety of different models, including joint projects with R&D players,  original equipment manufacturer (OEM), original design manufacturing (ODM) and joint development equipment development arrangements.

 Also Read:

CEO Interview with Carlos Pardo of KD

CEO Interview with Darin Davis of SILICET

CEO Interview with Peter L. Levin of Amida

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CEO Interview with Carlos Pardo of KD

CEO Interview with Carlos Pardo of KD
by Daniel Nenni on 07-11-2025 at 4:00 pm
Categories: Automotive, CEO Interviews

kd carlos pardo ceo cofounder screen 2

Carlos Pardo has a distinguished career as a manager in the microelectronics industry, excelling in leading R&D teams. He possesses extensive expertise in the high-tech silicon sector, encompassing both hardware and software development. Previously, he served as the Technical Director at SIDSA, where he managed R&D departments, product development, production, and customer support, among other responsibilities. Mr. Pardo also contributed significantly at Hewlett Packard SA Spain as an R&D engineer, handling various business functions, and at DS2 (Design of Systems on Silicon SA).

Tell us about your company

Fabless semiconductor supplier KD provides innovative high-speed optical networking solutions for harsh environments. Founded in 2010 in Madrid, Spain, KD offers its cost-effective technology as fully qualified automotive-grade ASSP, integrating electronics, photonics, and optics in a single IC.

KD’s technology makes use of information theory, innovative digital adaptive algorithms, and analog mixed-signal design to maximize the receiver’s sensitivity. KD innovates in optical coupling and packaging design, which enables integration of optical communications ports in electronic control units using standard printed circuit assembly processes. Together, these offerings allow KD to support high-yield and reliable optoelectronics production in low-cost automotive-grade bulk CMOS deep submicron nodes, and to deliver products to carmakers with low risk, low cost, and short time-to-market.

KD made gigabit communications for step-index plastic optical fiber (SI-POF) a reality for automotive and is now developing its multi-gigabit optimized solution for use with Glass Optical Fiber (GOF) as well.

What problems are you solving?

Data transfer in harsh environments, such as vehicles, presents unique challenges compared to data center environments, including stringent environmental conditions, reliability demands, cost constraints, and high production volumes. These factors have prompted the development of specialized specifications for optical links tailored to automotive applications.

More and more, seamless connectivity of sensors, such as cameras, radar, and LiDAR with central Artificial Intelligence (AI) units, plays a key role in sensor fusion, an integral part of Advanced Driver Assistance Systems (ADAS) and Autonomous Vehicles (AV). Therefore, an optical solution is required as copper communications do not meet these needs.

Optical Ethernet connectivity perfectly solves in-vehicle challenges and electrical interference thanks to its unbeatable electromagnetic compatibility, reliability, and low cost. Fiber is inherently immune to electromagnetic interference and does not emit interference, thus saving an immense amount of additional development time and cost. Regarding temperature, fiber cables withstand extreme temperature ranges from -40 ºC up to +125 ºC for operation ambient. A simpler channel allows for a lower power consumption than copper, thanks to a simpler DSP/equalization and no need for echo cancelling.

For reliability and durability, the selection of the 980 nm wavelength allows VCSEL devices to comply with automotive reliability standards and lifetime. As no shielding is needed, connectors are smaller and mechanically more robust. In contrast to copper, up to 4 inline connectors for a speed of 25 Gb/s and 2 inline connectors for 50 Gb/s can be inserted over a length of 40 meters. With copper, it is only possible to insert 2 inline connectors with a maximum length of 11 meters and 25 Gb/s. In addition, the lower diameter of the OM3 fiber results in significant cost efficiency.

What application areas are your strongest?

KD provides semiconductors for high-speed optical networking for harsh environments. Applications in automotive, home, small and home offices (SOHO), and industrial benefit from KD’s future-proven system solutions for connectivity over fiber optics.

Automotive

Optical fiber technology enhances the automotive industry by improving data transmission speeds, reducing weight, and increasing reliability. It enables high-speed communication between vehicle systems and is immune to electromagnetic interference. Additionally, its lightweight nature improves fuel efficiency and performance. Optical fibers advance vehicle connectivity, safety, and efficiency. Automotive use cases include: communications backbone, smart antenna link, infotainment, Battery Management Systems (BMS), ADAS, cameras, radar, and displays.

Industrial

Optical fiber technology benefits the industrial sector with high-speed, reliable data transmission over long distances, immune to electromagnetic interference. This supports advanced automation, real-time monitoring, and control systems, enhancing operational efficiency. Their durability and low maintenance reduce downtime and operational costs, improving connectivity, safety, and efficiency in industrial applications.

Consumer

KD delivers non-visible 1 Gb/s optical wired connectivity for homes and SOHO. Plastic optical fiber is not electrically conductive and its cross section and bending radius allows its routing through in any duct or collocated next to any wire, even electrical cabling avoiding the use of expensive new ducts or visible trucking inside walls.

What does the competitive landscape look like and how do you differentiate?

Since 2014, with the launch of the first transceiver, KD has led high-speed optical communications for the automotive industry. At present, KD is the only company offering transceivers that comply with the Ethernet standard IEEE Std 802.3cz, which is the standard suitable for gigabit and multigigabit optical communications in automotive.

In addition, we’re evolving from being a fabless IC supplier to component assembly and testing of fully integrated optoelectronic components. We’re setting up a high-volume production site for semiconductors close to our headquarters in Tres Cantos, Spain.

What new features/technology are you working on?

Our R&D is working on two fields, all of them focused to produce high-volume low-cost single-component optical multigigabit automotive transceivers. The first field is the integration of all the electronics – i.e. optoelectronics, analog and mixed signal, digital signal processing, high speed digital interfaces, microprocessors, dependability monitors, etc. – in a single die made in an automotive-qualified bulk CMOS process.

The second field is the development of hybrid packages that can be produced in automated way, where the CMOS die is integrated with VCSEL die, PIN PD die, optical lenses, and mechanical interface that accept the optical fiber ferrules. This hybrid package is very innovative, because it requires of high precision positioning of photonics and lenses, in short cycle times, and all the materials and assembly recipes must be chosen to support reflow temperatures without affecting performance degradation.

In addition, we’re developing a new and innovative optoelectronics packaging technology. It will be applied for the first time to produce the new transceiver IC KD7251 for high-speed automotive optical communications. In setting up several automated pilot plastic packaging lines for optical transceivers, we’re working with other companies on the automated line. The aim is to develop fully automated lines from the wafer, with dicing and backgrinding, with automated transfer between machines and high precision automated alignment in plastic packaging. At this time, we’ve installed a prototype line starting its first prototype assemblies. The final production line with high volume capacity is planned to start production in 2026.

How do customers normally engage with your company?

In the ecosystem with key industry partners, we provide a system solution for optical in-vehicle data transfer. Instead of various port components, customers benefit from the single, complete package.

Gigabit Integrated FOT

For 1 Gb/s optical communications over POF, the integrated KD9351 Fiber Optic Transceiver (FOT), in combination with the proven KD1053 IC, reduces the cost for optical in-vehicle networks at 1 Gb/s, compared to STP (shielded twisted pair of copper wires). Incorporating the transmit and receive optoelectronics into one single component, the KD9351 is an optical transceiver for 100 Mb/s up to 1 Gb/s with a small footprint, enhanced efficiency and flexibility.

Multigigabit Transceiver

The KD7251 is KD’s new ASIC that implements the BASE-AU physical layers, compliant with the IEEE Std 802.3cz™ specification for automotive multigigabit optical communications links over multi-mode glass optical fiber OM3. It‘s a single-chip solution with on-chip optical interface, supporting 2.5, 5, and 10 Gb/s. It includes bridging functionalities to enable the connectivity of MIPI sensors, as cameras and radar (CSI-2®), displays (DSI-2℠), or AI processors (PCIe®) in the vehicle.

Evaluation Boards

For a quick and easy project start, KD delivers various evaluation boards and kits. The EVB9351-SFP is an automotive optical 1000BASE-RHC small form factor pluggable (SFP) module, based on the KD1053 PHY and KD9351 FOT transceivers. The EVB9351AUT platform provides all the functional and performance evaluation capabilities requested by automotive OEMs, TIER-1s or test houses, enabling product designers to successfully evaluate KD’s technology and to shorten the time to market. Based on the NXP SJA1110A switch part, the EVB9351-AUT-SW board is an automotive Ethernet switch with five optical 1000BASE-RHC ports. The EVB7251 is an evaluation board for the new KD7251, allowing optical communications links up to 10Gb/s. It operate as a media converter between the optical BASE-AU port and the SFP+ module.

Contact KD

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Podcast EP297: An Overview of sureCore’s New Silicon Services with Paul Wells

Podcast EP297: An Overview of sureCore’s New Silicon Services with Paul Wells
by Daniel Nenni on 07-11-2025 at 10:00 am

Dan is joined by sureCore CEO Paul Wells. Paul has worked in the semiconductor industry for over 25 years including two years as director of engineering for Pace Networks, where he led a multidisciplinary, 70 strong product development team creating a broadcast quality video & data mini-headend. Before that, he worked for Jennic Ltd as VP operations, successfully building the team from scratch as the company transitioned to a fabless model. Prior to that, he was responsible for the engineering team and before that he led a team for Fujitsu Microelectronics supporting ASIC customers in Europe and Israel.

Dan explores the recent addition of silicon services to sureCore’s offerings. Paul explains that the memory design skills developed at sureCore create a rich set of core competencies in analog and mixed-signal design, low-power and low-voltage design, characterization and EDA flow development that are well-suited to help customers to develop cutting-edge applications by addressing complex design requirements.

Paul describes the broad range of skills required to develop ultra-low power memory solutions and how these capabilities can directly benefit design teams. He describes example design projects and the impact sureCore was able to make for projects such as edge AI. You can learn more about sureCore’s new silicon services here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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CEO Interview with Darin Davis of SILICET

CEO Interview with Darin Davis of SILICET
by Daniel Nenni on 07-11-2025 at 6:00 am
Categories: CEO Interviews

Davis Silicet

With over 30 years of diverse industry experience, Darin leads SILICET, a semiconductor IP licensing firm.   He spearheaded a strategic pivot to focus on a seamless LDMOS innovation that delivers unmatched cost, performance and reliability advantages – backed by a robust global patent portfolio.  Prior to co-founding SILICET, he held business development roles at Coventor and VLSI Technology.

Tell us about your company?

Silicet develops and licenses IP for semiconductors.  The current focus is delivering a scalable source-side LDMOS architecture that minimizes on-resistance for a given breakdown voltage, while simultaneously enhancing Safe Operating Area, mitigating fast-transient EOS and boosting HCI reliability.

Silicet’s IP transparently integrates with any existing BCD node, providing increased device performance at a lower total production cost.  With a global IP patent portfolio in the United States, Taiwan, China, and Europe, Silicet’s IP has already been integrated in mature BCD technology offerings.

What problems are you solving?

All MOSFETs have an inherent parasitic bipolar, which can cause catastrophic snapback in Lateral DMOS devices, where the traditional mitigation approach complicates source/body engineering.  Silicet’s source-side engineering provides LDMOS designers with several simultaneous advantages:

+   provides the lowest specific on-resistance (RSP)

+   virtually eliminates the parasitic NPN

+   enhances SOA and reliability mechanisms

+   avoids punch through of self-aligned body

+   enables a new Retrograde Body to boost breakdown voltage

+   seamlessly fits into any BCD process

Silicet’s comprehensive solution provides new design trade-offs which are not available from existing device architectures, enabling LDMOS designers to leverage their know-how to optimize LDMOS devices for lowest Rsp at a given BVdss, with increasing benefits as operating voltage decreases from 16V to 5V.

This innovation seamlessly integrates with existing lithography techniques and silicidation process flows, enabling ~25% cost/performance benefits while enhancing reliability –  thereby extending the useful life of existing BCD processes and associated installed process equipment.

What new features/technology are you working on?

Silicet’s innovative IP provides multiple “knobs” where LDMOS designers can leverage their know-how to optimize devices for demanding circuit applications.

There are three key aspects to Silicet’s novel BCD technology innovation.

First, Silicet’s Hybrid Source solution minimizes poly-to-poly pitch on the source side, enabling lowest on-resistance for devices at 5v to 28V operating voltage over their conventional counterparts, while providing performance advantages inaccessible from conventional LDMOS devices, opening new opportunities to minimize gate capacitance, leverage high drive current and faster switching speed to optimize GPU/CPU power conversion devices.

A second element is using the Retrograde Body to manipulate the source e-field, providing a new knob to minimize on-resistance for a given drift length, while simultaneously enhancing HCI reliability; which dramatically improves performance and reliability for 5V to 16Vop devices.

The third element takes advantage of novel mobility/carrier injection to provide unique transconductance and very high-drive current benefits – boosting unity gain ~3X.  This breakthrough device enhancement avoids the process complications (deep S/D, Halo, LDD, etc.) which are required to overcome short channel effects; significantly simplifying the LDMOS architecture for 28/40/55/65nm BCD solutions.

What does the competitive landscape look like and how do you differentiate?

The primary market for power conversion devices includes systems requiring low on-state resistance and efficient power management, such as servers (DC-DC converters & integrated modules), automotive (motor drivers & load switches) and power management ICs (PMICs) for portable consumer electronics and Class-D audio applications.

Foundries and IDMs are using existing approaches to incrementally refine LDMOS device performance.  Our source-only innovation provides a generational leap in benefits, simultaneously delivering superior electrical performance, increased reliability and smaller die size on any BCD node.

“ Silicet doesn’t create the LDMOS design,

               we dramatically enhance the LDMOS you design! ”

While our innovation provides more compelling benefits at lower operating voltage and shorter BCD nodes, high voltage (40V to 100V operation) devices can still leverage the enhanced SOA and fast-transient EOS benefits in circuit applications that demand robust and reliable operation – including RF-LDMOS applications.

Silicet’s IP is a gamechanger for LDMOS designers, enabling semiconductor firms to dramatically differentiate performance, cost, and reliability.

  • Performance Edge: Readily differentiates products in competitive markets
    Lowest Rsp, Lowest Gate Capacitance, Highest Drive Current
  • Faster Time-to-Market: Transparently integrates with any BCD node
    Realize “next node” benefits from existing lithography (no capex required),
    while reducing technical risks and lowering adoption barriers.
  • Enhanced Reliability: Ensures robust device operation in challenging applications
    The architecture improves Safe Operating Area (SOA), mitigates fast-transient
    Electrical Overstress (EOS), and boosts Hot Carrier Injection (HCI) reliability.
  • Maximize ROI : Leverage Know-How to target diverse LDMOS applications
    (e.g. – DC-DC, PMICs, motor drivers, and RF devices)
    Achieve higher margins in demanding, cost-sensitive market applications
    Optimize resource utilization (device/process/design expertise)

These factors collectively empower semiconductor companies to rapidly achieve distinct competitive advantages, positioning them to quickly capture new opportunities and improve profitability from a single, source-side innovation.

Final comments?

Not only has X-FAB been an instrumental development partner, but also they leveraged their process/device know-how to commercialize 2nd generation ultra-low Rsp devices in XT018, X-FAB’s leading 180 nm BCD-on-SOI technology platform. This simple solution offers customers Rsp reductions of 50% (5.5V) to 30% (28V), while also enhancing robust operation and reliability in challenging automotive and industrial applications.

X-FAB’s XT018 MV Gen 2

How do customers normally engage with your company?

Silicet is actively engaging strategic partners who either want to uplift an existing BCD process or future-proof an advanced BCD node.  Let’s work together to leverage your LDMOS device/process know-how to enable breakthrough solutions.

Contact SILICET

Join the LDMOS evolution!

Also Read:

CEO Interview with Peter L. Levin of Amida

CEO Interview with John Akkara of Uptime Crew

CEO Interview with Dr. Naveen Verma of EnCharge AI

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Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD Modeling

Altair SimLab: Tackling 3D IC Multiphysics Challenges for Scalable ECAD Modeling
by Kalar Rajendiran on 07-10-2025 at 10:00 am
Categories: 3D IC, Altair, Chiplet, EDA

What is SimLab

The semiconductor industry is rapidly moving beyond traditional 2D packaging, embracing technologies such as 3D integrated circuits (3D ICs) and 2.5D advanced packaging. These approaches combine heterogeneous chiplets, silicon interposers, and complex multi-layer routing to achieve higher performance and integration. However, this evolution introduces significant challenges in modeling, simulation, and reliability assessment due to the massive size and complexity of ECAD data.

A webinar addressing this very topic was recently offered by Altair. Iyad Rayane, senior technical specialist at the company delivered the webinar session.

The Growing Complexity of Modern ECAD Models

Modern IC packages feature thousands of nets across multiple routing layers and use a variety of materials with different physical properties. This results in extremely large ECAD datasets that are difficult to manage and analyze. High-density routing and compact layouts in 3D memory cubes and stacked-die packages also lead to increased power densities and mechanical stresses. Designers face issues like thermal stress, delamination, chip warpage, and solder fatigue, which can severely impact package reliability. Traditional simulation tools struggle to handle these detailed models efficiently, often requiring prohibitively long runtimes and limiting early-stage design exploration.

Challenges in Multiphysics Simulation

Several challenges complicate multiphysics simulation of large-scale 3D IC packages. The volume and complexity of ECAD data strain the capacity of existing tools to import and process models quickly. Accurate analysis requires coupling thermal, mechanical, fatigue, and electromagnetic effects, all while managing heterogeneous materials and thin-layer geometries. Applying fine mesh detail throughout the entire model is computationally expensive, yet necessary in critical regions. Moreover, the shift to system-level floorplanning and heterogeneous integration demands new workflows that traditional EDA tools do not fully support.

Altair SimLab’s Innovative Solution

Altair SimLab addresses these challenges by providing a paradigm-shifting multiphysics environment tailored for large-scale ECAD models. It drastically reduces import times—from hours to minutes—enabling detailed simulation on common desktop hardware. Its metal-mapping technology computes equivalent material properties based on volumetric metal and dielectric content, simplifying fine routing into effective continuous materials without sacrificing accuracy. The software supports hybrid modeling, where signal layers are represented as sheet bodies, vias as wire bodies, and insulating layers as solids, allowing flexible and efficient meshing strategies.

SimLab also incorporates submodeling, allowing designers to run fast global simulations with trace mapping to identify critical areas for detailed local analysis. Displacement and other boundary conditions are transferred from the global model to the detailed submodel, balancing speed with accuracy. Furthermore, the platform integrates thermal, thermal stress, solder fatigue, and package reliability simulations within a single, user-friendly environment. It also interfaces with third-party solvers to extend multiphysics capabilities, providing a comprehensive solution for advanced packaging analysis.

How Altair SimLab Helps Engineers

By combining scalable import, flexible modeling approaches, and multiphysics coupling, Altair SimLab enables engineers to accelerate simulation turnaround and improve prediction accuracy. Designers can quickly explore “what-if” scenarios early in the design cycle, making better-informed decisions about process nodes and package configurations. The efficient data handling allows for detailed reliability analysis of solder bumps, vias, and interconnects, helping identify potential failure points before manufacturing. This approach reduces costly redesigns, shortens development cycles, and ultimately leads to more robust semiconductor products.

Test Case Results: Significant Time Savings

The power of Altair SimLab is evident in real-world test cases. One example involves a large PCB measuring 42 cm by 34 cm with 14 routing layers and over 7,500 nets. SimLab reduced the import runtime from more than four hours on a high-performance computing system to just five minutes on a standard laptop. Another case features a 66 mm by 66 mm silicon interposer with 12 routing layers and over 3,000 nets. Import time was cut from one hour to three minutes. These results demonstrate how Altair’s efficient ECAD data handling enables complex multiphysics simulations to be performed quickly and cost-effectively on everyday hardware.

Summary

As semiconductor packaging continues to evolve toward 3D ICs and heterogeneous integration, simulation tools must keep pace with increasing complexity. Altair SimLab delivers a scalable, integrated platform that bridges the gap between massive ECAD datasets and accurate multiphysics analysis. Its innovative modeling techniques and efficient workflows empower designers to accelerate innovation, optimize reliability, and confidently address the challenges of advanced packaging technologies. By transforming how large-scale ECAD models are imported and analyzed, Altair SimLab plays a critical role in advancing the next generation of semiconductor devices.

Learn more at https://altair.com/simlab

Also Read:

Altair at the 2025 Design Automation Conference #62DAC

Who Are the Next Anchor Tenants at DAC? #61DAC

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AI Booming is Fueling Interface IP 23.5% YoY Growth

AI Booming is Fueling Interface IP 23.5% YoY Growth
by Eric Esteve on 07-10-2025 at 6:00 am
Categories: IP, IPnest, Semiconductor Services

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AI explosion is clearly driving semi-industry since 2020. AI processing, based on GPU, need to be as powerful as possible, but a system will reach optimum only if it can rely on top interconnects. The various sub-system need to be interconnected with ever more bandwidth and lower latency, creating the need for ever advanced protocol like DDR5 or HBM memory controller, PCIe and CXL, 224G SerDes and so on.

When you design a supercomputer, raw processing power is important, but the way you access memory, latency and network speed optimization will allow you to succeed. It’s the same with AI, that’s why interconnects protocols are becoming key.

In 2024, the interface IP segment grew by 23.5% to reach $2365 million. Our forecast shows growth for years 2024 to 2029, comparable to 20% growth in the 2020’s. AI is driving the semiconductor industry and Interconnect protocols efficiency are fueling AI performance. Virtuous cycle!

The interface IP category has moved from 18% share of all IP categories in 2017 to 28% in 2023. In 2024, we think this trend will amplify during the decade and Interface IP to grow to 38% of total (detrimental to processor IP passing from 47% in 2023 to 41% in 2029). We forecast total IP to weight $15 billion in 2029 and Interface IP $5.4 billion itself.

As usual, IPnest has made the five-year forecast (2024-2028) by protocol and computed the CAGR by protocol (picture below). As you can see on the picture, most of the growth is expected to come from three categories, PCIe, memory controller (DDR) and Ethernet, SerDes & D2D, exhibiting 5 years CAGR of resp. 17%, 17% and 21%. It should not be surprising as all these protocols are linked with data-centric applications! If we consider that the weight of the Top 5 protocols was $2200 million in 2024, the value forecasted in 2029 will be $4900 million, or CAGR of 17%.

This forecast is based on amazing growth of data-centric applications, AI in short. Looking at TSMC revenues split by platform in 2024, HPC is clearly the driver. Starting in 2020, we expect this trend to continue up to 2029, at least.

Conclusion

Synopsys has built a strong position on every protocol -and on every application, enjoying more than 55% market share, by doing strategic acquisitions since the early 2000’s and by offering integrated solutions, PHY and Controller. We still don’t see any competitor in position of challenging the leader. Next two are Cadence and Alphawave, with market share in the 15%, far from the leader.

In 2025 and after, we think that a major strategy change will happen during the decade. IP vendors focused on high-end IP architecture will try to develop a multi-product strategy and market ASIC, ASSP and chiplet derived from leading IP (PCIe, CXL, memory controller, SerDes…). Some have already started, like Credo, Rambus or Alphawave. Credo and Rambus already see significant revenues results on ASSP, but we will have to wait to 2026, at best, to see measurable results on chiplet.

Also Read:

Design IP Market Increased by All-time-high: 20% in 2024!

AI Booming is Fueling Interface IP 17% YoY Growth

Semi Market Decreased by 8% in 2023… When Design IP Sales Grew by 6%!

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Building Trust in Generative AI

Building Trust in Generative AI
by Daniel Payne on 07-09-2025 at 10:00 am
Categories: EDA, Events, Perforce

perforce AI challenges min

AI technology was prevalent at DAC 2025, but can we really trust what Generative AI (GenAI) is producing? Vishal Moondhra, VP of Solutions Engineering from Perforce talked about this topic in the Exhibitor Forum on Monday, so I got a front row seat to learn more.

Vishal started out by introducing the four challenges and risks of using GenAI for semiconductor design:

Liability questions arise over who owns the IP in a new design, how the IP is being licensed, and whose data is being used to train an AI model. Companies need to know how AI models were trained, so that training is a traceable procedure. What if a new IP block was created by GenAI and it contains an error, lengthening the time to production and increasing development costs? When mixing both external IP with internal IP, are there data quality concerns?

Establishing trust for using AI to train models requires three pillars:

  1. Clear and auditable data provenance for all training datasets
  2. Complete traceability of IPs and IP versions
  3. Secure and compliant use of both internal and external IP

With the Perforce methodology, a semiconductor team will use IP lifecycle management to provide the proper provenance for training datasets. Team members define their design in terms of IPs, establishing provenance for each IP, providing complete traceability down to the file level, along with its history. Data contamination of the dataset is avoided by adding and enforcing rules about IP usage. Incremental training is supported, giving users a history of what changed since the last training set. All of this reduces the risk of using GenAI to train models for semiconductor design.

Vishal spoke about what an IP object could be: processor, memory, register, library cell, PDK, chiplet, embedded SW, or firmware. Adding metadata to an IP block enables permissions to be set, technical specs to be added, properties to be defined, usage set, versions updated, and even bugs to be tracked. IP lifecycle management enables high-level abstract IPs to have dependencies, form subsystems and use hierarchy. Even the environment configuration is stored as workspace settings, documentation, startup files and scripts, or templates.

The AI training process was presented, showing the flow of how files are created and models formed by using scripts and actions. With Perforce, a completely traceable flow of data creates new training data, and the pipeline can be run multiple times.

With an IP Lifecycle Management (IPLM) flow, all data sources can be modeled as IPs. Each derived data source becomes the parent of the source, and the preprocessed data is the parent of raw data, while training data is the parent of the preprocessed data. Both the training and final models are also modeled as IPs. Each script that runs a data transformation and model training becomes an IP.

Using IPLM in AI/ML training pipelines allows semiconductor teams to manage all of their data and dependencies, creating a series of parent-child relationships. Data management can be mixed between tools like Perforce P4 and Git based on user preferences. Teams can quickly build new workspaces with the right data, scripts, and models each time. This whole ecosystem is fully traceable, so you always record the data source, know how the derivatives were assembled, have a record of all parameters, and ensure that all models are fully traceable and reproducible. Engineers learn how to add metadata to the training projects, like the training parameters, results, history of runs and runtimes. You can view and model the model lineage to see which project was derived or copied, and where it came from.

Summary

GenAI is sweeping across the EDA and IP landscape, so it’s worth questioning the integrity of this new paradigm. The software team at Perforce has thought about each trust challenge and come up with an approach to make GenAI model development and usage trustworthy. Learn more about Perforce and semiconductor design by visiting their website.

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