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Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB Design

Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB Design
by Bernard Murphy on 03-19-2026 at 6:00 am
Categories: AI, EDA, Siemens EDA

Fuse Agentic System

Though terminology sometimes get fuzzy, consensus holds that an agent manages a bounded task with control through a natural language interface. An agentic orchestrator, itself an agent, manages a more complex objective requiring reasoning through multi-step actions and is responsible for orchestrating those actions. By way of example, setting up an individual simulation might be handled by an agent. An orchestrator could manage setting up multiple scenarios for running simulation, launching those runs, debugging detected failures and summarizing results. More hands-free automation, at least in principle, freeing engineers to explore a wider range of optimizations and analyses.

A concrete example

These days I’m very much into specific instances of AI benefits rather than abstract potential benefits. Amit Gupta (chief AI strategy officer, senior vice president and general manager, Siemens EDA) shared a nice example, close to his prior roots in founding and growing Solido.

A designer wants to fully characterize a logic function across all relevant process corners. They have Liberty files for some voltage and temperature corners, encoded in the file names, but not all. The orchestrator figures out what is missing and sets up tasks for a generator agent to build the missing files, here leveraging Solido ML-based technology.

Next the orchestrator triggers validation agents to check the generated files, looking for potential inconsistencies or unphysical behavior. Where problems are found the orchestrator can trigger repair agents, then re-run validation. This may resolve most errors, perhaps leaving only one or two files that must be corrected manually.

Contrast this with the effort a designer must invest today: figuring out which files are missing, setting up Solido runs to build those files, checking each and manually repairing errors, then re-running validation. Each step well within the capabilities of the designer but together a lot of administrative overhead, burning expert designer cycles that could be better invested elsewhere. Agentic systems automate that overhead, directed by natural language setup. Not replacing the developer but making them more productive.

A challenge

In the example above, all the EDA technologies managed by agents are from Siemens EDA. How does an agentic flow work when tools you might want to include in an agentic task are provided by competing EDA vendors? In my earlier example of setting up multiple simulation scenarios, running, then debugging, maybe your approved simulator is from one vendor whereas your preferred debugger is from another. How well can an orchestrator work in a mixed vendor flow?

This isn’t a question of data compatibility. Most EDA tools support industry approved or de facto standards. The issue is that effective agents need deep insight into how to control tools, for which there no standards (in fact standards here would stifle innovation). An agent must understand not only internal controls within a tool but also the intent behind those controls. In the Fuse Agentic flow this insight is enabled by a RAG pipeline.

I have written before about RAG (retrieval augmented generation) and its evolution to higher accuracy. First generation RAG, as in early chatbots, digested natural language text from any source and then could answer question prompts on any topic covered in that area. Pretty slick except that while often impressive, answers were sometimes spectacularly wrong. When you (a human) read the retrieved text, this isn’t too damaging – you quickly spot the mistake. But it is a big problem when an agent is relying on the accuracy of retrieval.

Now there is a concept of advanced RAG, which itself depends on agentic methods to improve accuracy in retrieval through reasoning, self-reflection and verification. Accuracy goes up significantly, as you have probably noticed in recent AI responses accompanying Google searches. Newer methods continue to advance but the important point here is that we can have more confidence in document scraping, which equally can drive more accurate agentic behavior around a tool (though still not perfect; still requiting that we trust but verify, as in all things AI).

Which leads back to how to integrate a “foreign” tool into an agentic flow. A design team or the tool providers can build a model by scraping tool documentation, and that model can then be integrated under the Fuse EDA AI agent.

More on the Fuse EDA AI Agent

Fuse can plan and orchestrate across the full range of Siemens EDA tools, from front to back in IC and PCB circuit design, implementation, verification and manufacturing sign-off. For industry-standard agentic compatibility, Fuse supports MCP interfaces, the NVIDIA Agent Toolkit, Nemotron models and the NVIDIA AI infrastructure for enhanced tool calling and reasoning capabilities.

Fuse builds on an advanced RAG pipeline and a multimodal EDA-specific data lake spanning RTL, simulation, implementation, test and more.

Siemens already boasts endorsements from Samsung (Jung Yun Choi, executive vice president of Memory Design Technology, Samsung Electronics) and NVIDIA (Kari Briski, vice president of generative AI, NVIDIA).

The product debuted at NVIDIA GTC 2026 and is available today. You can learn more HERE.

Also Read:

Siemens Wins Best in Show Award at Chiplet Summit and Targets Broad 3D IC Design Enablement

Siemens Fuse EDA AI Agent Releases to Orchestrate Agentic Semiconductor and PCB Design

Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer

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Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer

Accelerating Computational Lithography Using Massively Parallel GPU Rasterizer
by Kalar Rajendiran on 03-18-2026 at 10:00 am
Categories: EDA, Lithography, Siemens EDA

Rasterization Polygon to pixel based representation

As semiconductor manufacturing pushes deeper into the nanometer regime, computational lithography has evolved from a supporting step into a central pillar of advanced chip design. Mask synthesis, lithography simulation, and optical proximity correction (OPC) now demand unprecedented levels of accuracy and computational throughput. At the heart of these workflows lies rasterization, which is the process of converting complex geometric layouts into ultra–high-resolution pixel grids.

Rasterization – Polygon to pixel-based representation

 

Siemens EDA recently published a whitepaper presenting an innovative approach to addressing this topic. The whitepaper explores why rasterization has become a bottleneck and how an innovative rasterization algorithm using massively parallel GPU configuration addresses the challenges. Real-world performance results presented in the whitepaper reveal the innovative technique’s impact on next-generation semiconductor manufacturing.

Why Rasterization Matters More Than Ever in Lithography

Rasterization is often associated with computer graphics, but in electronic design automation (EDA), its role is far more consequential. In computational lithography, rasterized layouts are used to simulate how light propagates through masks and how photoresist responds at nanometer scales. Unlike graphics applications, where a pixel can be treated as simply on or off, lithography requires precise fractional pixel coverage and strict preservation of connectivity between extremely fine features. A tiny error introduced during rasterization can propagate through simulation and OPC loops, ultimately affecting yield and manufacturability.

As technology nodes shrink below a few nanometers, the resolution required for rasterization skyrockets, and the same operation must be repeated many times during iterative OPC flows. Even highly optimized CPU-based rasterizers struggle to keep up, turning rasterization into a dominant runtime bottleneck.

The Limits of Traditional Rasterization Approaches

Most traditional rasterization techniques rely on binary coverage models that work well for visualization but break down in lithography contexts. These approaches fail to capture subtle intensity variations and often introduce connectivity artifacts when dealing with thin lines or closely spaced features. At the same time, the sheer scale of modern layouts with billions of polygons and trillions of pixel evaluations places enormous pressure on memory bandwidth and compute resources.

This is where GPUs become attractive. Their massive parallelism is well suited to data-intensive workloads, but GPUs also present challenges, including irregular memory access patterns and sensitivity to numerical precision. Successfully using GPUs for lithography rasterization requires algorithms designed specifically for accuracy-first, massively parallel execution.

Rethinking Rasterization for GPUs

A GPU-optimized rasterizer for computational lithography starts with a fundamentally different mindset. Instead of sequentially processing polygons, the layout is spatially decomposed into independent regions that can be rasterized in parallel. Each region is mapped to GPU thread blocks, allowing thousands of threads to evaluate pixel coverage simultaneously.

Example of pixel classification and processing

Fractional pixel coverage is computed using floating-point arithmetic, not approximations, ensuring that boundary interactions are handled with nanometer-scale precision. Special care is taken to preserve sub-pixel connectivity so that thin features are not inadvertently broken during rasterization. Manhattan geometries benefit from simplified evaluation paths, while curvilinear shapes are handled using more general, yet still parallel-friendly, methods.

How the GPU Rasterization Pipeline Works

The rasterization pipeline begins with CPU-side preprocessing, where layout data is parsed and binned into spatial tiles. These tiles are transferred to the GPU in memory layouts optimized for coalesced access. On the GPU, each tile is processed independently: geometry is cached in shared memory, threads are assigned to pixels or small pixel groups, and each thread computes whether its pixel lies inside a polygon, outside it, or on its boundary.

Rasterization of L-shape using block of threads

Boundary pixels receive special treatment. Polygon edges intersecting a pixel are analytically evaluated, and the fractional area covered is computed precisely. Atomic operations ensure correct accumulation when multiple polygons affect the same pixel. This design achieves both high performance and deterministic accuracy, two properties that are rarely achieved together in large-scale parallel systems.

The implementation leverages the CUDA programming model and is particularly effective on modern data-center GPUs from NVIDIA, which provide the memory bandwidth and concurrency required for extreme-resolution rasterization.

Real-World Performance Results Using Nvidia H100 GPUs

Performance benchmarking paints a compelling picture. When compared with highly optimized CPU-based rasterizers, the GPU approach delivers dramatic speedups across a range of layouts. For designs dominated by Manhattan geometries, speedups of up to 290× have been observed. Even for more challenging curvilinear layouts, the GPU rasterizer achieves speedups of up to 45×.

Crucially, these gains do not come at the expense of accuracy. Across all test cases, absolute error remains below one percent relative to reference CPU calculations. This level of precision meets the stringent requirements of computational lithography and confirms that massive parallelism can coexist with nanometer-scale accuracy.

Why This Matters for EDA and Manufacturing

The implications of GPU-accelerated rasterization extend far beyond raw performance metrics. Faster rasterization shortens OPC and mask synthesis cycles, enabling more iterations within the same design window. This leads to better correction quality, improved yield, and reduced time to market. High accuracy and connectivity preservation ensure that these gains do not introduce new risks into manufacturing flows.

As designs increasingly incorporate complex, non-Manhattan geometries and as simulation fidelity continues to rise, the scalability of GPU-based rasterization becomes even more valuable. What was once a bottleneck becomes a scalable, future-proof component of the lithography pipeline.

Summary

Massively parallel GPU rasterization represents a significant shift in how computational lithography workloads are approached. As GPU architectures continue to evolve, offering more cores and higher memory bandwidth, the performance advantages of this approach are likely to grow. Future work will focus on deeper integration with existing EDA platforms, support for heterogeneous CPU–GPU workflows, and extensions to more advanced lithography models and three-dimensional effects.

You can download the entire whitepaper from here.

Also Read:

Formal Verification Best Practices

AI-Driven Automation in Semiconductor Design: The Fuse EDA AI Agent

Siemens Reveals Agentic Questa

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Verification Analytics: The New Paradigm with Cogita-PRO at DVCON 2026

Verification Analytics: The New Paradigm with Cogita-PRO at DVCON 2026
by Daniel Nenni on 03-18-2026 at 8:00 am
Categories: EDA, Events

The Cogita PRO Paradigm

Cogita-PRO, developed by Vtool, introduces a transformative approach to design verification by treating it as a big data challenge rather than a traditional debugging exercise. Released in February 2026, this tool shifts the focus from manual log and waveform inspection to advanced verification analytics powered by data processing, AI, and algorithmic insights.

In conventional verification flows, engineers write testbenches and tests, then spend considerable time running simulations, debugging failures with waveforms and logs, fixing bugs in RTL or testbench code, and chasing coverage closure. This process often proves inefficient, especially in the final stages where the last few percent of coverage consumes disproportionate effort. Checkers may miss subtle legal-yet-problematic corner cases, and the sheer volume of data from gigabytes of logs makes gaining a holistic view difficult.

Cogita-PRO redefines this second phase as Verification Analytics. After initial sanity checks, it ingests simulation outputs including UVM logs, software logs, VIP traces, and waveform databases. Input format remains agnostic thanks to flexible data processors. These feed into a central smart database where raw information transforms into structured occurrence tables.

Key concepts include nodes (recurring log messages or sampled waveform signals), data fields (variables like addresses, IDs, or priorities), and routes (sequences linking related nodes to represent transaction lifecycles). Users can perform data fabrication to derive new metadata, calculate values, or label entries without rerunning simulations. This enriched dataset enables powerful analytics.

The tool delivers multiple layers of insight. Visualization features show routes evolving over time or outstanding transactions per master, offering immediate clarity on system behavior. Blind combination algorithms detect anomalies and perform root-cause analysis by highlighting outlier routes, nodes, or data fields with anomaly probability scores. For instance, multiple methods might converge on a specific address causing a NoC deadlock.

Route shape analysis examines sequence patterns, durations, and field variations. Pass/fail modeling constructs profiles from known good tests, then flags deviations in failing runs, such as altered node orders or unexpected durations in NoC packet routes. These techniques uncover hidden bugs, performance issues, and unintended behaviors that traditional methods overlook.

Cogita-PRO supports three usage models. The first accelerates individual debugging and closure through a GUI, chat interface, or CLI, with optional LLM assistance for setup and exploration. The second scales to regressions, teams, and organizations by exporting understandings like processed data, models, and algorithms for reuse across tests, IPs, subsystems, SoCs, and future projects. The third embraces agentic AI, positioning Cogita-PRO as a debugging agent within multi-agent systems, potentially collaborating with RTL or testbench generative agents while maintaining human-in-the-loop oversight.

Overall, Cogita-PRO promises faster convergence toward tapeout with predictable readiness. It catches elusive logic and performance problems early, reduces reliance on manual sifting through massive datasets, and scales effectively across projects. Vtool encourages early adopters to conduct one-week on-site trials with real data to demonstrate measurable value and train initial users.

Bottom line: By applying visualization, anomaly detection, comparison, and analytics inspired by fields like fraud detection (where false positives are preferable to missed threats), Cogita-PRO empowers verification teams to achieve deeper understanding with less effort.

CONTACT VTOOL 

Also Read:

Formal Verification Best Practices

AI-Driven Automation in Semiconductor Design: The Fuse EDA AI Agent

Agentic AI and the Future of Engineering

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Breker Hosts an Energetic Panel on Spec-Driven Verification

Breker Hosts an Energetic Panel on Spec-Driven Verification
by Bernard Murphy on 03-18-2026 at 6:00 am
Categories: AI, Breker Verification Systems, EDA
2 Comments

Energetic panel on AI in verification

I was fortunate to be asked to moderate an evening panel adjacent to the first day of DVCon 2026, on AI-Driven SoC Verification starting from specs. You know my skepticism on panels, finding they rarely generate insights or controversy. This panel was quite different. Panelists were Shelley Henry (CEO, Moores Lab AI), Adnan Hamid (CTO, Breker Verification Systems), Deepak Manoharan (Senior Director of Engineering, Arm), and Michael Chin (Senior Principal Engineer, Intel Corp). If you want to know more about reality in AI deployment in functional verification, these guys have opinions. I summarize my takeaways below.

Why automate spec-driven verification?

The purpose of verification is to certify what is being built is (functionally) consistent with the design spec (or test spec, here assume design spec). This spec is generated by an experienced in-house architect, crossing what they currently know about customer requirements with what they know about available in-house baseline designs, IP options and expertise.

There are unavoidable challenges in specs. These remain moving targets some way into the design schedule. Architects deliver a first pass for design and DV teams to shift left, understanding that updates will continue. Customer(s) themselves may not yet have frozen their requirements as they continue to gauge market expectations. They too are shifting left to the architect. Add to this that neither writing, reading nor understanding are error-free.

If you have ever been on the review cycle for a document, you will understand how mistakes can happen. First pass review, diligently read and checked. Second and later passes skimmed with high chance of missing small but important changes. Revision tracking is an outdated solution for locating and understanding changes.

Extracting relevant updates is a perfect application for AI. Also perfect is dynamically discovering topic-relevant sections in the spec “Show me all mentions of fence in this spec”. A related challenge, similarly addressed, is dealing with specs which back-reference earlier specs.

Here I should acknowledge a good question from the audience, “What if you don’t have a spec?” This is startup territory: no baseline design and not enough time to create a spec. I’ve been in this position myself. A startup has a core differentiating idea and should be busy creating a proof of concept around that idea before they run out of money. Creating a spec is a very low priority. That said, pre-funding and in-flight they must create documents and mail/text threads to communicate internally. Perhaps these could be sucked into a spec generator (Shelly, any comments)?

Automation experiences in production design

How accurately can AI generate, from a raw spec, an intermediate representation, say a table of opcodes or a flow diagram of operation? The sense here is 90-95%, but that last 5% is hard. No ideas were shared on how to characterize this shortfall, though Shelly has thoughts on how the gap could be narrowed.

Good discussion around hallucinations and over-enthusiastic claims from AI, with general agreement that we should never accept early responses. Instead, repeat the question, eliciting different responses, pick your favorites and iterate to a good solution. An interesting perspective was the importance of figuring out where in the AI process is best to provide feedback, to guide/train the system onto a better path when it looks like it might be headed down an unproductive path. Live experience has shown this can evolve correctness from 40% on a first pass to 100% over successive learning passes. Impressive!

Why not automate this process setting different agents to work on an answer, judging between answers using a critique agent? Interesting idea though there were mixed feelings on how ready we are for that step (or whether we will be given the option).

Which brought us to trust. This boils down to decomposing tasks between checkpoints with easily human-checkable output. PSS generated from a spec is easy to read, therefore easy to catch errors. Going all the way from spec to UVM is a more challenging jump, though Shelly suggests there is a market for that too, perhaps more based on UVM familiarity than ease of checking.

Threat or opportunity for DV engineers?

Will DV engineers train AI and then be out of a job? One response was that AI will simply make us more productive. We are nowhere near maxing out appetite for new semiconductor devices. Using AI, more of these will be in reach and we’ll need all our engineers to satisfy that need.

A rather different viewpoint noted that design execs are now pushing for a shorter design lifecycle per chip, to be competitive on time to market and cost. AI will play a larger part in that lifecycle than we may find comfortable, but we may have to adapt. Engineers who are curious, who can ask good questions and have a learning mindset will thrive in an AI-centric process. Those who are stuck in their old ways will not do so well.

A third panelist told his kids that they should not plan to do what he does, because that job won’t exist when they graduate. Current DV roles will have been replaced by verification architects. (Shout out here also to Abhi Kolpekwar at Siemens who calls them “verification scientists”.)

In closing, we do indeed need to train the AI, just as we currently train junior engineers. I’m sure existing training collateral would be a good start. We also need to develop more systematized methods to assess the performance of AI verification. Today these may be captured in spreadsheets and communal know-how. Now we must define metrics which critique agents can check. And processes to support periodic human review and update.

Breker and MooresLab have partnered to create the first commercial AI-driven SoC verification solution, I assume addressing a number of these areas. You can learn more HERE, including a recording of the panel discussion.

Exciting times!

Also Read:

Verifying RISC-V Platforms for Space

A Principled AI Path to Spec-Driven Verification

Breker Verification Systems at the 2025 Design Automation Conference #62DAC

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Formal Verification Best Practices

Formal Verification Best Practices
by Daniel Payne on 03-17-2026 at 10:00 am
Categories: EDA, Siemens EDA

formal verification

How do I know when my hardware design is correct and meets all of the specifications? For many years the answer was simple, simulate as much as you can in the time allowed in the schedule and then hope for the best when silicon arrives for testing. There is a complementary method for ensuring that hardware design meets the specifications by using formal verification, a mathematical technique to prove that the design functions properly under all possible cases. Nicolae Tusinschi, Siemens EDA wrote a white paper on this topic, so this blog shares what I learned about formal verification.

Simulation only tests what you provide as sequential inputs to a design, hoping that you may get close to covering all of the states in a design. Formal verification is an exhaustive approach, analyzing all possible states and input combinations, finding any potential violations to intended behavior.

For formal verification engineers do write assertions, assumptions and cover properties with languages like SystemVerilog Assertions (SVA) or the Property Specification Language (PSL), depending on preferences. An assertion states the expected behavior of a design. Constraints are used to limit the formal analysis to only be valid input sequences or states. Cover properties tell you how completely your design has been verified. These are the pieces that direct the formal verification methodology, showing that the design will work as specified through all conditions.

Pre-built formal applications make formal use easier than gaining formal experience. One formal app can check for clock domain crossing issues, identifying synchronization problems without any special knowledge. Control logic was an early use for formal verification with its limited state space, yet new formal tools can also verify data paths with their larger number of data values and operations. Siemens offers a full suite of formal verification solutions with Questa One Static and Formal Verification (SFV)..

Yes, formal verification has limits in terms of memory usage and total state space, so on large designs is recommended to use formal selectively on critical components, then rely on simulation for the remaining components.

Formal analysis can get stuck and report inconclusive results if the design is highly complex, or assertions are beyond the tool capacity to compute in one run. Limiters to formal analysis can be a large state space, deep sequential depth or property complexity. Using bounded proofs in formal verification will check an assertion only within a certain number of clock cycles, producing results in a more feasible amount of time. On the other hand, formal tools help identify limits by reporting the “cone of influence”, which is the logic that affects each property being verified. Questa One SFV shows the logic cone of influence, listing assumptions and signals, allowing you to address the complexity and maybe remove or add some assumptions.

For best results it’s recommended that assertions be written simply and with short sequential depth. Decomposition examples were provided for modular partitioning across multiple sub-modules. Counters create large sequential depth but can be abstracted by replacing them with a smaller one or using a non-deterministic model. Large memories can create a giant number of state bits, so you can either black box the memory model or reduce the memory size.

An example of abstracting memory is when there are 128 entries with a 64 bit data width. Memory addresses that are not 100 can be abstracted using this netlist cutpoint command. This abstracted memory has the number of state bits reduced to just 64 from 8,192, which improves the formal runtime speed.

for {set i 0} {$i < 128} {incr i} { 
    if {$i != 100} { 
        netlist cutpoint memory_instance.mem[$i] 
    } 
}

Summary

This white paper on formal verification shares many examples to explain where and how to use the technology most effectively. Best practices include strategically applying formal, combining both formal and simulation, iteratively refining where formal is used, and documenting to other team members the assertions, assumptions and abstraction usages. Formal verification uses a mathematical proof of your design being correct, instead of relying on probably being correct. Designs that are safety-critical or require high-reliability benefit greatly from higher levels of assurance provided by formal verification.

The larger the design and the more complex the design, the greater the role that formal verification provides. Formal apps cut down the learning curve and produce faster verification results.

Read the entire 19 page white paper here.

Related Blogs

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The First Real RISC-V AI Laptop

The First Real RISC-V AI Laptop
by Jonah McLeod on 03-17-2026 at 6:00 am
Categories: IP, RISC-V

DC ROMA

At a workshop in Boston on February 27, something subtle but important happened. Developers sat down in front of a RISC-V laptop, installed Fedora, and ran a local large language model. No simulation. No dev board tethered to a monitor. A laptop.

For more than a decade, RISC-V advocates have promised that the open instruction set would eventually reach mainstream computing devices. Until now the reality has mostly been evaluation boards, embedded systems, and research platforms. The ROMA II laptop changes that equation. Developers can treat it like a normal PC—boot it, install Linux, run software, try AI. The Boston event, part of World RISC-V Days and co-sponsored by DeepComputing, Red Hat, and RISC-V International, was less a product launch than a proving ground. Attendees worked directly with the hardware, tuned the operating system, and pushed the machine hard enough to reveal what works and what still doesn’t. In any ecosystem, a platform becomes real the moment developers start breaking it.

The machine itself is built around the SpacemiT K1, a RISC-V system-on-chip aimed at edge AI and general computing. It isn’t trying to compete with Apple’s M-series or Qualcomm’s new AI PC processors; the ambition is different. This is an open-ISA developer machine, designed to explore what an AI laptop built around RISC-V actually looks like. The architecture combines three compute domains: an eight-core 64-bit  complex running around the 2 GHz class; a 256-bit implementation of the RISC-V Vector Extension (RVV 1.0); and a fixed-function neural processor called the AI Fusion Engine delivering roughly two tera-operations per second.

The scalar cores run the operating system and application logic, the vector engine handles the messy middle ground of AI workloads—quantization, dequantization, normalization, and data reshaping—while the NPU accelerates the dense matrix multiplications that dominate transformer inference. Readers unfamiliar with RVV can find a practical introduction in Dr. Thang Tran’s RISC-V Vector Primer on GitHub (https://github.com/simplex-micro/riscv-vector-primer). Memory comes from LPDDR4X, up to sixteen gigabytes, paired with NVMe storage, all packaged inside a Framework-compatible modular chassis. It is very clearly a developer’s laptop.

The Boston workshop centered on Fedora Linux, and that choice was deliberate. Red Hat has been quietly treating RISC-V as a serious upstream architecture target, and the event exposed how far that effort has progressed. Participants booted Fedora on the ROMA II hardware, examined kernel support, checked package coverage, and explored the gaps that still need attention. For the first time, a mainstream Linux distribution ran interactively on a RISC-V laptop in a public developer workshop. A few years ago that alone would have been notable; what came next mattered even more.

The demonstration shifted quickly from operating systems to AI. Developers loaded compact language models—roughly one to three billion parameters—and ran inference locally. Tokens appeared in real time. Quantization settings changed. Thermal behavior became visible. The point wasn’t to prove that RISC-V could compete with GPU servers; the goal was simpler: show that local AI actually works on the platform. Several patterns emerged almost immediately. The NPU proved essential; CPU-only inference slows dramatically once models move beyond trivial size. The vector engine quietly handled much of the surrounding workload—quantization, KV-cache updates, normalization, reshaping—exactly the kind of glue logic modern AI systems require. The execution model looked familiar: CPU orchestrates, NPU performs the heavy math, vector units handle the data transformations in between.

The real constraint turned out to be memory bandwidth. LPDDR4X limits throughput once models approach roughly three billion parameters, which is one reason DeepComputing positions ROMA II as a developer platform rather than a consumer AI laptop. Even so, the system proved stable under sustained load. Developers ran inference long enough to observe predictable thermal throttling behavior, stable kernel drivers, and no crashes or hangs. For a first-generation RISC-V laptop platform, that level of stability matters more than benchmark numbers.

The machine already demonstrates several things the ecosystem has been waiting for: it runs Fedora natively, executes real LLM workloads locally, and operates within a fully open instruction-set ecosystem. The modular Framework chassis makes it attractive for engineers working on kernels, drivers, and machine-learning software. At the same time, its limits are obvious. Two TOPS of NPU performance supports small models but not larger seven-billion-parameter networks; CPU performance sits in the mid-range compared with modern laptop processors; memory bandwidth constrains scaling; the GPU contributes little to machine-learning workloads for now. ROMA II is not a consumer AI laptop—it is a developer workstation for the RISC-V ecosystem.

Still, the Boston workshop signals something broader. For years, discussions about RISC-V laptops lived mostly in presentations and roadmaps. Here developers were installing Linux, compiling software, and running AI on real hardware. That combination changes the conversation. When engineers can treat a platform like a normal computer—boot it, modify it, push it until it breaks—the architecture stops being a research topic and becomes an engineering target.

DeepComputing’s roadmap already points toward the next step. The upcoming DC-ROMA AI PC moves to an ESWIN dual-die system-on-chip with eight SiFive P550 cores, roughly forty TOPS of NPU performance, and thirty-two to sixty-four gigabytes of LPDDR5 memory, alongside a custom vector processing cluster and compatibility with the Framework Laptop 13 chassis. That level of compute should support four-to-seven-billion-parameter models comfortably. Seen in that light, ROMA II is less an endpoint than a bridge.

What happened in Boston may look small from the outside—a room full of developers installing Linux and running a language model—but these moments are how ecosystems turn. A laptop boots, software runs, developers start experimenting. At that point the architecture stops being hypothetical, and RISC-V personal computing starts to look real.

Also Read:

The Evolution of RISC-V and the Role of Andes Technology in Building a Global Ecosystem

The Launch of RISC-V Now! A New Chapter in Open Computing

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

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AI-Driven Automation in Semiconductor Design: The Fuse EDA AI Agent

AI-Driven Automation in Semiconductor Design: The Fuse EDA AI Agent
by Daniel Nenni on 03-16-2026 at 1:30 pm
Categories: EDA, Siemens EDA

The semiconductor industry is experiencing unprecedented growth in complexity as advanced process nodes, heterogeneous integration, and AI-driven workloads demand increasingly sophisticated chip designs. At the same time, semiconductor companies face rising design costs, increasing engineering workloads, and a shrinking talent pool. To address these challenges, Siemens has introduced the Fuse EDA AI Agent, an agentic artificial intelligence system designed to automate and optimize electronic design automation (EDA) workflows. This platform represents a major step toward AI-native semiconductor design by enabling end-to-end automation across the entire chip development lifecycle.

One of the key drivers behind the development of the Fuse EDA AI Agent is the rapid escalation in design complexity for modern system-on-chip (SoC) devices. As semiconductor process nodes shrink from 28 nm to advanced nodes such as 3 nm and below, the number of engineering hours required for design and verification increases significantly. The cost of developing a leading-edge SoC can exceed $300 million, making productivity improvements essential for maintaining innovation and competitiveness. Additionally, workforce shortages in the semiconductor industry further increase pressure on design teams.

Artificial intelligence has emerged as a promising solution to improve design efficiency and productivity. According to industry projections, AI-powered EDA tools could deliver more than a 50% productivity boost for chip designers by automating repetitive tasks, accelerating analysis, and enabling smarter decision-making throughout the design process.

The Fuse EDA AI Agent builds on this concept by introducing agentic automation that can plan, orchestrate, and execute complex design workflows.

Traditional EDA workflows involve many steps, including data preparation, tool configuration, simulation, verification, and reporting. These tasks often require engineers to manually coordinate multiple software tools, which can significantly slow development cycles. The Fuse EDA AI Agent addresses this limitation by integrating AI agents capable of managing these processes automatically. These agents can analyze design data, launch simulation tools, validate results, and generate reports without continuous human intervention. By automating these tasks, engineers can focus on higher-level design innovation rather than repetitive operational activities.

The architecture of the Fuse EDA AI system is built on several core technological pillars. These include agent-native workflows, multimodal data management, flexible deployment, granular access control, and multiple integration points for design tools and development environments. Together, these components enable the platform to support complex semiconductor design environments while maintaining high levels of security and scalability.

A key feature of the system is its multimodal EDA data lake, which aggregates large volumes of design data from various sources. Semiconductor design workflows generate diverse data formats such as netlists, layout files, simulation logs, and waveform data. The AI system is capable of parsing and analyzing these formats using specialized domain knowledge trained on semiconductor design workflows. This capability allows the AI agents to interpret design information accurately and generate actionable insights.

Another major innovation of the Fuse platform is its integration with existing Siemens EDA tools, including Calibre, Questa, Tessent, Aprisa, and Xpedition. The system can also interface with third-party development tools through standardized APIs. This open architecture ensures that engineers can adopt AI automation without replacing their existing toolchains. By integrating seamlessly with established EDA environments, Fuse enhances productivity while preserving established design methodologies.

The Fuse EDA AI Agent also introduces agentic workflows, in which multiple AI agents collaborate to complete design tasks. Instead of performing isolated operations, these agents can plan tasks, execute tool operations, analyze results, and iterate on design improvements. Over time, the system can deploy parallel teams of AI agents to address multiple design challenges simultaneously. This distributed AI approach allows semiconductor companies to scale their design processes and reduce overall development time.

Another critical component of the system is its reliance on high-performance computing infrastructure. GPU-accelerated hardware and advanced AI models enable faster simulation and analysis, reducing runtimes that previously required weeks to just hours or minutes. This acceleration significantly shortens design cycles and allows engineers to explore more design alternatives during development.

Ultimately, the Fuse EDA AI Agent aims to deliver three primary benefits: improved design productivity, higher design quality, and an open development ecosystem. By automating complex workflows and leveraging domain-specific AI intelligence, the platform helps engineers produce more reliable designs while reducing time-to-market. At the same time, its open architecture enables collaboration between EDA vendors, foundries, and semiconductor companies, creating a more integrated design ecosystem.

Bottom line: The Fuse EDA AI Agent represents a significant evolution in electronic design automation. By combining agentic AI, domain-specific knowledge, and high-performance computing, the platform transforms how semiconductor devices are designed and verified. As chip complexity continues to increase and AI-driven applications demand more advanced hardware, solutions like the Fuse EDA AI Agent will play a crucial role in enabling the next generation of semiconductor innovation.

 Siemens launches Fuse EDA AI Agent | Siemens

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TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation

TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation
by Daniel Nenni on 03-16-2026 at 10:00 am
Categories: Events, Foundries, TSMC

TSMC Technology Symposium 2026

One of my favorite times of the year is coming (sailing season) and my favorite event of the year is coming as the company I most respect will host the best international semiconductor networking event starting here in Silicon Valley.

The 32nd annual TSMC Technology Symposium represents one of the most influential events in the global semiconductor industry. Organized annually, the symposium brings together semiconductor designers, technology partners, researchers, and industry leaders to discuss the latest advancements in chip manufacturing, packaging technologies, and system integration. The 2026 symposium continues this tradition by highlighting major developments in advanced semiconductor nodes, AI computing, and system-level innovations that will shape the future of electronics.

To me this really is a collaboration victory lap inside the semiconductor ecosystem acknowledging the amazing products we as semiconductor professionals have brought to life. World Changing Technology, and if I may say, World Saving Technology that allows us to live the lives we live today, absolutely.

The event will be held as part of TSMC’s global symposium series, beginning at my favorite location, the Santa Clara, California, and followed by additional sessions in Asia and Europe. These events provide customers and technology partners with updates on TSMC’s semiconductor roadmap and opportunities to collaborate on next-generation chip designs. The symposium focuses on both process technology improvements and the ecosystem required to support modern integrated circuit development.

One of the central themes of the 2026 Technology Symposium will be the rapid growth of artificial intelligence and HPC applications. AI workloads demand extremely powerful processors capable of handling massive data processing and machine learning tasks. TSMC emphasized how advanced semiconductor manufacturing nodes enable higher transistor densities, improved performance, and lower energy consumption, critical requirements for AI data centers, cloud computing infrastructure, and edge devices. The symposium demonstrated how TSMC’s technologies are designed to support these increasingly complex workloads.

Another important focus is the advancement of 2nm-class and angstrom-era semiconductor technologies. TSMC has been preparing for the transition from FinFET to angstrom-scale processes with advanced packaging, representing the next stage of semiconductor scaling. A notable technology in this roadmap is the A16 process, which is expected to enter production in the second half of 2026. This node introduces innovations such as nanosheet transistor structures and backside power delivery, known as Super Power Rail. By delivering power from the backside of the chip rather than the front, this architecture improves signal routing efficiency and supports the high current requirements of advanced processors used in AI and high-performance computing systems.

The symposium will also highlight the importance of system-level innovation, not just transistor scaling. Modern semiconductor performance improvements increasingly rely on advanced packaging technologies, heterogeneous integration, and chiplet-based architectures. Instead of building a single large monolithic chip, designers can combine multiple specialized chiplets in one package to achieve higher performance and flexibility. TSMC’s advanced packaging solutions enable this integration while maintaining high bandwidth communication between chip components.

Another significant aspect of the event is the emphasis on the TSMC ecosystem. Semiconductor manufacturing requires collaboration between many companies, including EDA vendors, IP providers, and system developers. The Technology Symposium allows these partners to demonstrate how their tools and technologies work together with TSMC’s process nodes. In addition, the event often features an Innovation Zone, where startups and emerging companies showcase new semiconductor technologies and design solutions.

The broader semiconductor market context will also influence discussions at the symposium. Demand for advanced chips has increased dramatically due to the growth of AI, data centers, and high-performance computing systems. TSMC has responded by rapidly expanding its manufacturing capacity and investing heavily in new fabrication facilities worldwide. These investments are intended to ensure that the company can meet the rising demand for advanced nodes while maintaining its leadership in semiconductor manufacturing.

Bottom line: The 2026 TSMC Technology Symposium highlights the rapid evolution of semiconductor technology and the critical role that advanced manufacturing plays in enabling future computing systems. From breakthroughs in angstrom-scale process nodes to innovations in packaging and AI computing, the event demonstrated how TSMC continues to push the boundaries of chip design and production. As computing demands continue to grow, the technologies presented at the symposium will play a vital role in shaping the next generation of electronic devices, data centers, and intelligent systems throughout the world.

I hope to see you there!

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Synopsys Explores AI/ML Impact on Mask Synthesis at SPIE 2026

Synopsys Explores AI/ML Impact on Mask Synthesis at SPIE 2026
by Mike Gianfagna on 03-16-2026 at 6:00 am
Categories: AI, EDA, Events, Synopsys

Synopsys Explores AI:ML Impact on Mask Synthesis at SPIE 2026

The SPIE Advanced Lithography + Patterning Symposium recently concluded. This is a popular event where leading researchers gather. Challenges such as optical and EUV lithography, patterning technologies, metrology, and process integration for semiconductor manufacturing and adjacent applications are all covered. This was the 50th anniversary event and it was held in San Jose.

Synopsys had a major presence at the event, but the company went a step further by holding a special Lithography VIP Symposium coinciding with the show. Synopsys and its industry partners gave several excellent presentations on EUV mask making and computational lithography. More on that in a moment. The event concluded with a spirited panel discussion that explored how much of AI/ML for mask making is real today and what the practical impact could be. I was honored to host the panel, AI/ML in Mask Synthesis: Hype vs. Reality for Manufacturing. Let’s review how Synopsys explores AI/ML impact on mask synthesis at SPIE 2026.

The Panel

The panel was composed of senior executives from photomask operations, wafer fabs, and EDA. Together, these folks represent a substantial cross-section of the supply chain for advanced mask making. The panelists were:

Representing photomask

  • Dr. Kent Nakagawa, Technology Marketing Director, Tekscend Photomask US Inc.
  • Dr. Arvind Sundaramurthy, Technology Development and Yield Manager, Intel Mask Operations 

Representing wafer fab

  • Dr. Hyung-Joon Chu, Technical Vice President, Foundry OPC Samsung Electronics Device Solutions Division
  • Dr. Dan J. Dechene, Director of Technology Readiness & Digital Transformation, IBM
  • Dr. Seung-Hune Yang, Master, VP of Technology, Optical Proximity Correction Samsung Electronics

Representing EDA for manufacturing

  • Dr. Larry Melvin, Senior Director of Technical Product Management, Synopsys

The panelists are shown below.

This is a formidable group of highly technical and very smart people. When we were done with the introductions, I resisted the temptation to say, is there a doctor in the house? The comments these panelists made over the course of about an hour taught me a lot and gave me great hope for the future.

The Discussion

To kick things off, I asked, What are the most valuable applications in mask solutions and design enablement that AI and GPUs can unlock? I specifically referenced GPUs in the question. Advanced hardware is the key to making all AI relevant in the real world and I wanted to introduce that reference early.

Kent kicked off the panel with a discussion of the exploding complexity of mask requirements, not just at high NA EUV, but also standard EUV and leading-edge  immersion technologies. The new structures that are needed for advanced AI create this challenge. He went on to say that these requirements are often unique to each customer design, so the complexity is driven by designs and not fab processes. Managing all this to deliver high precision masks requires a new approach, and that’s where AI and special purpose hardware will be needed to move forward.

Arvind went next, and he focused on how GPUs are used in the mask shop to enable the required, highly complex processes such as optical simulation for mask defect prediction. The challenges here include data complexity of course, but also data consistency. He said it wasn’t possible to imagine dealing with these problems just a few years ago. GPUs have been instrumental in paving the way forward.

As Hyung-Joon spoke, a pattern began to emerge. He also focused on the critical requirements of complexity management. He explained that when he onboards new staff members, he tells them that OPC (optical proximity correction) really stands for optimization, prediction and correction. He went on to discuss some of the substantial challenges advanced technology presents. He felt AI and GPUs hold the key to deal with these challenges. He also discussed functional AI (e.g., things like resist and etch models) and agentic AI (to automate the process).

He felt today that a solid base of functional AI was most important. He mentioned the significant challenges posed by changes such as moving from conventional OPC to advanced inverse lithography technology (ILT) and dealing with stochastic vs. deterministic models. Agentic will add efficiency later.

Dan observed a different aspect of the problem. He discussed the move to 3D design and the substantial challenges required to tame 3D metrology. AI and GPUs again were cited as the way forward. Dan also brought in the importance of collaboration across the supply chain. He pointed out that every company represented on the panel had a piece of the budget required to solve this problem. If the supply chain could collaborate to understand the details of the 3D stack, all involved would benefit and stay in business for a very long time.

Seung-Hune focused on the difficulties of delays in production cycle time. Items such as reticle issues can take a long time (months) to correct. So, using AI and GPUs to increase the maturity of the design would have a significant impact.

Larry stepped back and characterized the problem in a fundamental way. He focused on the requirements of model accuracy in the sub-nanometer range. This physically represents two crystal lattice lengths of silicon.  Looking closer, we’re attempting to control many atoms on a layer, all going to the same place at the same time thousands of times per hour. To collect, process and analyze the massive amount of data required to achieve this can only be done with advanced AI algorithms running on the most advanced hardware.  He went on to point out that all this information must be shared up and down the supply chain from design to manufacturing. This is the only way to achieve enough understanding of the whole process to make it work.

I provided all the details of these responses to paint a picture of the overall mood of the panel. It was one of substantial reliance on advanced AI and the associated GPU hardware to continue moving forward. That flattens the question of hype vs. reality for AI/ML in mask synthesis. The panel agreed the technology is real and increasingly necessary, particularly at the leading edge.

My second question examined collaboration aspects: What role do partnerships between EDA vendors, fabs, and equipment suppliers play in accelerating AI/ML innovation for mask solutions and design enablement?

The response from all panelists was quite consistent here. The overall sentiment was that complexity drives the need for more collaboration and partnerships are critical. Recall the group already focused on the need for end-to-end analysis of data. This is only achievable with substantial efforts across the supply chain. A more direct way to say this is: what are the pain points you have associated with AI and how can we verify what we are doing? That is, what are we getting out of the AI?

The problem of highly sensitive fab data (think defect density) was also brought up. There was a genuine focus on how to minimize this problem. That is, how to make sure AI models are trained with accurate data. Otherwise, the usefulness of these models is quite limited. Think garbage in, garbage out. Having lived in semiconductors and EDA for many years, the tone of this discussion was quite uplifting for me. This group truly believed that better collaboration is a must to tame the substantial problems before us. I can tell you it wasn’t always like this.

I’ll conclude with the overall response to my last question, How will Al/ML impact mask and lithography workflows over the next five years?

While panelists approached the problem from different parts of the value chain, there was strong alignment on direction and priorities.  Impact always starts at the leading edge. There is an overall conservative attitude in this group. The stakes are too high to do it any other way. This means the leading edge will see benefit in the next five years, but broader impact will likely take longer. In terms of the technology, the feeling was that generative AI will enable better understanding of the models and result in a wider impact, and so that will lead the way. Agentic AI will face larger deployment challenges and will come later.

It was a genuine pleasure to lead this panel discussion. I believe we all came away with an optimistic view of the future. A future where the impact of AI was understood and valued, and the importance of collaboration was also understood and valued. Below is a photo of the panel and our executive host from Synopsys, Dr. Kostas Adam (far left).

The Rest of the Session

The Synopsys Lithography VIP Symposium also contained several excellent technical presentations. Here is a summary:

  • Enabling the Future: How GPUs are reshaping computational lithography. Michael Lam, Senior Director of Modeling at Synopsys.
  • Advances in EUV Mask Manufacturing. Arvind Sundaramurthy, Head of Integration and Yield at Intel.
  • The Dimensional Explosion: Navigating Super-Linear Computational Complexity in Semiconductor Scaling. Ryoung-Han Kim, Litho Program Director at imec.
  • Automating EDA with AI – Are agents going to replace engineers? Thomas Andersen, VP Engineering, AI and Innovation at Synopsys.

To Learn More

Synopsys offered many presentations at the SPIE Advanced Lithography + Patterning Symposium. You can see a summary of those presentations here. And that’s how Synopsys explores AI/ML impact on mask synthesis at SPIE 2026.

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Unraveling Dose Reduction in Metal Oxide Resists via Post-Exposure Bake Environment

Unraveling Dose Reduction in Metal Oxide Resists via Post-Exposure Bake Environment
by Daniel Nenni on 03-15-2026 at 4:00 pm
Categories: Events, Lithography
1 Comment

Unraveling Dose Reduction in Metal Oxide Resists via Post Exposure Bake Environment

In the realm of extreme ultraviolet (EUV) lithography, metal oxide resists (MORs) have emerged as promising candidates for advanced semiconductor patterning. However, their stability poses challenges, particularly interactions with clean-room environments like humidity and airborne molecular contaminants (AMCs) post-exposure. Researchers at imec, led by Ivan Pollentier, Fabian Holzmeier, Hyo Seon Suh, and Kevin Dorney, have developed a novel platform called BEFORCE to probe these effects. Presented at SPIE Advanced Lithography + Patterning in February 2026, their work unveils a dose reduction strategy by optimizing the atmospheric conditions during post-exposure delay (PED) and post-exposure bake (PEB).

BEFORCE integrates a bake and EUV system with Fourier-transform infrared (FTIR) spectroscopy and outgas measurements, enabling precise control over environmental variables. This setup allows evaluation of MOR in controlled atmospheres, addressing stability concerns that arise mostly after EUV exposure. The platform’s design facilitates experiments where gases like nitrogen (N2), carbon dioxide (CO2), and clean air (CA) are mixed with controlled relative humidity (RH%) and oxygen (O2) levels via mass flow controllers (MFCs). Initial findings from imec’s press release on February 25, 2026, highlight BEFORCE’s potential to enhance MOR performance.

A key focus is enhancing EUV dose response through PED/PEB environments. Dose-to-gel (D2G), a metric of photo-speed, serves as the primary indicator. Experiments show that oxygen concentration significantly influences condensation and dose requirements. In atmospheres with less oxygen than standard air (21% O2), condensation is minimal, but increasing O2 to 50% yields a 25-30% reduction in D2G. This suggests oxygen’s role is not saturated at nominal levels; higher concentrations accelerate the photochemical reactions leading to gelation, thus lowering the required EUV dose.

Humidity’s impact is nuanced and interdependent with oxygen. At low O2 levels, higher humidity improves photo-speed, mainly by aiding condensation in oxygen-scarce environments. Graphs from the study depict D2G decreasing sharply with rising humidity under low O2, but the effect plateaus or reverses in high-O2 settings. For instance, at 5% RH, increasing O2 from 0% to 50% reduces D2G by up to 30%. Conversely, in low-O2 conditions, humidity drives a steeper drop in D2G, indicating it compensates for oxygen’s absence in promoting resist cross-linking.

To disentangle PED and PEB contributions, the team conducted separate environment tests. Using a model MOR, they varied conditions: PED in air (21% O2, 45% RH) followed by PEB in vacuum, or vice versa. Results reveal that PEB atmosphere dominates condensation. PEB in air promotes significant film thickness changes indicative of condensation, while vacuum PEB suppresses it, regardless of PED conditions. Preliminary data with 120-second PED/PEB cycles underscore this: vacuum PEB yields higher D2G (slower photo-speed), but air PEB enhances sensitivity. This implies chemical transformations during baking are more sensitive to ambient gases than during delay.

Further inter-relations emerge with PEB temperature and time. At ~5% RH, oxygen trends hold across temperatures, but in zero-O2 environments, photo-speed remains stable, suggesting temperature independence without oxygen. With O2 present, longer PEB times significantly boost photo-speed, hinting at kinetic chemical effects. Kevin Dorney’s related talk (SPIE 13983-50) explores these origins, proposing mechanisms like ligand exchanges in MOR structures (e.g., OH to other groups).

The study opens avenues for co-optimization: tuning O2, humidity, temperature, and time could reduce doses by 25-30%, improving throughput in EUV lithography. For commercial MORs, humidity aids condensation without strong oxygen dependence, aligning with model resists but showing subtler effects.

Bottom Line: imec’s BEFORCE demonstrates that PEB environment is pivotal for MOR dose reduction. By elevating O2 and modulating humidity, manufacturers can enhance sensitivity without compromising stability. Acknowledgments go to Intel and resist suppliers for materials. Funded by the EU’s Chips Joint Undertaking and partners like Belgium and France, this research paves the way for efficient, environmentally tuned EUV processes, potentially revolutionizing high-volume semiconductor fabrication.

More information

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