SemiWiki – Page 9 – The Open Forum for Semiconductor Professionals

April 30, 2026April 30, 2026

Advanced Microelectronics Paving the Way for 6G with Alphacore

Advanced Microelectronics Paving the Way for 6G with Alphacore
by Daniel Nenni on 04-30-2026 at 6:00 am
Categories: Alphacore, IP

The world stands at the threshold of a new era in wireless communication as research communities, standards bodies, and technology companies begin shaping what will become sixth generation mobile networks. While fifth generation systems are still expanding across global markets, attention has already shifted toward defining the capabilities, performance targets, and architectural principles of 6G. This transition is not merely about increasing data rates. It represents a broader transformation in how networks sense, compute, and interact with the physical world. At the heart of this transformation lies microelectronics, whose progress will determine whether ambitious visions can become practical realities.

The development of 6G is guided in part by the International Telecommunication Union through its IMT 2030 framework. This framework outlines performance expectations that extend beyond traditional metrics such as throughput and latency. Future networks are expected to integrate sensing and communication, embed artificial intelligence deeply into their operation, and provide seamless connectivity across terrestrial and non terrestrial domains. In parallel, industry groups such as the Third Generation Partnership Project are preparing study items and future specifications that will eventually formalize these goals into implementable standards. Yet standards alone cannot create a new generation of wireless systems. The feasibility of 6G depends on the capabilities of semiconductor technologies that must support higher frequencies, wider bandwidths, and tighter integration than ever before.

One of the most visible shifts in 6G research is the exploration of new spectrum regions, including upper millimeter wave and sub terahertz bands. These frequencies promise extremely wide channel bandwidths and unprecedented peak data rates. However, operating above one hundred gigahertz introduces formidable challenges. Signal attenuation increases, power amplifier efficiency declines, and maintaining linearity becomes more difficult. Thermal constraints intensify as devices attempt to deliver greater output power in compact form factors. In this regime, the physical properties of semiconductor materials, device geometries, and packaging techniques become decisive factors in system performance.

Massive antenna arrays and advanced beamforming further amplify the demands placed on microelectronics. Future base stations and terminals may rely on dense phased arrays that require precise timing, calibration, and mixed signal processing. Each antenna element must be supported by radio frequency circuitry and data converters capable of handling wide instantaneous bandwidths. As arrays grow larger, integration density and power efficiency become critical. The burden on silicon is not only to process signals but to do so within strict energy budgets that align with sustainability goals and practical deployment constraints.

Another defining feature of 6G is the integration of artificial intelligence into network operation. Rather than treating intelligence as an overlay, future systems are expected to incorporate learning and optimization directly into the air interface, resource management, and service orchestration layers. This shift increases the need for specialized accelerators and efficient digital processing units at the edge of the network. Delivering high compute performance per watt will require careful co design of logic, memory, and radio frequency components. Heterogeneous integration techniques that combine complementary semiconductor processes within a single package are likely to play a central role.

Advanced packaging is emerging as a key enabler rather than a secondary consideration. At very high frequencies, interconnect parasitics and package losses can significantly degrade signal integrity. Shortening signal paths through two and three dimensional integration can reduce these effects while enabling tighter coupling between antennas and radio circuitry. By combining silicon based logic with silicon germanium or compound semiconductor devices optimized for high frequency operation, designers can exploit the strengths of multiple technologies within one system.

Bottom line: The journey to 6G will be shaped by the pace of innovation in microelectronics research and development. Achieving the goals envisioned for IMT 2030 requires more than incremental improvements. It calls for breakthroughs in device efficiency, converter performance, thermal management, and system integration. As the industry moves from conceptual studies to formal specifications, the collaboration between standards experts and semiconductor engineers will be essential. Only by aligning ambitious performance targets with the realities of physics and manufacturing can 6G evolve from aspiration to deployment, delivering networks that are not only faster but also more intelligent, reliable, and deeply integrated into the fabric of society.

For more detailed information about the importance of microelectronics in 5G/6G and Alphacore’s role in this development, download the whitepapers “Microelectronics Paving the Way for 6G” and “ML in Microelectronics”. Please also feel free to explore analog, mixed signal and RF solutions on Alphacore’s website https://alphacoreinc.com/analog-mixed-signal-rf-solutions/ and reach out to us for further information https://alphacoreinc.com/analog-mixed-signal/contacts/#Form

References terms:

Massive Machine Type Communications (mMTC) is a 5G technology designed to support connectivity for billions of IoT devices.
Integrated Sensing and Communication (ISAC) is a cornerstone 6G technology that merges wireless communication with radar-like sensing, allowing network infrastructure to detect, track, and image objects in real-time.
Enhanced Mobile Broadband (eMBB) for centric private networks are tailored 5G deployments designed specifically to provide high-speed, high-capacity connectivity within a defined, private area.
SMART: Scalable Modular Architecture for RF Transceivers

Also Read:

A Tour of Advanced Data Conversion with Alphacore

Analog to Digital Converter Circuits for Communications, AI and Automotive

High-speed, low-power, Hybrid ADC at IP-SoC

CEO Interview: Dr. Esko Mikkola of Alphacore

April 29, 2026April 29, 2026

Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration

Enabling Next-Generation AI Through Advanced Packaging and 3D Fabric Integration
by Kalar Rajendiran on 04-29-2026 at 10:00 am
Categories: 3D IC, AI, Chiplet, Foundries, TSMC

The rapid rise of artificial intelligence is fundamentally reshaping computing architectures. As AI models scale toward trillions of parameters, traditional approaches to performance improvement are no longer sufficient. Instead, the industry is entering a new era where system-level innovation, advanced packaging, and 3D integration are becoming the primary drivers of progress. This shift reflects a broader transition in computing, where performance gains increasingly depend on how well entire systems are designed and integrated, rather than how small individual transistors can become.

The End of One-Dimensional Scaling

AI compute demand is growing at an exponential rate, creating a widening gap between required performance and what conventional silicon scaling can deliver. Bridging this gap requires innovation beyond the chip itself. The most important shift is that AI performance is now determined at the system level rather than purely at the silicon level. Future gains will depend on how effectively compute, memory, interconnect, and power systems are integrated into a cohesive whole. This marks a transition from device-centric optimization to full-stack co-design, extending from transistor technology all the way to data center architecture.

Data Movement Is the New Bottleneck

A critical constraint in modern AI systems is no longer computation, but data movement. Transporting data across chips can consume up to 50 times more energy than moving data within a single chip. At the same time, data transfer can account for the majority of system activity, significantly reducing accelerator utilization due to communication delays. This shift makes interconnect efficiency a central design priority. Improving bandwidth, reducing latency, and minimizing energy per bit are now essential to unlocking overall system performance.

The Memory Wall Is Getting Worse

As AI models continue to scale, memory demands are increasing even faster than compute capabilities. Emerging workloads, such as long-context processing and multimodal AI, are driving exponential growth in both memory capacity and bandwidth requirements. Systems are transitioning from gigabyte-scale memory to terabyte-scale configurations, while also demanding lower latency. However, memory technology is not advancing at the same pace as compute, creating a widening imbalance. Overcoming this “memory wall” is therefore essential for sustaining AI progress, and it is driving rapid innovation in high-bandwidth memory and memory integration strategies.

Power and Thermal Constraints Are Critical

The increase in compute density, particularly with the adoption of 3D stacking technologies, has led to a corresponding rise in power density and heat generation. These factors are quickly becoming limiting constraints for AI system scaling. Without significant advancements in power delivery, energy efficiency, and thermal management, performance gains cannot be sustained. As a result, power and cooling are no longer secondary considerations but have become central to system design and overall performance.

3D Fabric Technologies: The New Foundation

To address these challenges, advanced 3D fabric technologies are emerging as the foundation of next-generation AI systems. These technologies enable the integration of multiple chips and components into highly efficient, high-performance systems. Innovations such as 3D chip stacking allow for dramatically higher interconnect density, reducing both data movement distance and energy consumption. Advanced packaging platforms make it possible to combine logic and memory in close proximity, enabling massive bandwidth and capacity scaling. At the same time, high-bandwidth memory continues to evolve, delivering higher throughput and improved energy efficiency. Together, these advancements position packaging not merely as a supporting technology, but as a primary driver of system performance.

Co-Packaged Optics: Rethinking Interconnects

As electrical interconnects approach their physical limits, co-packaged optics is emerging as a promising solution for high-speed data transfer. By integrating photonics directly with compute hardware, this approach enables significant improvements in both power efficiency and latency. It also provides a scalable path forward for data center networking, where the need for higher bandwidth and lower energy consumption continues to grow. This evolution signals a broader shift toward optical technologies as a key enabler of future AI infrastructure.

System-on-Wafer and Wafer-Scale Integration

Looking further ahead, system integration is advancing toward wafer-scale architectures, where entire systems are built on a single substrate. This approach enables unprecedented levels of integration density while reducing the overhead associated with traditional interconnects. By minimizing communication distances and improving efficiency, wafer-scale integration offers a powerful pathway for scaling AI performance beyond the limits of conventional packaging methods.

The Rise of System Technology Co-Optimization (STCO)

As AI systems grow more complex, optimizing individual components in isolation is no longer sufficient. The industry is increasingly adopting System Technology Co-Optimization, an approach that simultaneously considers chip design, packaging, interconnects, power delivery, and thermal behavior. This holistic methodology ensures that all parts of the system are designed to work together efficiently, enabling better overall performance and energy efficiency. It represents a fundamental shift in how hardware systems are conceived and developed.

Summary

The future of AI hardware will not be defined by silicon scaling alone. Instead, it will be shaped by advances in packaging, interconnects, memory systems, and power efficiency, all brought together through system-level design. In this new paradigm, the system itself becomes the primary unit of innovation. Success will depend on the ability to integrate across multiple domains and optimize them collectively. As this transformation continues, it is clear that the “system” has effectively become the new chip, redefining how performance is achieved in the age of AI.

Also Read:

Dr. Cliff Hou and the TSMC N2 Process Technology

The Shift to System-Level AI Drives Next-Generation Silicon

All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die

TSMC Technology Symposium 2026 Overview

April 29, 2026May 11, 2026

WAVE-N Specialized Video Processing NPU for Edge AI Systems

WAVE-N Specialized Video Processing NPU for Edge AI Systems
by Daniel Nenni on 04-29-2026 at 6:00 am
Categories: Chips&Media, IP

The rapid growth of AI applications in edge devices has created a strong demand for specialized hardware capable of performing high-performance neural network inference under strict power and latency constraints. Traditional CPUs and GPUs often struggle to meet the efficiency requirements of embedded and mobile systems. As a result, dedicated neural processing units (NPUs) have emerged as a key technology for accelerating deep learning workloads. The WAVE-N specialized video processing NPU, developed by Chips&Media, represents a modern approach to integrating AI acceleration with video processing pipelines for next-generation edge devices.

At the core of the WAVE-N architecture is the need to address the computational demands of deep learning models used in computer vision and video analytics. Recent trends in AI development demonstrate that increasing model size and complexity often leads to improved accuracy and performance. However, this scaling law significantly increases computational requirements. Edge devices such as smart cameras, drones, autonomous robots, and automotive systems cannot rely on cloud infrastructure due to latency, privacy, and connectivity constraints. Therefore, local processing with highly optimized hardware is essential.

The WAVE-N NPU is designed specifically to accelerate neural network workloads related to video and image analysis. These workloads include object detection, motion tracking, image classification, super-resolution, and other computer vision tasks. Unlike general-purpose processors, an NPU implements specialized hardware units optimized for matrix multiplication, convolution operations, and tensor processing, which are the fundamental building blocks of deep neural networks. By implementing these operations in dedicated hardware, the NPU achieves significantly higher throughput and energy efficiency compared with CPU-based processing.

One of the key architectural features of WAVE-N is its parallel processing capability. Neural network inference involves executing a large number of arithmetic operations on multidimensional data structures known as tensors. WAVE-N uses a highly parallel compute engine that distributes these operations across multiple processing elements, allowing simultaneous execution of convolution and activation functions. This massively parallel design dramatically reduces inference latency and increases throughput for real-time video applications.

Another important component of the WAVE-N system is its optimized memory architecture. Memory bandwidth and data movement are critical bottlenecks in AI accelerators. Large neural network models require frequent access to weights, feature maps, and intermediate results. WAVE-N addresses this challenge by integrating high-efficiency on-chip memory buffers and intelligent data reuse mechanisms. These features minimize external memory access and reduce energy consumption while maintaining high computational performance.

Software support also plays a vital role in the usability of hardware accelerators. The WAVE-N platform includes a software simulation and development package that enables developers to design, test, and optimize neural network models before deployment on hardware. This simulation environment allows engineers to evaluate performance characteristics, estimate throughput, and refine model architecture without requiring physical silicon. Such tools significantly shorten development cycles and facilitate integration into complex embedded systems.

In addition to raw performance, scalability and flexibility are critical design goals. The WAVE-N architecture supports various neural network frameworks and can be configured for different performance targets depending on the application. For example, lightweight configurations may be used in low-power IoT devices, while larger configurations can support high-resolution video analytics in smart surveillance systems or automotive platforms.

The applications of specialized video processing NPUs extend across many industries. In smart security systems, WAVE-N can enable real-time object detection and behavioral analysis directly on edge cameras. In automotive environments, the NPU can accelerate driver assistance features such as pedestrian detection, lane recognition, and traffic monitoring. Similarly, robotics and industrial automation systems can leverage the hardware for rapid visual perception and decision-making.

Bottom line: The WAVE-N specialized video processing NPU represents a significant advancement in edge AI hardware design. By combining parallel computation, optimized memory management, and dedicated neural network acceleration, it delivers high performance while maintaining power efficiency. As AI models continue to grow in complexity and edge computing becomes increasingly important, specialized NPUs like WAVE-N will play a critical role in enabling intelligent, real-time processing directly on embedded devices.

CONTACT CHIPS&MEDIA

Also Read:

Chips&Media and Visionary.ai Unveil the World’s First AI-Based Full Image Signal Processor, Redefining the Future of Image Quality

CEO Interview with Steve Kim of Chips&Media

Complex PCB signoff challenges

April 28, 2026April 26, 2026

Complex PCB signoff challenges

Complex PCB signoff challenges
by Daniel Payne on 04-28-2026 at 10:00 am
Categories: EDA, Siemens EDA

Many complex PCB designs have high data-rate signals like USB, PCIe, DDR and HDMI which call for more thorough verification methods to ensure compliance plus mitigate any signal integrity, power integrity and EMI/EMC issues. Siemens has a methodology that uses automated rule-based electrical verification with an EDA tool, HyperLynx DRC. This blog stems from reading their white paper. The old method of manual verification is just too slow and inadequate to ensure no respins.

The complexity and density of PCBs have increased significantly over the last 20 years, creating the need for multiple specialized verification experts, which can add more bottlenecks in the design process. Design teams require detailed knowledge of protocols and new verification techniques to be successful.

Electrical verification can take significant time for tasks like model set up and validation, often leading to delays. Models range from datasheets to complex S-parameters and even extracted 3D structures. EDA tool complexity can reduce engineering efficiency, so using automation helps improve productivity. Stitching together multiple point tools from different vendors increases CAD integration efforts. The goal should be automating tasks and shifting verification to earlier in the design process.

Point EDA Tools

Traditional manual inspection and verification are both time-consuming and prone to human error, especially when it’s performed only at the end of design. The manual approach has visual checks performed layer-by-layer and net-by-net, with only critical nets and corner cases manually simulated. This leads to only partial inspection, risking missed issues. In contrast, automated DRCs can be run throughout the design cycle, actually saving time and reducing errors.
Proper targeting of PCB areas via object lists and parameter settings is crucial for efficient rule checks using HyperLynx DRC. There are system-generated object lists that filter components automatically.

System object lists

In addition there are user-defined object lists to target specific signals or protocol, where parameters reflect actual design choices, such as high-speed net names or voltage levels. Proper set up reduces false violations and streamlines verification.

DDR4 net naming user list

Rules in HyperLynx are organized into groups within .hldset and .hldproj files, enabling reuse across projects. The default .hldset file provides a starting point to save and capture object lists and rule groups that users define. Custom rule libraries can be created for different technologies and shared between PCB projects and with a hierarchical organization it allows inheritance. Having reusable rule setups improve consistency and efficiency.

HyperLynx DRC detects EMI/EMC issues like metal islands and return path breaks rapidly, typically in seconds, unlike visual inspection which takes 30 minutes to an hour. As an example this metal island detection completed in just 2 seconds.

There are even rule checks for return path continuity during layer changes, so that violations, such as reference plane breaks, are highlighted with correction advice. Detection time for EMI issues is under a minute, aiding quick fixes with HyperLynx.

Automated signal integrity (SI) rules identify issues like impedance discontinuities and crossing gaps efficiently, so that you can focus on easy fixes first to reduce modeling workload. The key rules include impedance and differential impedance checks. Nets crossing gaps are automatically checked for impedance change and reflection risks.

Power delivery is verified through rules that ensure proper decoupling and grounding. The out-of-the-box rules cover decoupling capacitor placement and coverage. Checks include minimum distance from IC power pins to decoupling capacitors. These rules help prevent AC analysis failures and validate layout spacing and component placement for effective power delivery.

Power integrity rules

HyperLynx DRC offers scripting environments for creating your own tailored rules, and you can learn more about these by attending Siemens training. Custom rules can be written in VBScript or Python, and they address complex or proprietary design needs. There are over 100 pre-defined rules that span SI, power integrity (PI), EMI/EMC, and high voltage safety, forming a foundation for effective verification. Siemens offers The Getting Started Workshop to get you up to speed on these quickly.

Summary

PCB verification and sign-off has multiple steps, requiring an understanding of SI, PI and EMI/EMC issues that cause board respins. Using an automated, rule-based verification approach will speed up PCB sign-off, reducing manual effort, and minimizing the risk of respins.

Instead of using visual inspection only once at the end of a project, the automated DRC approach in HyperLynx DRC enables continuous verification during the design process.

Read the entire 27 page White Paper online.

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April 28, 2026April 27, 2026

Dr. Cliff Hou and the TSMC N2 Process Technology

Dr. Cliff Hou and the TSMC N2 Process Technology
by Daniel Nenni on 04-28-2026 at 8:00 am
Categories: Events, Foundries, TSMC

Cliff Hou, Senior Vice President and Deputy Co COO, TSMC

Dr. Cliff Hou is Senior Vice President, Deputy Co-COO, and Chief Information Security Officer at TSMC, where he also serves as deputy to Y.P. Chyn. Over a long career with the company since joining in 1997, he has played a pivotal role in advancing TSMC’s design technology and ecosystem strategy.

Before assuming his current position, Dr. Hou held several key leadership roles. He served as Vice President of Design and Technology Platform from 2011 to 2018, and later as Vice President of Technology Development starting in August 2018. Earlier in his career, from 1997 to 2007, he established TSMC’s technology design kit and reference flow development organizations, laying the foundation for its design enablement infrastructure.

Over the past decade, Dr. Hou has been instrumental in building TSMC Open Innovation Platform (OIP), which has grown into one of the most comprehensive design ecosystems in the global semiconductor industry. His work in reference flows and design-for-manufacturing (DFM) has significantly lowered barriers to IC design and improved accessibility for customers.

In recognition of his contributions, Dr. Hou received the National Manager Excellence Award in 2010. He also led TSMC’s OIP project team to win the National Industry Innovation Award in 2011, presented by the Ministry of Economic Affairs in Taiwan.

Prior to joining TSMC, Dr. Hou worked at the Industrial Technology Research Institute (ITRI/CCL) as a section manager focused on design environments. He also served as an associate professor at I-Shou University (formerly Kaohsiung Polytechnic Institute).

Dr. Hou holds 44 U.S. patents and serves on the board of directors of Global Unichip Corp.. He earned his bachelor’s degree in control engineering from National Chiao Tung University and a Ph.D. in electrical and computer engineering from Syracuse University.

Cliff’s presentation outlined the significant progress and achievements made by TSMC over the past year in semiconductor manufacturing, focusing on technology advancement, capacity expansion, advanced packaging, global footprint, and sustainability initiatives.

In 2025 TSMC made strong strides in both cutting-edge technology and production capacity. The company’s most advanced node, TSMC N2, has already entered volume production. Despite its increased complexity compared to previous generations, TSMC has achieved an improved yield learning curve, demonstrating its manufacturing excellence. The next iteration, featuring backside power delivery remains on track and is progressing according to schedule.

TSMC has also made advancements in automotive technology, with its N3A node now production-ready and capable of meeting stringent quality requirements. Across all advanced nodes, including 3nm, 5nm, and 7nm, the company continues to refine performance and reliability to support a wide range of applications. Additionally, TSMC is aggressively expanding its advanced packaging technologies to meet growing demand for HPC and AI applications.

A major highlight is the rapid expansion of 2nm production capacity. TSMC is ramping up five phases of 2nm fabs within a single year—an unprecedented pace. As a result, first-year output for 2nm is projected to be 45% higher than that of the previous 3nm generation. Looking ahead, the company plans to further increase 2nm capacity by approximately 70% between 2026 and 2028. Meanwhile, combined capacity for 3nm and 5nm technologies is expected to grow steadily by about 25% over several years.

To address the time constraints associated with building new fabs, TSMC is leveraging artificial intelligence and digital transformation to optimize existing facilities. AI-driven systems improve scheduling, equipment efficiency, and process optimization, enabling higher throughput and reduced production cycle times. Generative AI is also used to fine-tune process parameters, while data analytics helps minimize downtime and maximize tool utilization. These innovations allow TSMC to extract greater productivity from existing capacity while new fabs are under construction.

Demand for AI and HPC applications is a key driver of growth. From 2022 to 2026, the number of wafers shipped for AI accelerators is expected to increase elevenfold. Notably, large-die chips (over 500 mm²) are also seeing strong growth, with shipments increasing sixfold. TSMC’s accumulated experience across multiple generations has enabled consistent improvements in yield and defect density, even for these complex designs.

Beyond leading-edge technologies, TSMC continues to invest in mature nodes, including specialty processes such as radio frequency, high-voltage, analog, embedded memory, and image sensors. The company aims to remain the leading provider in this segment while expanding capacity in a measured and strategic manner.

In advanced packaging, TSMC is pushing the boundaries of 3D integration technologies, such as CoWoS and SoIC. These technologies are critical for enabling chiplet-based architectures and high-bandwidth memory integration. The company has reduced the time required to transition from development to high-volume manufacturing—by 30% for CoWoS and 75% for SoIC—helping customers bring products to market faster. Collaboration with ecosystem partners, including material suppliers and testing providers, has further improved yield and manufacturing efficiency. Packaging capacity is also expanding aggressively, with significant growth projected through 2027.

TSMC’s global expansion strategy is another key focus. The company is doubling its pace of fab construction, with nine new or converted phases planned annually in 2025 and 2026—twice the historical average. This expansion extends beyond Taiwan to include major investments in the United States, Japan, and Germany.

In Arizona, TSMC’s first fab is already in production, with additional phases under construction targeting advanced nodes such as 3nm and 2nm. The company is also planning advanced packaging facilities and acquiring additional land to support long-term growth. In Japan, the Kumamoto fab has entered production and is expanding capacity, while a second fab is being developed with a revised focus on 3nm technology. In Germany, a new fab in Dresden is under construction, targeting automotive and industrial applications. Across these regions, TSMC has demonstrated the ability to replicate high yields comparable to its Taiwan operations.

Sustainability and green manufacturing are central to TSMC’s long-term vision. The company aims to achieve net-zero carbon emissions by 2050 and has already reduced emissions by 3.8 million tons in 2025 alone. Resource recycling is another priority, with goals of 70% internal recycling and up to 98% total recycling by 2030. Water stewardship initiatives target 100% water positivity by the 2040s, with significant progress already made through reclaimed water usage and conservation efforts.

Bottom line: TSMC is aggressively advancing semiconductor technology while scaling capacity to meet surging demand, particularly in AI and HPC. Through innovation in manufacturing, packaging, and AI-driven optimization, combined with global expansion and sustainability commitments, the company is positioning itself to remain a leader in the semiconductor industry for years to come.

Also Read:

TSMC Technology Symposium 2026 Overview

TSMC to Elon Musk: There are no Shortcuts in Building Fabs!

TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation

April 28, 2026April 29, 2026

UX in Agentic Systems. Innovation in Verification

UX in Agentic Systems. Innovation in Verification
by Bernard Murphy on 04-28-2026 at 6:00 am
Categories: AI, Cadence, EDA

A switch this month to principles behind building effective agentic systems, going beyond simply a new way to stitch together tools, agents and orchestration, to deeper consideration of user experience and how we most effectively blend agentic with human-in-the-loop. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Magentic-UI- Towards Human-in-the-loop Agentic Systems. The authors are from Microsoft Research. The paper was published in arXiv in 2025 and has 19 citations.

How can we ensure that agentic system assemblies don’t compound uncertainty and complexity in operation? This paper from Microsoft Research describes a web-based platform (open-source under GitHub) for researching how to optimize user experience (UX) and confidence in control by systematizing collaboration between agents and human-in-the-loop, a very relevant topic these days.

This isn’t a deeply technical paper, but it does offer plenty of interesting ideas on co-planning, co-tasking, action guards, and learning from task execution.

Paul’s view

Intriguing paper this month out of Microsoft Research, exploring how to keep a human “in the loop” during long running complex agentic AI tasks. With 2026 shaping up to be a big year for applying agentic AI to RTL design and verification, how best to keep DV engineers and RTL designers in the loop is a hotly debated topic with our customers.

The paper summarizes various methods to keep a human in the loop based on the underlying workflow-based architecture on which modern agents approach complex tasks. For example, an agent usually begins by asking the LLM to break the task down into a multi-step plan consisting of smaller more manageable sub-tasks which are then swarmed out to sub-agents to complete. A quick summary of the methods proposed in the paper is as follows:

Co-planning: check back in with the user after the initial multi-step plan is generated.
Co-tasking, part 1: have agents continuously communicate what they are doing to a live stream that the user can watch and intercept if an agent is going off the rails.
Co-tasking, part 2: Provide instructions in prompts that guide agents to seek user clarification or confirmation in certain situations.
Memory: whenever an agentic session is successful at a task, the user can save that session to a side file by running an agent to review and summarize its live stream traces into a prompt that can guide a future agentic session. What we now call a “skill”. The live stream traces also include all the human interventions, so the saved skill can include instructions on when to prompt the user.

The authors implement their methods in a system called Magentic-UI and benchmark it on a well-known agentic AI benchmark called GAIA by creating a special agent that operates as a surrogate for a real human. This “simulated user” is given a cheat sheet of golden human created reference plans for how to complete each of the tasks in the benchmark. Magentic-UI achieves a 30% score when it’s told never to prompt the user, and a 50% score when allowed to prompt the simulated user. A human performing the tasks entirely on their own with a web browser scores 90%. Hard to know if the 50% to 90% gap is due to limitations in the simulated user agent or the human prompting methods themselves, but either way it’s a big gap, so plenty of room for further innovations here!

Raúl’s view

This month’s paper is about Magentic-UI: Towards Human-in-the-loop Agentic Systems, an open-source prototype interface from Microsoft Research for studying human-in-the-loop agentic systems. The premise is straightforward: today’s agents are not reliable enough to operate autonomously, so productivity comes from combining agent execution with human oversight.

Magentic-UI is built as a multi-agent architecture that explicitly treats the human as part of the agent team. Its main contribution is a set of six interaction mechanisms:

Co-planning (joint human–agent plan creation)
Co-tasking (shared execution)
Action guards (human approval of risky actions)
Answer verification (post hoc validation of results)
Memory (reuse of prior plans)
Multi-tasking (parallel agent execution with human oversight)

Evaluations include benchmarks (GAIA, WebVoyager, etc.), simulated users, and a small qualitative study. The authors conclude that these mechanisms “have the potential to improve task success and reduce oversight burden.”

Two issues stand out.

First, the evaluation is weak. A ~10–12 person, one-hour user study is not statistically meaningful, and simulated users (LLMs) are a poor proxy for real human behavior. The authors themselves position the study as qualitative.

Second, the idea of a standard interface for agentic AI is questionable. History suggests otherwise: different ecosystems optimize for different interaction models. Google tends toward minimalist, search-centric interfaces (one box, increasingly agentic underneath), Microsoft favors feature-rich, layered interfaces (Office, now Copilot everywhere). Agentic systems will likely fragment by context, for consumers, largely invisible automation; for enterprises, audit-heavy workflows; for developers, programmable pipelines.

The system also remains far from human-level performance (roughly 30–50% task success vs. ~90% for humans on some benchmarks), and only 41.7% of users in the study said they would use it frequently. This reinforces the paper’s premise but also highlights that the interface does not solve the core capability gap.

Despite these limitations, the paper is worth reading. It clearly defines human–agent interaction patterns (co-planning, co-tasking, etc.), tightly integrates agents with UI, introduces practical safety ideas like action guards, and argues for a plan-centric interface that improves transparency and control. Most importantly, it shows how humans can collaborate with imperfect agents, rather than assuming near-term full autonomy.

Magentic-UI sits within a broader movement toward agentic interfaces. Google appears to be pushing toward invisible, search-centric agents, while Microsoft is embedding agents into rich, Office-like workflows. My view is that agent interfaces will fragment across use cases rather than converge.

April 27, 2026April 27, 2026

Scalable Network-on-Chip Enables a Modular Chiplet Platform

Scalable Network-on-Chip Enables a Modular Chiplet Platform
by Daniel Nenni on 04-27-2026 at 10:00 am
Categories: Arteris, IP

The semiconductor industry is undergoing a profound transformation as system complexity, performance expectations, and time-to-market pressures continue to rise. Traditional monolithic system-on-chip (SoC) designs are increasingly giving way to modular, chiplet-based architectures that enable flexibility, scalability, and faster innovation cycles. Within this evolving landscape, the collaboration between Menta and Arteris illustrates how a scalable NoC strategy can serve as the backbone of a modular silicon platform.

Founded in 2007, Menta has established itself as a pioneer in eFPGA IP, delivering highly configurable programmable logic solutions for integration into SoCs and ASICs. Its focus on measurable performance gains, power efficiency, and long-term sustainability has positioned the company strongly in high-value embedded markets such as edge AI, robotics, industrial automation, and smart vision systems. As system requirements expanded, Menta recognized the need for a more advanced integration framework capable of supporting heterogeneous chiplets across multiple generations and configurations.

This vision materialized in the MOSAICS platform, a modular chiplet-based architecture designed to rethink how custom silicon systems are built and deployed. At the center of this platform is the MOSAICS Hub, delivered as a Known Good Die to ensure predictable system integration. The Hub orchestrates communication among diverse chiplets, enabling system-in-package designs with significantly reduced risk. The platform promises up to ten times lower system costs and up to four times faster time-to-market, reflecting a strong emphasis on scalability and ecosystem enablement.

However, realizing this vision required overcoming significant technical challenges. A chiplet-based architecture demands a robust on-chip communication infrastructure capable of managing both bandwidth-intensive data transfers and latency-sensitive control transactions. The interconnect must scale across multiple chiplet generations while maintaining performance, area efficiency, and power constraints. Additionally, it must integrate seamlessly with a wide range of initiators and targets without increasing redesign effort or integration risk.

To address these requirements, Menta selected FlexNoC® interconnect IP from Arteris as the communication backbone of the MOSAICS Hub. FlexNoC is a silicon-proven, highly configurable NoC solution designed to optimize data movement in complex SoCs. By leveraging FlexNoC, Menta implemented a high-performance interconnect capable of supporting more than 30 initiators and targets operating at frequencies exceeding 500 MHz. This architecture enabled the team to balance scalability, performance, and silicon efficiency while accommodating diverse traffic profiles within a single coherent framework.

The configurability of FlexNoC proved particularly valuable. In a heterogeneous chiplet environment, predictable QoS, error detection and correction, and future functional safety capabilities are essential, especially for high-end HPC and AI applications in data centers. FlexNoC’s mature feature set provided these capabilities while integrating smoothly into Menta’s existing design framework. This reduced engineering complexity and minimized integration risk across the broader MOSAICS roadmap.

Another key benefit was accelerated development. The ease of configuration and integration allowed Menta’s engineering team to rapidly prototype, test, and validate the NoC implementation. Faster iteration cycles translated directly into reduced development timelines and improved confidence in meeting both performance and area targets. For a platform aimed at edge AI and other demanding embedded markets, this agility is critical.

The results demonstrate that a well-architected NoC foundation is more than a technical component, it is a strategic enabler. By standardizing on a scalable interconnect solution, Menta established a communication fabric capable of evolving alongside its chiplet ecosystem. This foundation supports current deployments while providing flexibility for next-generation platforms, new customer configurations, and emerging market requirements.

Bottom line: MOSAICS represents more than a single product initiative. It introduces a new model for designing and delivering custom silicon through modularity, ecosystem collaboration, and silicon-proven building blocks. The partnership between Menta and Arteris underscores the importance of strong technology alliances in achieving this vision. By combining programmable logic innovation with a scalable, power-efficient NoC architecture, the companies have laid the groundwork for a new generation of chiplet-based systems that are faster to develop, easier to integrate, and built for long-term scalability.

CONTACT ARTERIS IP

Also Read:

Arteris Smart NoC Automation: Accelerating AI-Ready SoC Design in the Era of Chiplets

WEBINAR: Why Network-on-Chip (NoC) Has Become the Cornerstone of AI-Optimized SoCs

The IO Hub: An Emerging Pattern for System Connectivity in Chiplet-Based Designs

April 27, 2026April 27, 2026

The Shift to System-Level AI Drives Next-Generation Silicon

The Shift to System-Level AI Drives Next-Generation Silicon
by Kalar Rajendiran on 04-27-2026 at 8:00 am
Categories: 3D IC, AI, Chiplet, FinFET, Foundries, TSMC

At its 2026 Technology Symposium, TSMC delivered a clear message: the AI era has entered a new phase. The primary constraint is no longer model capability, but the systems required to run those models at scale. Addressing this shift will demand significant advances in semiconductor technology, spanning compute, memory, interconnects, and power efficiency.

From Model Scaling to System Scaling

Over the past several years, AI progress was largely driven by scaling models. In other words, expanding parameter counts, improving training methods, and unlocking new reasoning capabilities. That paradigm is now evolving. In 2026, the bottleneck has shifted to system-level challenges such as compute throughput, memory bandwidth, interconnect efficiency, power delivery, and deployment scale. AI is becoming fundamentally a systems problem rather than a purely algorithmic one.

This transition is especially visible in the rise of enterprise AI agents. These systems are moving beyond narrow task assistance to orchestrating workflows, integrating enterprise data, and enabling more autonomous decision-making. As a result, they require high reliability, strong security, and sustained performance, all of which significantly increase infrastructure demands.

Explosive Growth in AI Compute Demand

AI compute demand continues to grow at an extraordinary pace, driven by both training and inference. On the training side, large language models have already driven roughly fivefold annual increases in compute requirements. And the shift toward multimodal AI which combines text, vision, audio, and real-world signals, is accelerating this trend further. Training demand alone is expected to increase by another order of magnitude.

Even more striking is the growth in inference. Token generation has increased more than 500 times between 2022 and 2025, and new techniques such as chain-of-thought reasoning are significantly increasing compute per query. The emergence of agent-based AI systems could multiply this demand again, while large-scale multimodal deployments may push total inference workloads toward million-fold growth. As a result, inference is rapidly becoming the dominant driver of compute infrastructure expansion.

AI Is Expanding Beyond the Cloud

AI is no longer confined to centralized cloud environments; it is rapidly expanding into edge and physical domains. At the edge, inference is increasingly being performed directly on devices such as PCs, smartphones, and wearables. This shift enables lower latency, improved privacy, and real-time responsiveness, and is driving the widespread adoption of dedicated AI accelerators like NPUs in consumer hardware.

At the same time, physical AI is bringing intelligence into the real world through robotics and embodied systems. These applications require tight integration of AI with sensing, actuation, and real-time control, all within strict power and reliability constraints. Together, these trends highlight the growing need for silicon solutions that can balance performance, efficiency, and compact form factors across a wide range of environments.

Data Center Scaling Enters Hyper-Growth

The rapid expansion of AI workloads is fundamentally reshaping data center infrastructure. Annual capacity additions, which previously grew at a steady rate of around 5 to 6 gigawatts, are now expected to reach 30 to 40 gigawatts per year. At the same time, overall data center investment growth has accelerated from roughly 10 percent annually before the rise of generative AI to more than 30 percent per year through the end of the decade.

This growth is not just about adding capacity; it is about delivering efficient, reliable, and scalable systems. Energy efficiency and total cost of ownership are becoming central concerns, making semiconductor-level improvements critical to the sustainability of AI infrastructure.

TSMC’s Technology Roadmap: Key Innovations

A14: Next-Generation Logic Platform (2028)

A14 represents TSMC’s next major step in logic technology, combining second-generation nanosheet transistors with NanoFlex Pro architecture and continued backend scaling innovations. Compared with the N2 node, A14 is expected to deliver a 10 to 15 percent speed improvement at the same power or a 25 to 30 percent power reduction at the same speed, along with approximately 1.2 times the logic density.

A central innovation in A14 is NanoFlex Pro, which enhances standard cell architecture to improve area efficiency and performance per watt. This is complemented by significant backend scaling advancements, including tighter metal pitch and reduced minimum metal area, enabling higher transistor density and improved overall efficiency. Together, these innovations demonstrate that progress at advanced nodes now depends on full-stack optimization rather than transistor scaling alone.

A13 and A12: Extending the Platform

Building on A14, TSMC is extending its roadmap with A13 and A12 technologies, both targeted for production around 2029. A13 further improves density and efficiency while maintaining backward compatibility with A14, enabling smoother design migration for customers. A12 introduces backside power delivery, a major innovation that improves power integrity and performance by separating power and signal routing. These developments reflect a broader shift toward holistic scaling, where power delivery and system-level considerations play an increasingly important role.

N2 Family: Nanosheet Era in Production

The N2 node marks TSMC’s transition from FinFET to nanosheet transistor architecture, delivering improved electrostatic control, reduced leakage, and lower operating voltage. These benefits translate into tangible efficiency gains in real-world applications.

The N2 family includes several variants designed to address different performance needs. The base N2 node entered production in 2025, followed by N2P in 2026 as an enhanced version. N2X, expected in 2027, targets high-performance applications with additional frequency gains, while N2U, planned for 2028, integrates NanoFlex Pro enhancements to further improve performance and power efficiency. This expanding family underscores the importance of offering flexible solutions tailored to diverse workloads.

Advanced Packaging and 3D Integration

As AI workloads continue to scale, advanced packaging technologies are becoming as critical as process nodes themselves. TSMC is advancing its chiplet and 3D integration capabilities with improvements such as second-generation CoWoS technology, which reduces interconnect resistance and enables higher bandwidth through finer I/O pitch.

These innovations allow for denser integration of compute and memory, improving performance and energy efficiency at the system level. In the AI era, packaging is no longer a secondary consideration but a key enabler of overall system performance.

N3: Today’s Workhorse Node

While future nodes attract significant attention, the N3 family remains the backbone of current high-performance computing. It is widely deployed across mobile devices, CPUs, AI accelerators, and networking applications, with multiple variants such as N3P and N3C supporting different use cases. Strong customer adoption and a robust pipeline of new designs highlight the continued importance of mature leading-edge nodes in delivering value across the ecosystem.

Summary

TSMC’s roadmap reflects a fundamental shift in the semiconductor industry. As AI continues to scale, the primary challenge is no longer developing more powerful models, but building the infrastructure required to support them efficiently. This requires innovation across the entire technology stack, from transistors and interconnects to packaging and system architecture.

In this new era, success will depend on the ability to deliver not just better chips, but better systems. The companies that can integrate performance, efficiency, and scalability at every level of the stack will define the future of AI—and increasingly, that future is being shaped at the silicon level.

Also Read:

TSMC Technology Symposium 2026 Overview

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TSMC Technology Symposium 2026: Advancing the Future of Semiconductor Innovation

April 27, 2026April 26, 2026

All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die

All in One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die
by Daniel Nenni on 04-27-2026 at 6:00 am
Categories: Ceva, Events, Foundries, IP, TSMC

The rapid evolution of wireless audio has placed unprecedented demands on system integration, power efficiency, and performance. Against this backdrop, the webinar “All-in-One Bluetooth Audio: A Complete Solution on a TSMC 12nm Single Die” offers a timely and technically rich exploration of how modern semiconductor design is meeting these challenges. For engineers, architects, and product leaders working in wireless audio, connectivity, or system-on-chip (SoC) design, this session provides both practical insights and a forward-looking perspective on integration trends shaping the industry.

REGISTER HERE

At the heart of the webinar is a detailed examination of a fully integrated Bluetooth audio solution implemented on a single die using advanced 12nm process technology from TSMC. Moving to a single-die architecture represents a significant shift from traditional multi-chip or module-based designs. By consolidating RF front-end, baseband processing, digital signal processing (DSP), memory, and power management into one silicon platform, designers can achieve tighter coupling between subsystems, reduced latency, and improved energy efficiency. This level of integration is particularly critical for applications such as true wireless earbuds, smart headsets, and embedded audio systems, where size, battery life, and performance must be optimized simultaneously.

One of the key reasons to attend this webinar is the opportunity to understand the architectural trade-offs involved in such high levels of integration. Designing on a 12nm node introduces both opportunities and constraints. While the process enables higher transistor density and lower power consumption, it also requires careful attention to analog/RF performance, noise isolation, and thermal considerations. The session is expected to walk through these challenges, offering insights into how designers balance digital scaling benefits with the sensitivities of RF and mixed-signal blocks.

Another compelling aspect of the webinar is its focus on system-level optimization. Bluetooth audio is no longer just about connectivity; it is about delivering high-quality, low-latency audio experiences under strict power budgets. Attendees will gain visibility into how DSP pipelines are structured for efficient audio processing, how coexistence mechanisms are implemented to handle interference, and how power management strategies are designed to extend battery life without compromising performance. These are not abstract concepts but practical considerations that directly impact product success in competitive consumer markets.

The webinar also promises to cover silicon validation and real-world performance metrics. This is particularly valuable because it bridges the gap between theoretical design and deployed systems. Understanding how a single-die solution performs in terms of power consumption, latency, RF robustness, and audio fidelity provides attendees with a benchmark for their own designs. It also offers a clearer picture of what is achievable with current process technology and integration techniques.

Beyond the technical depth, the webinar is relevant because it reflects a broader industry trend toward consolidation and platformization. As wireless audio devices become more ubiquitous, the ability to deliver complete, scalable solutions on a single chip is becoming a competitive differentiator. Engineers who understand these trends will be better positioned to design future-proof systems and make informed decisions about architecture, process nodes, and integration strategies.

Finally, attending this webinar is an efficient way to stay current in a fast-moving field. Instead of piecing together information from disparate sources, participants can gain a cohesive understanding of end-to-end Bluetooth audio system design in a single session. Whether you are an RF engineer looking to understand digital integration impacts, a DSP developer interested in system constraints, or a product engineer evaluating design trade-offs, the content is directly applicable to real-world challenges.

REGISTER HERE

Bottom line: This webinar is more than a product overview; it is a deep technical dive into the future of integrated wireless audio systems. By attending, you gain not only knowledge of a specific implementation but also a framework for thinking about integration, efficiency, and performance in next-generation designs.

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April 26, 2026May 14, 2026

Closing the Reality Gap: A New Architecture for 1.8-Tb/s Chiplet Governance

Closing the Reality Gap: A New Architecture for 1.8-Tb/s Chiplet Governance
by Moh Kolb on 04-26-2026 at 4:00 pm
Categories: 3D IC, AI, Chiplet

Dr. Moh Kolbehdari is a Senior Lead Architect at Socionext, where he specializes in the industrialization of high-performance AI chiplets and 1.8-Tb/s interconnects. With over two decades of experience in SI/PI, electromagnetic field theory, and system-level architecture, he has been a pivotal force in bridging the gap between cutting-edge silicon design and high-volume manufacturing (HVM).

Dr. Moh is the creator of the SEGA™ (Systematic Engineering Governance Architecture) framework, a methodology designed to solve the “Crisis of Complexity” in heterogeneous integration. His work focuses on transforming the package into an Active Control Plane, utilizing field-confined EM Corridors and state-aware causality to ensure deterministic yield at 2nm and beyond. He is a frequent contributor to industry-standard committees and is recognized for his “Physics-First” approach to solving the semiconductor industry’s most challenging entropy walls.

The Entropy Wall at 2nm

The semiconductor industry is hitting a “Traceability Wall”. As we push toward 1.8-Tb/s interconnects and massive 2.5D/3D AI chiplet systems, the traditional design-then-verify flow is breaking down. We can no longer afford to treat the package as a passive “container” for silicon; at these speeds and densities, the package must be viewed as the Active Control Plane.

The “Reality Gap”—the delta between golden-state simulations and high-volume manufacturing (HVM) yield—is widening. Standard EDA tools excel at predicting nominal performance, but they often fail to account for the stochastic nature of the OSAT environment. To close this gap, we must move beyond “Nominal Design” and embrace Governed Convergence.

Introducing SEGA™: Systematic Engineering Governance Architecture

To address this complexity, I have developed SEGA™. It is a governance layer that sits above the standard EDA ecosystem, enforcing a unified “Readiness Loop” between simulation, lab measurement, and OSAT metrology. SEGA™ ensures that every picosecond of signal performance is backed by admissible evidence from the assembly floor.

Figure 1: The Governed Convergence Pyramid

As shown in the pyramid, SEGA™ establishes a three-tier hierarchy for system success:

The Foundation: Packaging as the Control Plane. This tier treats the substrate as a dynamic hub that governs the convergence of SI, PI, Power, and Thermal stresses. By managing these variables in a unified hub, we prevent late-stage design “blow-ups” that typically occur when these domains are siloed.
The Middle Tier: EM Corridor Architectures. Traditional PCB and package traces rely on “dirt road” routing that becomes chaotic at sub-THz frequencies. We implement field-confined physical pathways—EM Corridors—that ensure electromagnetic field continuity across the BGA transition zone.
The Apex: Evidence Gating. This is the final filter. Only data that passes the State-Aware Causality filter is allowed to proceed to tape-out. This means every simulation result must be “certified” against known physical manufacturing modes.

Confronting the OSAT Reality

The biggest threat to modern chiplet systems isn’t just signal decay; it is the physical variables of the assembly floor. Substrate warpage, solder-bump collapse, and thermal drift create an OSAT Reality that golden simulations often ignore. When a design moves from the lab to HVM, these physical stresses introduce “entropy” that degrades performance.

Figure 2: Governed Convergence – Closing the Reality Gap

By using State-Aware Causality, we link performance decay directly to specific deformation modes. For example, if a 1.8-Tb/s eye diagram closes during stress testing, the SEGA™ framework doesn’t just report a failure; it tells us exactly which manufacturing variable—such as a $30\mu$m substrate warp or lateral misalignment—caused the shift. This transforms “failure analysis” from a reactive guessing game into deterministic governance.

Deep-Dive Case Study: AI Chiplet PDN Impedance Flattening

The power of systematic governance is most visible in the Power Delivery Network (PDN). In high-performance AI systems, suppressing mid-frequency die resonance is critical for maintaining system stability under heavy workloads.

Figure 3: SEGA™ Case Study – PDN Impedance Flattening

Our case study on 2.5D AI Chiplet Power Architecture (CPA) demonstrates how implementing a Localized VRM (PCA) governs the PDN. Traditionally, VRMs placed on the PCB struggle to manage the resonance peaks occurring at the interposer and die levels. By aligning the VRM response directly with the in-package parasitics discovered via our state-mapping, we successfully suppressed the die resonance peak (occurring between 170–280 MHz) to remain consistently below the $0.09 \Omega$ Target.

This level of flattening ensures that the silicon sees a stable voltage environment regardless of the switching activity of adjacent chiplets. This is a result that “golden” simulations can suggest, but only a governed architecture like SEGA™ can guarantee in a mass-production environment.

The Path Forward: Industrializing the Interconnect

The move toward 2nm and beyond is not just a lithography challenge; it is a governance challenge. As we move toward 10 Tb/s UCIe targets and increasingly complex heterogeneous systems, the architects who can bridge the gap between simulation and the factory floor will define the future.

The next era of advanced packaging will be won by governed convergence, not by activity alone. By implementing SEGA™, we move the industry toward a future where “first-time-right” isn’t a goal—it is a deterministic outcome of the architecture itself.

Also Read:

Alchip’s Leadership in ASIC Innovation: Advancing Toward 2nm Semiconductor Technology

Synopsys Advances Hardware Assisted Verification for the AI Era

Scaling Multi-Die Connectivity: Automated Routing for High-Speed Interfaces