SemiWiki – Page 10 – The Open Forum for Semiconductor Professionals

April 26, 2026April 27, 2026

SemiWiki Q&A with Julie Rogers, Executive Director, ESD Alliance

The Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, an international association of companies providing goods and services throughout the semiconductor design ecosystem, is a forum to address technical, marketing, economic and legislative issues affecting the entire industry. It acts as the central voice to communicate and promote the value of the semiconductor design industry as a vital component of the global electronics industry.

Tell us a little bit about yourself and your path to your new role as Executive Director of the Electronic System Design (ESD) Alliance.

I’m excited for what lies ahead for the ESD Alliance, also known as ESDA, and the design industry. My career has been shaped by curiosity about how technology evolves and reaches the market. Early in my career, I worked with a large hospital system writing grants and securing education funding from medical device companies, which sparked my interest in innovation and ultimately drew me to Silicon Valley.

More than a decade ago, while running my own marketing firm, I added the ESD Alliance—then EDAC—to my client list. When ESDA later merged into SEMI, I became Director of Marketing for SEMI Americas while continuing my work with ESDA, giving me a front-row seat to the evolution of the design ecosystem.

What are your responsibilities and priorities in your new role as Executive Director?

My focus is to support and advance our member companies and strengthen the role of the ESDA within the broader semiconductor ecosystem. Key priorities include driving executive engagement, expanding thought-leadership platforms, global outreach and ensuring our programs deliver value.

A key priority is inspiring leadership participation, bringing executives together to collaborate, share insights, and address challenges that impact the entire design community. Our events appeal to everyone working in and with the design industry bringing topics and companies together, which helps strengthen established and emerging companies as the industry navigates rapid change.

What do you see as the biggest opportunity for the ESD Alliance and the EDA and IP community in 2026?

A major opportunity is helping members navigate complexity, from export regulations to AI-driven innovation, while continuing to support emerging companies through visibility and strategic connections. Design is increasingly central to all semiconductor end products and services, and ESDA plays a critical role in communicating this value.

I see tremendous opportunity to support emerging companies. These innovators are driving new ideas and technologies, and we can help them with strategy, visibility, and the right networking connections to accelerate their growth. I really enjoy this part when it all comes together to up level the design ecosystem.

We have an expanded resource working with our regional offices on a global level as well. Pre-pandemic we had initial meetings worldwide and we plan to enhance visibility of ESDA and increase the design community momentum on a global scale.

How is the ESD Alliance working to address these opportunities?

We’re expanding both the scope and depth of our programs to address the most urgent member needs.

The ESD Alliance 2026 Executive Outlook, scheduled for Wednesday, June 10, at Cadence in San Jose, brings together senior leaders to discuss critical trends focusing on “How will Agentic AI Change Chip Design and Verification.” Panelists will survey the excitement surrounding the innovation in chip design and verification, collaboration between traditional EDA and agentic AI startups and broader implications for technological advancements.

The event will be held at Cadence, 2655 Seely Avenue in San Jose beginning at 5:30 p.m. with networking, dinner and beverages. The panel will follow at 6:30 p.m. Tickets for the event are free for SEMI/ESDA members and $40 per person for non-members. Registration is open.

We’re also continuing to grow our advocacy programs with another webinar “Navigating Export Controls in EDA” Thursday, June 11“Gen-AI for Chip Design and Security: A Look into the Future” will be held Thursday, August 27. Additional events and a webinar on workforce development are also in the works.

SEMICON West 2025 included a design program that was well attended. Will that continue?

Absolutely. The response was incredibly strong, so in 2026 we’re expanding the design program to a full day of content. We’re actively looking for speakers and fresh perspectives, and we want this to be a must-attend forum for the design community. We will be featuring a design keynote as well. It’s coming up October 13-15 at the Moscone Center in San Francisco.

How do companies in the EDA and IP space typically engage with the ESD Alliance?

Engagement happens at many levels. Executives participate in events such as the ESDA/CEDA Phil Kaufman Award Dinner and the ESDA Executive Outlook. Companies also engage their design engineers and other key staff through participation in our webinars, advocacy initiatives, education, networking events, workforce development efforts through our SEMI Foundation, speaking opportunities and working groups. We have groups focused on key industry challenges such as platform interoperability, license management, and anti-piracy and we produce a highly regarded quarterly market report, Electronic Design Market Data (EDMD). Details can be found on the ESDA website.

Or SemiWiki readers can contact me directly:

jrogers@semi.org
(916) 798-9919
Julierogers.200Skype
WeChat ID: JulieARogers

Also Read:

Podcast EP333: A Look at the Broad, Worldwide Impact SEMI Has on the Semiconductor Industry with Ajit Manocha

The Name Changes but the Vision Remains the Same – ESD Alliance Through the Years

Podcast EP340: A Review of the Q4 2025 Electronic Design Market Data Report with Wally Rhines

April 25, 2026April 28, 2026

CEO Interview with Xianxin Guo of Lumai

CEO Interview with Xianxin Guo of Lumai
by Daniel Nenni on 04-25-2026 at 2:00 pm
Categories: CEO Interviews

Xianxin is the CEO and Co-Founder of Lumai, an Oxford University spin-out pioneering disruptive optical computing technologies for Al and data center acceleration. He brings over 15 years of experience in physics and engineering, and was previously an RCE 1851 Research Fellow, a prestigious fellowship whose past awardees include eight Nobel Laureates.

Tell us about your company.

Lumai is an optical compute company changing how AI compute is delivered at scale. Traditional silicon-only approaches are hitting fundamental limits in power efficiency, cost, and scalability. Our team brings together expertise across optics and AI systems with a shared belief: that new AI infrastructure requires a new approach, and that approach will use optical compute.

The technology is based on many years of research at the University of Oxford. At Lumai, we are building optical computing technology designed specifically for AI workloads. By leveraging light instead of electrons for key computational operations, we dramatically improve performance-per-watt and unlock a more sustainable path forward for large-scale AI deployment.

What problems are you solving?

AI has hit a power wall. Due to the limitations of silicon scaling, it is increasingly difficult to deliver a step-change in token generation within the fixed power constraints of a data center. A 1GW data center is limited to 1GW. Yet the goal of AI companies is to generate the maximum number of tokens – more tokens mean more intelligence and more revenue.

The core issue we address is compute inefficiency: data centers need to generate more tokens per Watt. Lumai tackles this through a hybrid optical and electronic approach, performing dense linear algebra (i.e. tensor operations) in light, alongside a standard digital chip where the software runs.

This hybrid design means the processor exposes a standard interface to the software stack and system interfaces, while offloading matrix computations to a far more efficient medium and dramatically reducing energy consumption.

In short, we are breaking through the bottlenecks slowing down AI systems.

What application areas are your strongest?

Our technology is particularly well suited to high-throughput AI inference workloads in data centers. This includes compute-bound applications such as large language models, recommendation systems, and video processing.

Lumai’s processor can be used as a prefill processor in a disaggregated compute architecture, alongside (for example) a GPU used for decode. It is especially effective in applications with long input contexts and large token volumes (e.g. KV cache generation heavy workloads).

What keeps your customers up at night?

Two things consistently come up: cost and scalability. AI is becoming central to business strategy, but the infrastructure required to support it is increasingly expensive and power-constrained.

Customers are concerned about how to scale their AI capabilities without hitting data center power limits or seeing costs spiral. At the same time, they want to achieve this without fundamentally changing their software workflows or models.

Ultimately, they’re asking: how do we continue advancing AI performance without running into a wall on cost and power?

What does the competitive landscape look like and how do you differentiate?

The landscape is evolving quickly, with innovation across GPUs, ASICs, and other AI accelerators. While these approaches deliver incremental improvements, they still rely on electronic architectures.

Lumai differentiates by taking a fundamentally different approach: optical compute. This allows us to bypass many of the inherent limitations of electronic-only systems, where increasing performance drives both higher power consumption and higher total cost of ownership (TCO).

Our focus isn’t just on building a faster processor, it is about redefining how compute is performed for AI workloads in the most efficient way. That enables step-function improvements rather than incremental gains.

We are building an architecture designed to scale generation after generation.

What new features/technology are you working on?

We are continuing to advance our optical compute platform, with a strong focus on integration and scalability. This includes developing the supporting electronics and software stack required for seamless deployment.

We have already proven the core technology; our current focus is on supporting trials, further increasing performance, and ensuring our platform integrates easily into existing AI infrastructure. Compatibility with current frameworks and workflows is key so customers can adopt it without major disruption.

As we move forward, you will see continued progress toward production systems that deliver meaningful performance and efficiency gains at scale.

How do customers normally engage with your company?

Engagement typically begins with collaborative discussions around specific AI workloads and infrastructure challenges. From there, we work closely with customers to evaluate where optical compute can deliver the most value.

We take a partnership-driven approach: whether through early access programs, joint development efforts, or pilot deployments. Close collaboration is key to ensuring successful integration and real-world impact.

Our goal is to meet customers where they are, help them break through the power wall, and transition to a more efficient, scalable AI compute platform that will serve them not only today but well into the future.

Also Read:

CEO Interview with Johan Wadenholt Vrethem of Voxo

CEO Interview with Dr. Hardik Kabaria of Vinci

CEO Interview with Steve Kim of Chips&Media

Podcast EP343: How Ethernet is Enabling Advances in AI with Dr. Mohan Kalkunte

Podcast EP343: How Ethernet is Enabling Advances in AI with Dr. Mohan Kalkunte
by Daniel Nenni on 04-24-2026 at 10:00 am

Daniel is joined by Dr. Mohan Kalkunte, Vice President of Architecture & Technology in the Core Switch Products group at Broadcom, where he leads architecture for Ethernet switching and NIC products across data center, enterprise, and service provider markets. With over 35 years of industry experience his previous stints include AT&T Bell Labs, AMD and Nortel Networks. He has over 150 patents, was named a Broadcom Fellow in 2009, elected IEEE Fellow in 2013, and elected in 2025 as NAE member for his contributions to Ethernet Switching.

Dan explores AI networking architectures with Mohan who explains why AI networking is different. Mohan provides an excellent overview of how AI demands have impacted network architecture. In this very informative discussion, items such as Ultra Ethernet, the Ultra Ethernet Consortium (UEC) and other open standards are discussed. The requirements for scale-up and scale-out are discussed. Mohan explains that the overall goal is to make Ethernet viable across the entire AI network stack. Mohan also discusses how the pace of network innovation is accelerating to fuel next-generation AI technology.

Innovations at Broadcom that are advancing AI networking are reviewed. Mohan also describes how all the work underway will come together to enable future generations of AI technology.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

April 24, 2026April 24, 2026

SemiWiki Acquires IPnest!

SemiWiki Acquires IPnest!
by Daniel Nenni on 04-24-2026 at 8:00 am
Categories: IPnest, Semiconductor Services

After more than 15 years of collaboration with Dr. Eric Esteve and IPnest, SemiWiki has acquired the famed IP reports with Eric Esteve staying on through 2026 to ease the transition. Not only will SemiWiki provide the industry standard Interface IP and Design IP reports, SemiWiki will be expanding the depth and breadth of the coverage. Semiconductor IP has always been a critical enabler of modern semiconductor design and a great source of traffic for SemiWiki.com so this is a 1+1=3 type of transaction.

When I started SemiWik in 2011 I recruited the top two EDA bloggers; Dr. Paul Mc Lellan and Daniel Payne. Paul has since retired and Daniel Payne is still writing for SemiWiki. I covered the foundries and I recruited Eric Esteve to cover Semiconductor IP. Eric was not a blogger when we met but he turned out to be one of the top bloggers on SemiWiki. Eric wrote 427 IP related blogs garnering more than 6 million views and for this I am very grateful.

Eric Esteve:

After starting on CMOS 2 micron in the 80’s by ASIC design I enjoyed multiple projects like supercomputer and Airbus engine motor control (CFM56), later used on Rafale Aircraft and many others to end my technical career as program manager for one of the first System-on-Chip (SoC) in 1995. We didn’t talk about IP, but we were using it. Later I was ASIC marketing manager in charge of North-American market and visited multiple customers, from Orlando to Salt Lake City, Chicago to Atlanta, learning a lot more about human contact. Finally, since 2005, my focus is IP, working for PLDA then Snowbush before creating IPnest in 2009 and developing a customer base of more than 20 customers: Top 3 EDA and many IP vendors (Alphawave, Rambus, CEVA, Arteris, Silicon Creations…) but also TSMC, Intel and most of the hyperscalars (Amazon, Google, Facebook). Most of them are loyal customers year after year for 17 years!

Just before creating IPnest in 2009, I worked for Snowbush in Toronto were I had to create a 5 year business plan and I learned two key lessons: The first was how important it was to manage SerDes design if you have to support interconnects protocol. The second was that the industry needed a source of intelligence about the interface protocol market, because I had to invent it in 2008 to build Snowbush’s business plan. IPnest’s first Interface IP report built in 2009 and sold to my first customers, Synopsys and Cadence, was certainly not perfect, but the quality has constantly improved, thanks to my customers challenging me and providing a feedback loop.

Just a side comment, in 2009, the Interface IP market was valued at $250 million, last year (2025) it was $2.5 billion. The interconnect IP market is booming since 2010, and will continue if you look at AI. You can improve compute by adding GPU or redesign it, but you have to use more powerful interconnect when developing new system and it’s possible to do it as protocols have been created to support it. PCIe 1.0 speed was 2.5 GT/s in 2005, today if you select PCI 7.0, you enjoy 128 GT/s. Clearly, the future of interconnect IP protocols will be essential for building more powerful AI systems!

The Design IP report is simply a tool needed by the IP industry, it’s a market share ranking, by IP category helping IP customers to select their provider and IP vendors to monitor their progress on a fast growing market. Easy to describe, it’s a little bit more complex to build as many players prefer to keep secret their detailed results. Experience is the key word here.

It’s almost the end of a 43-year journey. Deciding to go into a business that nobody knew in 1983 was challenging, it was also a way to be creative and to learn along the way. A special thanks to SemiWiki founder Daniel Nenni who offered me to blog when I was starting IPnest. It helped to pay the bills and, more importantly, to network and be recognized as an IP expert on such a large platform. So I am more than happy to transfer IPnest to SemiWiki. I am confident and trust SemiWiki to be the right place to develop IPnest reports to an even higher level!

SemiWiki:

The entire SemiWiki team wishes Eric a happy retirement and we look forward to continuing his excellence in IP reporting.

Also Read:

AI Booming is Fueling Interface IP 23.5% YoY Growth

Design IP Market Increased by All-time-high: 20% in 2024!

AI Booming is Fueling Interface IP 17% YoY Growth

Semi Market Decreased by 8% in 2023… When Design IP Sales Grew by 6%!

April 24, 2026April 24, 2026

Elon Musk Needs to Put His Fab Money Where his Mouth is!

Elon Musk Needs to Put His Fab Money Where his Mouth is!
by Daniel Nenni on 04-24-2026 at 6:00 am
Categories: Foundries, Intel Foundry
1 Comment

Terafab: Elon Musk’s Vertically Integrated AI Chip Manufacturing Initiative with Intel

To me this is going to be one of the bigger Chicken Little moments in the history of semiconductors. Mostly because we are now a click driven society and the media is plagued by so called influencers that live and die by clicks. In my 40+ years as a semiconductor professional I have witnessed many of these Chicken Little moments with semiconductor outsiders saying that we cannot scale semiconductors for one reason or another. A common headline starting in the early 2000s was that “Moore’s Law is Dead”, right? Yet here we are making semiconductors that were deemed impossible to make many times over.

This time however the richest man in the world says that we will not have enough 2nm capacity to satisfy the world’s demands due to the AI surge and the coming onslaught of AI driven products. Please note that Elon Musk did not consult the top semiconductor manufacturing company in the world (TSMC) nor did he consult the semiconductor legend that is Intel UNTIL AFTER HE SAID THIS. I’m sure there is a method to his madness and I’m also sure that the semiconductor industry will respond appropriately, we always do.

The picture above is encouraging. If anyone can turn Elon Musk around it is Lip-Bu Tan. Remember when he turned Donald Trump around?

Donald Trump Truth Social (Aug 7, 2025)
“The CEO of INTEL is highly CONFLICTED and must resign, immediately. There is no other solution to this problem. Thank you for your attention to this problem!”

This was on Thursday. Lip-Bu met with Donald Trump the following Monday at the White House which resulted in this:

“I met with Mr. Lip-Bu Tan, the CEO of INTEL. The meeting was a very interesting one. His success and rise is an amazing story. We discussed many things, including the future of Intel and the importance of U.S. chip manufacturing. We will see what happens, but it was an honor to meet him.”

Not only did Lip-Bu Tan turn POTUS around, he got an incredible investment and backing from the US Government. Talk about taking lemons and making a lemon meringue pie!

At the TSMC Technical Symposium this week TSMC made it clear that there will be no issue with TSMC N2 (2nm) availability. In fact, TSMC N2 is ahead of TSMC N3 on the yield learning curve. Remember, TSMC N2 went into HVM in Q4 of 2025 so this is a fact not a forecast.

I remember when Apple turned to TSMC to manufacture the iProduct chips back at 20nm (iPhone 6). Semiconductor outsiders did not think TSMC could deal with Apple’s volume, or Apple would ruin TSMC as they did other partners, or TSMC could not handle Apple’s accelerated schedules. Just about every year the media claims Apple will consume all of TSMC NX so there would not be wafers left for anyone else. They now say that about Nvidia but of course that is also not true. Wafer agreements are legally binding contracts and are the life blood of contract semiconductor manufacturing.

The fact of the matter is that Apple and TSMC have a wafer agreement that spells out how many wafers Apple will get on a specific process node several years in advance so TSMC can build fabs for Apple. Every single TSMC customer has a wafer agreement, that is how we do business. In Apple’s case TSMC made processes tuned just for Apple and Apple had exclusive rights to it. Apple and TSMC would collaborate closely on process development and the process release would be timed for the Apple iPhone launches in the fall. This has been going on for 15 years and today the Apple iPhone is the most successful in the history of smartphones and the A Series SoC inside them is nothing short of miraculous.

Someone needed to explain to Elon Musk how semiconductor design and manufacturing really works and who better than Lip-Bu Tan?

Elon Musk needs to know that it takes longer for companies to design complex AI chips on leading edge processes than it takes TSMC and Intel to build the fabs that will manufacture them. Elon also needs to know that he will need to collaborate very closely with the semiconductor supply chain and make some very big investments to make sure his companies have the chips they need to be successful.

Lip-Bu Tan will explain this to him of course and Elon will tell the world so this is a win-win Chicken Little situation if I have ever seen one.

Intel is the big winner here of course and we can all thank Lip-Bu for that. As I have said many times before, do not bet against Lip-Bu Tan!

Tesla CEO Elon Musk said on Wednesday the EV maker plans to use Intel’s next-generation 14A manufacturing process to make chips at its Terafab project, an advanced AI chip complex Musk has ‌envisioned in Austin.

TSMC and the semiconductor industry as a whole are both winners here as Intel will become a serious foundry competitor and that will push semiconductor innovation and supply chain strength to an even higher level which is for the greater good for all.

“We either build the Terafab or we don’t have the chips,” Musk had said during a presentation in Austin in March, adding that current global chip production would meet only a small fraction of his companies’ future needs.

The only loser that I can see here is Samsung Foundry. Not long after Samsung and Tesla signed an 8 year $16.5B 2nm wafer agreement Elon Musk announces to the world that not enough 2nm chips can be made? Ouch!

Bottom line: Elon Musk is a disrupter and I am glad to have him inside the semiconductor industry. The first thing I said in the SemiWiki forum after the Terafab announcement was made is that the only chance of success is for Elon to work with Lip-Bu Tan and Intel. So there you have it. I am still waiting for the financial details but I would bet that Elon Musk will in fact be putting his money where his mouth is, absolutely.

Also Read:

Is Intel About to Take Flight?

Disaggregating LLM Inference: Inside the SambaNova Intel Heterogeneous Compute Blueprint

Who’s Buying America’s Foundry Future?

April 23, 2026April 23, 2026

Two Paths for AI in Semiconductor Manufacturing: Platform Integration vs. Point Solutions

Two Paths for AI in Semiconductor Manufacturing: Platform Integration vs. Point Solutions
by Kalar Rajendiran on 04-23-2026 at 10:00 am
Categories: AI, Analytics, China, EDA, Foundries, PDF Solutions

Semiconductor manufacturing has become one of the most data-intensive industrial environments in the world, and AI is rapidly becoming central to how fabs operate and optimize. Yet, rather than converging on a single model for AI adoption, the industry is evolving along two distinct paths. One centered on platform-scale integration and the other on fast, point-level deployment. The two approaches reflect differences in market structure, customer expectations, vendor ecosystems, and cultural approaches to manufacturing. This article explores these two models not as competing answers, but as context-driven responses to different operating environments, with the long-term outcome still open.

Global Semiconductor AI Context

The increasing complexity of semiconductor devices and manufacturing processes has led to an explosion in data generation, often reaching millions of parameters per device and petabyte-scale datasets per fab. At the same time, the industry must accelerate new product introduction while maintaining yield and stability in mass production. These pressures have made AI a necessary layer in semiconductor manufacturing, enabling scalable analysis, automation of decision-making, and interpretation of complex process interactions.

Modern AI systems in this space are typically built on a combination of scalable analytics engines, structured workflows, and domain-specific knowledge, often enhanced by natural language interfaces. While these foundational elements are broadly consistent across regions, how they are packaged, deployed, and monetized varies significantly.

Reference Architecture (Platform AI as a Model)

One way to understand these differences is through a reference architecture that represents a platform-based approach to semiconductor manufacturing AI.

At its core is a scalable analytics engine designed to process extremely large and complex datasets using parallel computation. This enables real-time or near-real-time analysis across vast manufacturing data environments.

Above this sits a workflow layer that defines how analytics are structured and executed. In this model, workflows act as a system-level language, capturing logic, enabling reuse, and providing traceability. They also function as a form of long-term system memory, embedding best practices and analytical patterns.

A natural language interface layer allows engineers to interact with the system more intuitively, translating human intent into structured workflows. This improves accessibility but relies on the underlying system for execution.

Finally, a semiconductor domain knowledge layer provides the contextual intelligence needed to interpret data correctly. This layer encodes device physics, process interactions, and historical expertise, ensuring that AI outputs are grounded in real manufacturing behavior rather than purely statistical patterns.

This architecture reflects a platform-oriented philosophy, where AI is treated as infrastructure rather than a collection of isolated tools. At its latest Users Conference PDF Solutions introduced the overall architecture of its platform and AI strategy, and demonstrated how LLMs integrated with this platform can be used to answer complex semiconductor manufacturing analytics questions using natural language.

Core Market Divergence: Platform vs. Point Solutions

In North America and Europe, semiconductor AI has largely evolved around platform-based deployment models. AI systems are designed as foundational layers that integrate with existing manufacturing systems and support multiple use cases over time. This approach emphasizes consistency, scalability, and long-term value creation. Because these environments often involve complex legacy systems, platforms serve as a unifying layer that can bridge data and processes across the fab. Deployment tends to be methodical, with significant emphasis on validation and integration.

In China, a different pattern has emerged. AI adoption is often driven by forward-deployed, point-specific solutions that address immediate manufacturing challenges. Many vendors are smaller and highly specialized and work closely with fabs and equipment providers to develop targeted applications for specific problems such as tool matching, chamber variation, or yield excursions. These solutions are deployed quickly, refined through direct feedback, and expanded incrementally to other problem areas. Rather than building a unified platform upfront, the system evolves through a series of practical implementations.

Structural Drivers Behind the Divergence

These two approaches are shaped by a combination of structural and cultural factors. In China, the prevalence of smaller AI vendors creates a strong need for rapid monetization, which favors solutions that can be developed and deployed quickly with clear, measurable outcomes. The manufacturing environment also places a high value on immediate operational improvements, reinforcing a preference for short deployment cycles and tangible results.

In North America and Europe, semiconductor companies often operate within more mature ecosystems that include extensive legacy infrastructure. This creates a need for integration and consistency across systems, making platform-based approaches more attractive. There is also a greater tolerance for longer deployment timelines when the expected outcome is system-wide optimization and long-term efficiency gains.

These differences do not reflect a gap in capability, but rather different priorities shaped by market conditions and organizational context.

Trade-offs Between the Two Approaches

Each model offers distinct advantages and challenges. Platform-based approaches provide a structured foundation that can support multiple use cases, enable cross-system optimization, and reduce redundancy over time. They are particularly well-suited for large-scale environments where integration and consistency are critical. However, they can require significant upfront investment and may take longer to deliver visible results.

Point-solution approaches, by contrast, are highly effective at delivering rapid impact. By focusing on specific problems, they can be deployed quickly and aligned closely with operational needs. This makes them well-suited for environments where speed and measurable outcomes are prioritized. At the same time, the accumulation of independent solutions can introduce fragmentation, making it more difficult to achieve system-wide optimization or maintain consistency across processes.

Importantly, these trade-offs are not absolute; they reflect different ways of balancing speed, scale, and integration.

Strategic Hybrid Possibility

Rather than converging entirely toward one model, there is growing recognition that elements of both approaches may coexist. A platform layer can provide structure, scalability, and domain intelligence, while localized solutions can continue to address specific operational challenges quickly and effectively. In such a model, platforms may evolve to incorporate or orchestrate point solutions, creating a layered system that combines integration with flexibility.

Whether and how this hybrid model develops will depend on how vendors and customers navigate the balance between standardization and customization, as well as how ecosystems mature over time.

Summary

The current landscape of semiconductor manufacturing AI reflects not a single direction of travel, but a divergence shaped by real-world constraints and priorities. Platform-centric and point-solution approaches each represent viable responses to different environments, and both are likely to continue evolving. Over time, one model may prove more scalable or sustainable, or a hybrid approach may emerge as dominant. For now, understanding the underlying drivers of each model is more important than determining a definitive long term winner.

Learn more at PDF Solutions.

Also Read:

WEBINAR: Beyond Moore’s Law and The Future of Semiconductor Manufacturing Intelligence

Operationalizing Secure Semiconductor Collaboration: Safely, Globally, and at Scale

Why PDF Solutions Is Positioning Itself at the Center of the Semiconductor Ecosystem

April 23, 2026April 23, 2026

Carbon in the Age of AI Chips: What the Semiconductor Industry Needs to Know This Earth Day

Carbon in the Age of AI Chips: What the Semiconductor Industry Needs to Know This Earth Day
by Admin on 04-23-2026 at 6:00 am
Categories: Semiconductor Services, TechInsights, TSMC

Stephen Russell: Senior Technical Fellow, TechInsights

Every April, Earth Day prompts a flurry of corporate sustainability pledges and green-tinted press releases. But for the semiconductor industry in 2026, the conversation has moved well past pledges. Carbon accountability is now a procurement requirement, a regulatory expectation, and increasingly a design constraint. This Earth Day, TechInsights is releasing a new sustainability report, Carbon in the Age of AI Chips. Authored by TechInsights Senior Technical Fellow Stephen Russell and Senior Sustainability Analyst Lara Chamness, the report examines where semiconductor emissions are actually coming from, why AI is accelerating the problem faster than most reporting methods can track, and what engineering, procurement, and sustainability teams can do about it right now.

Here’s a preview of what’s inside:

The Scale of the Problem Is Getting Harder to Ignore

Start with the headline numbers. Fabrication emissions are projected to reach 186 million metric tons of CO₂e in 2026, a record high, rising to approximately 247 million metric tons by 2030. Leading-edge technologies below 4nm will account for 26% of total emissions this year, climbing to 42% by 2030. Those are not abstract figures. They represent real consequences of real decisions: which fab to use, which memory configuration to specify, which supplier to source from.

What makes 2026 feel genuinely different from prior years is the convergence of three forces pushing carbon upstream into product decisions. Advanced manufacturing keeps getting more energy- and resource-intensive, especially at leading-edge logic and high-layer 3D NAND. AI demand is driving unprecedented silicon and memory intensity per system, not just more units but fundamentally heavier systems. And procurement teams are being asked, with increasing urgency, to defend supplier choices with traceable carbon logic rather than slide-deck narratives.

Manufacturing Carbon Is a Strategic Variable, Not a Fixed Cost

One of the report’s central arguments is that manufacturing carbon should not be treated as a black box or a rounding error. It is a strategic variable, and it responds to specific decisions.

The report’s Sustainability Matrix maps carbon hotspots across device types and toolsets. For advanced logic nodes, Scope 2 emissions driven by electricity are concentrated in lithography. For 3D NAND, dry etch can account for nearly half of total manufacturing emissions, driven by high-power plasma processes and high global warming potential gases. Some of those gases carry a 100-year GWP of around 25,000 times that of CO₂.

Perhaps the most striking case study involves backside power delivery (BSPD), a major scaling innovation that many assume carries a straightforward carbon penalty due to added process complexity. The reality is more nuanced. In an illustrative comparison of Intel 18A manufactured in the United States versus TSMC N2 manufactured in Taiwan, the Intel process results in lower manufacturing CO₂e per die. Not because it is simpler, but because the U.S. grid is cleaner. The electricity mix where a chip is fabricated can outweigh the complexity of the manufacturing process itself. That is a finding with immediate implications for anyone making sourcing or fab-selection decisions.

AI Hardware Is Scaling Emissions Faster Than Shipments

The report’s treatment of AI accelerators is where the numbers become genuinely striking. TechInsights’ Global AI GPU Manufacturing Carbon Emissions Forecast shows that by 2030, manufacturing emissions from AI GPU production are projected to rise more than twelvefold, from approximately 1.8 million metric tons CO₂e in 2024 to 21.6 million metric tons CO₂e. AI GPU manufacturing is expected to account for roughly 8.7% of total semiconductor die fabrication emissions by 2030. The average accelerator is expected to exceed one metric ton of CO₂e per unit by 2029.

The driver is not primarily bigger logic dies. It is memory, specifically high-bandwidth memory (HBM). The average AI accelerator is expected to integrate roughly 250 HBM dies by 2030. NVIDIA’s Rubin Ultra-class designs are projected to approach approximately 1 TB of HBM through higher stack counts and heights. As Stephen Russell notes, the AI-driven surge in HBM and advanced memory is likely to raise semiconductor manufacturing emissions in absolute terms, increasing memory wafer starts and adding process complexity even as leading manufacturers improve efficiency per transistor.

There is a subtler dimension the report explores carefully: yield. Stacking dies compounds yield loss, and in tall-stack HBM scenarios, stacking yields above 93% are necessary to prevent emissions per usable stack from rising sharply. That makes yield learning and process control first-order sustainability levers, not just cost levers.

The Client Device Story: Carbon Paid Upfront

The report’s third major focus is consumer and enterprise devices, where on-device AI is often framed as an operational efficiency win. Fewer cloud calls, lower network load, specialized local hardware: all genuine benefits. But the manufacturing emissions for those devices are paid upfront, and they are concentrated in places that might surprise you.

Using teardown-based analysis of AI PCs including recent Microsoft Surface and ASUS Zenbook models, the report finds a consistent pattern: memory and storage, not the headline processor or NPU, account for the majority of embodied carbon in AI PC platforms. Across the examples evaluated, memory accounts for roughly 43% to 57% of packaged-IC CO₂e, while the applications processor accounts for only about 14% to 21%.

The supplier concentration finding is particularly actionable. In one Surface Laptop 7 configuration, three suppliers account for approximately 73% of packaged-IC carbon. In a Zenbook S14 model, three suppliers account for roughly 84%. A small number of parts and vendors determine most of the footprint, which means platform configuration and supplier selection are among the highest-leverage carbon choices a product team can make.

What Can Actually Be Done

The report identifies a clear set of high-leverage actions: pursuing cleaner electricity and power purchase agreements, reducing yield loss and rework especially late in the flow and in stacked memory, substituting low-GWP gases with higher abatement efficiency, improving tool energy and utilization, and optimizing bit density and platform configuration.

Semiconductor sustainability has become a decision problem. The highest-impact choices around fab location, memory configuration, supplier mix, and platform architecture are made before a product ships, carrying carbon consequences that most legacy reporting methods cannot capture. The full report, Carbon in the Age of AI Chips, is available now.

LINK: Carbon in the Age of AI Chips | Earth Day eBook | TechInsights

Stephen Russell: Senior Technical Fellow

As Senior Technical Fellow for Sustainability at TechInsights, Stephen provides expert insight into carbon footprint across the entire technology life cycle, from raw materials through product manufacturing, use and end of life. Stephen also works on unique initiatives to characterize Scope 3 emissions in the use phase of consumer electronics products, with further reaching implications for data center and automotive applications.

Stephen is internationally recognized for technical research contributions and collaborations. These include being awarded best paper 2018 for the IEEE Journal Transactions on Power Electronics paper “High Temperature Electrical and Thermal Aging Performance and Application Considerations for SiC power DMOSFETs”. He led an exploratory research project in gallium oxide for power devices, presenting findings to the Royal Institution, London. While working in industry, he led the development of a new silicon IGBT product line and instigated a research and development project to use silicon carbide JFETs in circuit protection applications.

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April 22, 2026April 22, 2026

TSMC Technology Symposium 2026 Overview

TSMC Technology Symposium 2026 Overview
by Daniel Nenni on 04-22-2026 at 12:00 pm
Categories: Events, Foundries, TSMC
2 Comments

Yes, it is that time of year again, the 2026 TSMC Technology Symposium kick-off event in Silicon Valley. TSMC has never been in a better position to forecast the future of semiconductor technology and the industry itself. TSMC closely collaborates with the top semiconductor companies around the world and the top players in the semiconductor ecosystem. Never in the history of TSMC have they been in such a prominent position and the information that comes from that is astounding.

Dr. Kevin Zhang, Senior Vice President and Deputy Co-COO, again honored us with a press briefing before the event which is what we are talking about today. Next week we will talk in more detail about the event itself and some of the announcements. Unlike most of the media I will be there live with SemiWiki blogger Kalar Rajendiran.

Again, this is TSMC’s perspective on the semiconductor industry but it is backed collectively by the entire semiconductor ecosystem, absolutely.

The semiconductor industry is entering a new phase of accelerated growth and architectural transformation, driven primarily by artificial intelligence (AI) and high-performance computing (HPC). Recent projections indicate that semiconductor market growth has significantly outpaced earlier expectations, rising from a forecasted 10% to an actual 23% annual increase, with future projections reaching approximately 45% growth . This rapid expansion is largely attributed to AI-driven demand, which is reshaping both technology development and system-level design.

Could this be the first year that the semiconductor industry outpaces TSMC? Hard to believe but yes. TSMC revenue is expected by me to grow 30-40%. Here is the hitch: While wafer pricing is stable chip pricing is not. The bulk of the 45% revenue growth is due to chip pricing versus chip unit sales. Memory pricing is a big part of this but some of the AI chips (NVIDIA) are also selling at a premium.

A major milestone in this transformation is the advancement of global semiconductor revenue toward the $1 trillion mark, now expected to be achieved earlier than previously projected. As illustrated in the industry trend chart, AI represents the latest inflection point following previous computing waves such as PCs, the internet, and smartphones. By 2030, the semiconductor market is expected to exceed $1.5 trillion, with HPC and AI contributing over 55% of total demand, far surpassing other segments like smartphones (20%), automotive (10%), and IoT (10%) .

At the core of this growth is continuous innovation in semiconductor process technology. The roadmap for advanced nodes demonstrates a steady progression from nanometer-scale fabrication toward angstrom-class technologies. Nodes such as TSMC N2 and its enhanced derivative TSMC N2U focus on improving power, performance, and area (PPA) through design-technology co-optimization (DTCO). According to the technical data presented, N2U offers a 3–4% speed improvement at constant power, up to 10% power reduction at the same speed, and a modest increase in logic density. These incremental improvements are critical for maximizing return on investment for chip designers while maintaining compatibility with previous node designs.

Further advancements are seen in next-generation nodes such as A13, which extend technology leadership through optical shrink techniques. A 97% optical shrink enables approximately 6% area reduction while preserving backward compatibility in design rules. This allows designers to benefit from improved density without requiring extensive redesign, thereby accelerating product deployment.

While transistor scaling remains important, it is no longer sufficient to meet the exponential demands of AI workloads. Consequently, advanced packaging and system integration technologies have become central to performance scaling. Technologies such as CoWoS (Chip-on-Wafer-on-Substrate) and SoIC (System-on-Integrated-Chips) enable heterogeneous integration of logic and memory components. The HPC platform diagram illustrates how advanced logic dies, high-bandwidth memory (HBM), and photonic components are integrated into a single package to maximize compute density and efficiency.

The scaling of interposer size is a key enabler of this integration. Interposer capacity is expanding from 3.3 reticle sizes to over 14 reticles by 2029, supporting up to 24 HBM stacks. This expansion allows for massive increases in memory bandwidth and compute capability. Additionally, wafer-scale integration technologies such as System-on-Wafer (SoW) extend this concept further, enabling integration at scales exceeding 40 reticles, equivalent to 64 HBM stacks.

Three-dimensional stacking technologies also play a critical role in enhancing interconnect density and power efficiency. SoIC technology enables vertical integration with significantly higher interconnect density—up to 56× compared to traditional 2.5D approaches—and improved power efficiency. This shift from planar to vertical integration reflects a broader industry trend toward system-level optimization rather than purely transistor-level scaling.

The impact of these innovations is evident in system-level performance metrics. The number of compute transistors within a single CoWoS package is projected to increase by up to 48× between 2024 and 2029. Similarly, memory bandwidth is expected to scale by 34× during the same period, driven by advancements in HBM technology and integration techniques.

Another critical innovation is the adoption of co-packaged optics (CPO) for high-speed interconnects. Traditional electrical interconnects face limitations in power efficiency and latency. By integrating optical communication directly into the package, systems can achieve up to 10× improvements in power efficiency and 20× reductions in latency, as shown in a performance comparison chart. This transition from electrical to optical signaling is essential for scaling AI infrastructure, where massive data movement between compute units is required.

Beyond data centers, semiconductor advancements are also enabling the emergence of physical AI applications, particularly in automotive and robotics. Modern vehicles are evolving into compute-centric platforms with significantly increased silicon content, incorporating advanced processors, sensors, and connectivity modules. Looking forward, humanoid robots represent a convergence of digital AI and physical interaction, requiring integrated systems for sensing, computation, motion control, and power management.

Bottom line: The semiconductor industry is transitioning from traditional scaling paradigms to a holistic, system-level approach that integrates advanced process nodes, heterogeneous packaging, photonics, and AI-driven architectures. This convergence is enabling unprecedented growth in computational capability and will define the technological landscape of the next decade.

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April 22, 2026April 22, 2026

Could Neutral Atoms Take the Lead in Quantum Computing?

Could Neutral Atoms Take the Lead in Quantum Computing?
by Bernard Murphy on 04-22-2026 at 10:00 am
Categories: Quantum Computing

As of my recent posts on quantum computing (QC), superconducting QC is the leading technology contender, exemplified in systems from IBM, Google, and Fujitsu. Other technologies such as ion trap, neutral atom, photonic and quantum dot have generally been viewed as intriguing but second tier. I just read a very recent paper suggesting that neutral atom methods may have more potential than I thought. The paper is technically very dense and I haven’t yet had a chance to fully digest some of the claims, but what I have read suggests some very interesting shifts in what might be possible through neutral atom-based QC.

A neutral atom QC architecture. Image courtesy Oratomic, Caltech and Berkeley (in paper referenced above)

Backgrounder on neutral atom QCs

Neutral atom technologies suspend an array of atoms in vacuum, each atom acting as a very pure qubit. Atoms with a single valence electron such as rubidium or cesium allow information to be stored in hyperfine states split by interaction between the valence electron spin and the nuclear magnetic moment. Atoms are held in place using laser-based optical tweezers.

Lasers operating at different frequencies perform multiple functions. Laser cooling minimizes thermal motion and initializes qubit states. Simple gating operations (Clifford gates like X, Hadamard and S) are implemented through targeted laser pulses addressing individual qubits. Two qubit gates are implemented by pumping the control atom/qubit to a highly excited (Rydberg) state with a greatly expanded electron wavefunction. This can interact with neighboring qubits, enabling entanglement. Finally, measurement is accomplished through targeted laser-stimulated resonance fluorescence. Lots of lasers, yet research indicates this complexity is becoming manageable.

Neutral atom methods offer a very intriguing advantage over fixed qubit technologies (most if not all other options). Fixed qubit methods (superconducting for example) only allow for communication between nearest-neighbor qubits. Algorithms which need to superpose or entangle geometrically distant qubits require multiple SWAP gates to cross the gap, amplifying error rates. In neutral atom arrays, optical tweezers can be steered to reconfigure qubits dynamically. If qubit A needs to interact with qubit B and they are not adjacent, steer them to be adjacent, perform the operation then steer those qubits back to their original positions.

A major step forward for quantum architectures

Reconfigurability may not seem like such a big deal, but it opens an important option for QC architectures. An architecture can be partitioned into distinct components (see the figure above): a memory, a processor and a resource for magic states (supporting operations beyond Clifford gates, like T-gates and Toffoli-gates). Communication between these functional units is accomplished through teleportation, a proven method to transfer quantum state from one qubit to another using entanglement (this is different from reconfiguring). Lots of quantum weirdness but now starting to look more familiar as a computer architecture.

There is a second benefit, in quantum error correction (QEC). You may remember that QEC is conceptually similar to classical error correction, using additional (ancilla) qubits to check and correct errors. Except that QEC can require 1000 physical qubits for every logical qubit, which is why it is proving so difficult to get to high logical qubit counts in fault-tolerant systems. It appears that reconfigurability in neutral atom systems can dramatically reduce ancilla qubit demand.

The state of the art for QEC in fixed qubit systems uses a mechanism called “surface codes” which has somewhat reduced the physical to logical qubit threshold but still requires hundreds of physical qubits for every logical qubit. The Oratomic paper suggests a Low-Density Parity Code method offering better than two orders of magnitude reduction over those surface codes in required physical qubits. Further, qubits not currently participating in active processing can be moved to a less noisy storage area (memory) with lower error potential until needed again. Overall, greatly reduced QEC impact in necessary ancilla qubits. Potentially making fault-tolerant QC much closer than we had thought.

Caution and some implications

The paper suggests that a few techniques proposed in support of this technology are still in development. That said, Oratomic launched in March this year, founded and staffed by authors of this paper, to deliver a reconfigurable neutral atom computer along these lines. Given how new they are, we should probably expect the usual teething problems.

Still, if they deliver, Shor’s algorithm may be implementable at cryptographically significant levels (RSA-2048 and ECC-256) sooner that we expected, potentially within this decade. That’s the downside, but the upside is that quantum compute for much more interesting application may also be closer than we thought.

One more thought: compiling to, topologically organizing and simulating these systems will become a lot more interesting. Opportunities for EDA and compiler tech development!

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April 22, 2026April 22, 2026

Transitioning Voltage Regulator Design From Unidirectional To Bidirectional

Transitioning Voltage Regulator Design From Unidirectional To Bidirectional
by Daniel Nenni on 04-22-2026 at 8:00 am
Categories: Alphacore, IP

An interesting article by Nazzareno Rossetti, published in How2Power Today, explores the transition from designing traditional unidirectional voltage regulators to bidirectional converters essential for modern energy management systems (EMSs). These systems optimize energy flow and storage among electric vehicles, photovoltaic arrays, home batteries, and the grid, requiring components like regulators and chargers to handle power in both directions seamlessly.

Most power electronics experience stems from unidirectional applications, such as buck converters supplying CPUs or mobile devices. Here, energy flows one way from a variable input to a regulated output powering passive loads. Transitioning to bidirectional operation, exemplified by the phase-shift dual active bridge (DAB) converter, represents a significant shift. Designers accustomed to unidirectional PWM buck control may feel unprepared for DAB complexities. Rossetti bridges this gap by demonstrating that bidirectionality is not entirely foreign—elements already exist in conventional designs.

Synchronous power stages reveal inherent bidirectionality. In a synchronously rectified buck converter (e.g., 12 V to 1.8 V), inductor current ripple at light load can dip negative, causing brief reverse energy flow from output to input. This “annoyance” disrupts regulation and efficiency, often requiring designers to disable synchronous rectification at low loads. Similarly, in PWM full-bridge motor drivers, current recirculates back to the input during off-time, risking capacitor overvoltage.

These examples show synchronous half-bridges naturally support bidirectional flow. Rossetti illustrates this by reconfiguring the same power train: placing feedback at the low-voltage side yields a buck converter (current from high to low), while placing it at the high-voltage side creates a boost (current from low to high). Thus, the topology can exchange energy between nodes bidirectionally for instance, allowing a depleted 1.8-V battery to draw from a 12-V battery or vice versa.

Conventional hard-switched converters suffer efficiency losses during switching transitions. Negative current in light-load scenarios enables zero-voltage switching (ZVS) by bootstrapping the switching node, but only with excessive ripple relative to DC load current, impractical for most uses. The solution lies in embracing reverse current fully via two-stage topologies that generate a zero-average, 50% duty-cycle square-wave current for soft switching, then rectify it to DC.

The phase-shift DAB exemplifies this approach. It features isolated full bridges on primary and secondary sides, connected via a high-frequency transformer. Phase-shift modulation between bridges controls power direction and magnitude at fixed frequency. Primary and secondary phase-shift chains, with proportional-integral compensation, regulate the designated output port. Auxiliary flyback converters and pulse transformers provide high-side gate drive and isolated feedback. Dead-time generation prevents shoot-through.

Simulations for grid-tied/off-grid storage applications (100 V to 5000 V DC link) show bipolar inductor current enabling consistent ZVS. Phase-shift control outperforms PWM by maintaining fixed frequency, simpler filtering, easier gate-drive design, and fewer diode conductions, yielding excellent full-load efficiency (though light-load performance degrades as ZVS weakens).

Rossetti concludes that emerging bidirectional markets challenge designers under tight deadlines. Yet, familiar tools like synchronous half-bridges form the foundation. A full bridge extends two half-bridges, and with imagination, unidirectional concepts evolve into mature bidirectional architectures like the DAB. This perspective eases the mindset shift from one-way to two-way energy control, helping engineers deliver innovative solutions for EMS applications.

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