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CEO Interview: Sandeep Kumar of L&T Semiconductor Technologies Ltd.

CEO Interview: Sandeep Kumar of L&T Semiconductor Technologies Ltd.
by Daniel Nenni on 11-22-2024 at 6:00 am

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Sandeep Kumar is the Chief Executive of LTSCT (L&T Semiconductor Technologies Ltd). A seasoned technology executive with over 35 years of experience, Kumar has a proven track record in building and scaling technology businesses globally.

As a pioneer in the Indian semiconductor industry, he has co-founded multiple technology ventures and holds leadership positions in several high-growth companies. His expertise spans technology development, finance, M&A, and global partnerships.

Currently, Kumar also serves as the Chief Mentor for the Indian government’s AI CoE, Neuron. He also chairs the boards of Qritrim (enterprise AI), Bhartel (communications, networking, and energy systems), and Mekumi (EdTech). He is also a Partner at Kizki Japan Fund, TMPC Japan, and Global Ascent Partners.

An active investor and advisor, Kumar is involved with numerous startups, MSMEs, and MNCs worldwide as a board member. His deep industry knowledge and extensive network make him a sought-after leader in the technology ecosystem. His global reach extends to the US, India, Japan, China, Taiwan, Chile, Mexico, Israel, and Russia.

Prior to his entrepreneurial pursuits, Kumar held key positions at established corporations. He was a Managing Partner at TechRanch incubator and held leadership roles at Texas Instruments, where he headed the Broadband Business Division and the Global Microcontroller R&D Division. He has also been a Partner at venture capital firms JVP and Crimson.

Tell us about your company?
L&T Semiconductor Technologies (LTSCT) is India’s first major fabless product semiconductor company, pioneering the next generation of semiconductor solutions. Our focus is on designing and delivering smart semiconductor devices for global markets, offering a wide range of semiconductor technologies that enable energy-efficient and high-performance systems. These solutions are critical in sectors like mobility, industrial, and energy.

Our product portfolio spans across smart analog, MEMS & sensors, RF and power electronics, helping sectors with competitive technology solutions. To achieve this, we are leveraging key trends such as electrification, data-driven technologies, and advanced processors. We are committed to supporting decarbonization and digitalization efforts globally, and our mission is to empower our customers with market-leading power, sense, and control integrated circuits.

With a strong presence across India, US, Europe, and Japan, we are positioned to deliver innovative semiconductor technologies and solutions to a diverse set of customers around the world. Our goal is to be a key driver of smart, efficient applications that address the critical needs of a rapidly evolving, tech-driven world.

What problems are you solving?

At L&T Semiconductor Technologies, we’ve chosen the path of chip design over chip manufacturing because we see a tremendous opportunity to address the technology-oriented transformation happening in critical sectors such as mobility, industrial, and energy. These sectors are evolving rapidly, moving from traditional hardware systems to more advanced solutions, creating demand for cutting-edge semiconductor technologies that can support innovations like smarter, more efficient vehicles, smart grids, and Industry 4.0. By focusing on chip design, we can lead the development of these technologies and meet the future needs of these industries.

By specializing in design, we can be agile, respond faster to market needs, and deliver cutting-edge semiconductor technologies that drive efficiency and future readiness. While India is ramping up its manufacturing, our long-term vision is to integrate both design and manufacturing, positioning ourselves as a global semiconductor leader with deep roots in India’s growth story.

What application areas are your strongest?

Our innovative product offerings focus on areas such as mobility, industrial, and energy infrastructure to usher in the next-generation applications.

In mobility, we are working on high-end silicon chips to support the shift toward software-defined vehicles and electric mobility. In the industrial space, our focus is on designing chips that drive automation and smart manufacturing, aligning with the Industry 4.0 movement. The energy sector is evolving with the rise of smart grids and renewable energy integration, and our chips enable real-time data flow and optimized power management in these environments.

In the long term, our goal is also to establish three distinct fabs, each requiring different levels of investment to cater to different technologies, ranging from high-end silicon to SiC and GaN chips. Thus, ensuring we address the specific needs of these sectors while leading the market. Investment decisions will depend on returns and the availability of financial incentives from the government at that time.

What keeps your customers up at night?

We are focusing on customers from mobility, industrial, and energy sectors, as these sectors are strategically important for India and are seeing an increasing push by the government to achieve localization and reduce dependency on global supply chains.  Therefore, our customers need to achieve supply chain resiliency. In addition, global efforts on net-zero and decarbonization are pushing our customers to achieve aggressive targets in a very short period.

LTSCT is a global company with a strong development footprint in India. India offers a stable source of design expertise, a large resource pool in semiconductors, and a nation that is looked upon by others as one that follows strong IP protection, and a non-monopolistic policy. Indian companies have transparency levels that are as advanced as any other free economy. LTSCT provides globally competitive semiconductor solutions to the world that help them diversify and secure a stable supply chain.

Our core vision is to develop ethical and secure solutions that help achieve decarbonization for a globally interconnected digital economy. We combine advanced technologies, creative system design, and strong IP to develop solutions that help our customers meet their net-zero goals while realising energy efficient, high-performance systems to benefit from data, electrification, and the latest technology trends.

What does the competitive landscape look like and how do you differentiate?

The global semiconductor design landscape is highly competitive, with companies vying for market share through mergers and acquisitions. Companies are also heavily investing in their R&D investments, especially areas like artificial intelligence, machine learning, Internet of Things (IoT), autonomous vehicles, and high-performance computing. The industry is witnessing a geographic shift, with Asia emerging as a major player. The growing demand for specialized chips and the rapid pace of technological advancements further intensify competition.

We are committed to driving the shift towards software-defined systems across focus domains. Our focus on chip design for innovations like advanced tech-driven vehicles, smart grids, and Industry 4.0 positions us as leaders in these rapidly evolving markets. LTSCT’s fabless model allows the company to stay agile and responsive to market demands, enabling faster development of cutting-edge technologies. We are leveraging our country’s strength in engineering and innovation while avoiding the massive capital costs associated with semiconductor fabrication. This strategy positions India to succeed in a complex and competitive market, even as it continues to scale its operations and workforce.

What sets us apart is our holistic, system-level approach—we work closely with clients to understand the entire system and deliver a differentiated solution. This includes ensuring software upgradability and adaptability, crucial across sectors/domains where over-the-air updates are becoming essential. Our global reach and local expertise ensure we bring the right innovation and differentiation to the market.

What new features/technology are you working on?

This is one of the most exciting times in the history of technology, specifically India’s semiconductor tech ecosystem. Semiconductors are changing how all industries operate and reimagining how conventional architecture is being designed and used. We are working towards creating innovative solutions to support India’s ambition to become a global semiconductor manufacturing hub by significantly elevating India’s technological capabilities.

Our recent partnership with IBM aims to harness our cutting-edge semiconductor design technology and IBM’s advanced processors to forge next-gen technology products through R&D. We are elevating India’s landscape of surveillance technology by developing a comprehensive range of indigenous Indian IP SoCs (Systems on Chips) for advanced AI IP CCTV products, through one of our collaborations.

Apart from corporate collaborations, we have partnered with C-DAC to create a powerful commercialisation programme for advanced technologies created by C-DAC in semiconductor design and development, embedded software, open-source OS, HPC, and power systems. We are transforming their portfolio of indigenous IPs into global products. Additionally, we have entered a partnership with one of the prominent institutions in the country, IIT Gandhinagar, to develop semiconductor solutions for projects of national importance.

We are thus, strategically collaborating with organisations and academia to create innovative semiconductor solutions with improved functionality and performance.

Also Read:

CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix

CEO Interview: Bijan Kiani of Mach42

CEO Interview: Dr. Adam Carter of OpenLight

CEO Interview: Sean Park of Point2 Technology


Semiconductors Slowing in 2025

Semiconductors Slowing in 2025
by Bill Jewell on 11-21-2024 at 2:00 pm

Semiconductor Market Forecasts 2024 SemiWiki

WSTS reported third-quarter 2024 semiconductor market growth of $166 billion, up 10.7 percent from second-quarter 2024. 3Q 2024 growth was the highest quarter-to-quarter growth since 11.6% in 3Q 2016, eight years ago. 3Q 2024 growth versus a year ago was 23.2%, the highest year-to-year growth since 28.3% in 4Q 2021.

Nvidia remained the largest semiconductor company in 3Q 2024 with $35.1 billion in revenue due to its strength in AI GPUs. Nvidia sells its AI GPUs as modules which include memory supplied by SK Hynix, Micron Technology, and Samsung as well as other components supplied by outside vendors. Thus, Nvidia’s semiconductor revenue from its own devices is less than its total revenue. However, Nvidia would still be the largest semiconductor company even if externally purchased components were excluded. Samsung Semiconductor was second at $22.0 billion with memory for AI servers cited as a major revenue driver. Broadcom remained third with its guidance for 3Q 2024 at $14.0 billion. Broadcom highlighted its AI semiconductors as a growth driver. Intel and SK Hynix rounded out the top five.

The third quarter of 2024 was robust for most major semiconductor companies. The memory companies SK Hynix, Micron Technology, and Kioxia all reported double-digit revenue growth in 3Q 2024 versus 2Q 2024. Nvidia and AMD each reported 17% growth due to AI data center demand. The only company showing declining revenue was Renesas Electronics, down 3.8% due to a weak automotive market and inventory reductions. The weighted average revenue growth for 3Q 2024 versus 2Q 2024 for the sixteen companies was 10%.

The outlook for 4Q 2024 shows diverging trends. The data center market, driven by AI, is expected to lead to substantial revenue growth for Nvidia, Micron, and AMD. Samsung Semiconductor and SK Hynix did not provide specific 4Q 2024 revenue guidance, but both cited AI server demand as strong. Companies which are dependent on the automotive industry expect a weak 4Q 2024. Infineon Technologies, Texas Instruments, NXP Semiconductors, and Renesas Electronics all guided for revenue declines in 4Q 2024 based on a weak automotive market and inventory reductions. STMicroelectronics also cited these factors but expects a 2.1% revenue increase. The companies heavily dependent on smartphones have differing revenue expectations, with Qualcomm guiding up 7.2% and MediaTek guiding down 1.0%. The weighted average guidance for 4Q 2024 versus 3Q 2024 is a 3% increase. However, the individual company guidance varies widely, from plus 12% from Micron to an 18% decline from Infineon and a 19% decline from Renesas.

As is the case with 4Q 2024 guidance, the outlook for year 2025 is mixed. AI will drive 2024 server growth in dollars to 42%, according to IDC. 2025 server growth will still be a strong 11% but it will be a significant deceleration from 2024. Smartphones and PCs each recovered to growth in 2024 from 2023 declines. IDC expects 2025 modest growth of smartphones and PCs in the low single-digits. Light vehicle production was a robust 10% in 2023 due to the post-pandemic recovery. S&P Global Mobility shows a 2.1% decline in production in 2024. Production is expected to recover slightly to a 1.8% growth in 2025.

The impact of the memory market also needs to be considered. WSTS’ June 2024 forecast called for 16% semiconductor market growth, with memory growing 77% and non-memory only growing 2.6%. Much of the memory growth in 2024 has been driven by price increases which are certain to slow in 2025.

The chart below shows recent forecasts for the semiconductor market in 2024 and 2025. 2024 forecasts are converging in the range of 15% from Future Horizons to 19% from us at Semiconductor Intelligence (SC-IQ). 2025 forecasts are in two camps. RCD Strategic Advisors and Gartner project slightly slower growth than 2024 at 16% and 13.8%, respectively. We at Semiconductor Intelligence expect significantly slower growth at only 6% in 2025. Future Horizons also sees slower growth at 8%. Our 2025 assumptions are:

· Continued growth in AI, though decelerating
· Healthy memory demand due to AI, but prices moderating
· Mediocre growth for PCs and smartphones
· Relatively weak automotive market
· Potential higher tariffs (particularly in the U.S.) affecting consumer demand

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com

Also Read:

AI Semiconductor Market

Asia Driving Electronics Growth

Robust Semiconductor Market in 2024

Semiconductor CapEx Down in 2024, Up Strongly in 2025


Relationships with IP Vendors

Relationships with IP Vendors
by Daniel Nenni on 11-21-2024 at 10:00 am

Semiwiki Blog Post #3 Image #2

An animated panel discussion Design Automation Conference in June offered up a view of the state of RISC-V and open-source functional verification and a wealth of good material for a three-part blog post series.

Parts One and Two covered a range of topics from microcontroller versus more general-purpose processor versus running a full stack with an operating system and buying from a major vendor versus picking open source and adding instructions versus keeping it pristine.

In Part Three, Ron Wilson and Contributing Editor to the Ojo-Yoshida Report tidies up the discussion by asking how to determine the right questions for an IP vendor and whether the functional models are in place. Answering those questions and more were Jean-Marie Brunet, Vice President and General Manager of Hardware-Assisted Verification at Siemens; Ty Garibay, President of Condor Computing; Darren Jones, Distinguished Engineer and Solution Architect with Andes Technology; and Josh Scheid, Head of Design Verification at Ventana Microsystems.

Wilson: Is the gold standard to have asked all the right questions of the vendor. Or is the gold standard to see the RTL performing functionally correctly with the software stack?

Scheid: Designers must focus on both at different stages of the project. It needs vendor selection and what’s needed from the vendor selected. The designer will need to commit to that at some point. The amount of effort it takes to go from evaluating IP into a hardware prototyping platform where the designer can see all that working is a significant investment already.

Garibay: Designers would be happy to have a vendor selection problem with the Arm core, but they don’t. It’s a little unfair to focus on that for RISC-V. Because many of the players in the RISC-V market are relatively new, they have to establish a track record and earn user trust. Arm has been doing that for years and has done a good job. I have no problem staying to the current gold standard and what we all hope to be the challenge.

How can we compare each of the potential players in RISC-V today? It’s knowing the people, their track records, their companies and business profiles. As we move forward and IP becomes silicon, we’ll find out who the real viable players are. Go ahead, disagree.

Jones: CPU IP are complex designs, especially the higher performance ones with so many transistors dedicated to eking out that last quarter of a percent of performance. It’s difficult to verify. That’s why it still matters that at first silicon, a designer can see Linux is booting. Booting Linux is huge because Linux seems simple when turning on the computer. It comes to a prompt. But it just ran billions of instructions and probably touched 90%-plus of the system to get to that prompt.

Scheid: I agree. Designers need a greater relationship with their IP vendor and a good understanding of what has been done and what has been verified. They also need to verify even more themselves. In our space, providing solutions to assist the verification of an SoC or IP integration is good because there are greater challenges associated with it. Ultimately, they’re going to measure up to the point where they boot Linux and see what’s happening. To do this, they need to have an entire SoC where each component talks correctly to each other. That’s a huge task.

Jones: We are talking about the CPU instructions and that’s not the hardest part. When a designer is trying to verify an SoC, the hardest part is the interconnect and the buses and that’s not RISC-V versus Arm. These processors use AXI, an industry standard. That’s where the verification IP is needed. Otherwise, how does a designer find bus exercisers and monitors? It’s more about the large SoC than it is the pieces.

Wilson: Because you did your job, it can be about integration. It sounds like you agree that we’re at that stage, if licensing from an experienced, reputable vendor.

Garibay: If I look at what I expect to be the total challenge for verification of our CPU, the percentage of what is ISA-specific is maybe 10%. Yes, designers must check all the boxes, make sure all the bits are in the right place, and they flip and twiddle correctly. At that level of performance, we’re shooting for with hundreds and hundreds of instructions in flight at any one time. It doesn’t matter which ISA. Making sure that the execution is correct and that the performance is 90% of verification

I’ve done 68,000, x86, MIPS, Arm, PowerPC, a couple of proprietaries and now RISC-V. The difference is not substantial, other than the fact that the theoretical ownership of the specification lies with an external body that is a committee. That’s the main difference. Typically, the ownership has always lived with MIPS or PowerPC, Arm or x86 Duo. Yes, the difference is that the ownership is in a committee. Once the committee makes a call, the industry lives with it.

Scheid: We can contribute as well, whether it’s systemic concerns about software availability or specification extension capabilities that have multiple vendors on stage to talk about these things.

That’s the power of RISC-V. When looking at these solutions, we’re all interested in addressing concerns, making sure everyone’s communicating about what the CPU implements, what the software expects, what user software may run. Systemic risks with other solutions are put aside with the way that RISC-V is set up.

Garibay: It’s not our interests to put out a bad product. We all are cheering for each other.

Brunet: The RISC-V community and ecosystem and the market have mature chips using the RISC-V core, and everything works well. It’s a good sign.

Wilson: You mentioned earlier virtual models. The same question with best functional models. Are those in place? Are they coming?

Jones: Models of RISC-V are publicly available from Imperas. RISC-V is not immature.

Garibay: Designers can get the models. What they run on them may be a challenge.

Also Read:

Changing RISC-V Verification Requirements, Standardization, Infrastructure

The RISC-V and Open-Source Functional Verification Challenge

Andes Technology is Expanding RISC-V’s Horizons in High-Performance Computing Applications


Silicon Creations is Fueling Next Generation Chips

Silicon Creations is Fueling Next Generation Chips
by Mike Gianfagna on 11-21-2024 at 6:00 am

Silicon Creations is Fueling Next Generation Chips

Next generation semiconductor design puts new stress on traditionally low-key parts of the design process. One example is packaging, which used to be the clean-up spot at the end of the design. Thanks to chiplet-based design, package engineers are now rock stars. Analog design is another one of those disciplines.

Not long ago, analog design had a niche place in semiconductor design for the small but important part of the system that interfaced to the real world. Thanks to the performance demand of things like AI, analog design is now a critical enabling technology for just about every system. Data communication speed and latency as well as ubiquitous sensor arrays are prevalent in all advanced designs. These technologies now rely on analog design. At a recent Siemens event, substantial details were presented about this change in system design. Let’s dig into how Silicon Creations is fueling next generation chips.

The Event

Siemens EDA held its Custom IC Verification Forum recently on August 27 in Austin. The event aimed to present a comprehensive view of leading-edge AI-enabled design and verification solutions for custom ICs.  Topics such as circuit simulation, mixed signal verification, nominal to high-sigma variation analysis, library characterization, and IP quality assurance were all covered.

You can check out more details about this event here. What you will see is most of the presentations are given by Siemens folks, with one exception. They keynote address is delivered by Silicon Creations. I’d like to cover the eye-opening insights presented in that keynote.

The Keynote

Randy Caplan

Randy Caplan, Principal and Co-Founder of Silicon Creations presented the keynote, entitled Increasing Analog Complexity is a Reality for Next Generation Chips. For nearly 18 years, Randy has helped to grow Silicon Creations into a leading semiconductor IP company with more than 450 customers in over 20 countries, with a remarkable statistic of nearly 100% employee retention.

Silicon Creations’ designs have been included in over 1,500 mass-produced chips from 2nm to 350nm, from which more than ten million wafers were shipped. The company is known for award-winning analog mixed-signal silicon intellectual property that lowers risk. You can learn about this unique company on SemiWiki here.

Randy’s keynote presented a great deal of information about how chip/system design is changing. He presented many trends, backed-up with detailed data to illustrate how growing complexity is enabled by high-performance analog IP. Below is one example that surprised me. We are all aware of the growth in MOS logic and memory. However, shipments of analog chips are actually growing much faster, indicates how ubiquitous analog IP is becoming across many markets.

Unit forecasts

Randy covered many other relevant and interesting topics in his keynote, including the evolution from monolithic to multi-die design, process technology evolution, multi-core trends, the growth of analog functions required for advanced designs, reliability considerations, and a broad overview of design and process challenges. The unique demands of SerDes and PLL design are also explored.

There are examples presented, along with several architectural options to consider. The collaboration between Silicon Creations and Siemens is discussed, along with details around the use of Siemens Solido, Calibre and Questa solutions are presented.

To Learn More

I have provided a high-level overview of the topics covered in Randy’s keynote. There is much more detail and many more insights available in the slides. If analog content is becoming more important to your chip projects, you should get your own copy of this important keynote address. You can download it here and learn more about how Silicon Creations is fueling next generation chips.


I will see you at the Substrate Vision Summit in Santa Clara

I will see you at the Substrate Vision Summit in Santa Clara
by Daniel Nenni on 11-20-2024 at 10:00 am

Soitec Substrate Vision Summit

WIth packaging being one of the top sources of traffic on SemiWiki, I am expecting a big crowd at this event. A semiconductor substrate is a foundational material used in the fabrication of semiconductor devices. Substrates are a critical part of the manufacturing process and directly affect the performance, reliability, and efficiency of 3D IC based semiconductor devices.

I will be moderating a panel at this event and you certainly do not want to miss that!

AI’s impact on the semiconductor value chain is profound, enabling faster, more efficient, and more innovative approaches across all stages, from material discovery to design, fabrication, and testing. By leveraging AI technologies, the semiconductor industry can address the challenges of scaling, complexity, and demand for high-performance chips in emerging fields like AI, IoT, 5G, and beyond. Panelists will discuss this challenge. 

Panel discussion (Intel, Meta Reality Lab, Samsung Foundry Soitec, moderated by Daniel Nenni).

Register Here

Substrate Vision Summit, organized by Soitec, gathers leading engineers and industry professionals to explore the cutting-edge developments in semiconductor materials that are shaping the future of technology. This event provides a platform for the exchange of ideas, research findings, and technological advancements that are driving the evolution of the semiconductor industry.

As the demand for faster, smaller, and more efficient electronic devices continues to surge, the role of advanced semiconductor materials becomes increasingly critical. This conference will delve into topics such as the latest breakthroughs in silicon-based technologies, the rise of alternative materials like gallium nitride (GaN) and silicon carbide (SiC).

Keynote speakers, including prominent industry leaders, will share their insights on the future directions of semiconductor research and development. Technical sessions will cover a range of themes, from material synthesis and characterization to device fabrication and application. Attendees will have the opportunity to engage in in-depth discussions on challenges and solutions related to material performance, scalability, and sustainability.

Networking sessions and panel discussions will provide additional opportunities for collaboration and knowledge exchange, fostering connections that can lead to innovative partnerships and advancements in the field.

Join us at the Substrate Vision Summit to stay at the forefront of this dynamic and rapidly evolving industry. Together, we will explore the materials that are set to revolutionize electronics and enable the next generation of technological innovation.

Agenda
[ Registration Required ]
Wednesday, December 4
8:00 AM – 9:00 AM
9:00 AM – 9:20 AM
Pierre Barnabé – CEO
9:20 AM – 9:40 AM
Ajit Manocha – CEO & President
9:40 AM – 10:00 AM
Barbara De Salvo – Director of Research
10:00 AM – 10:15 AM
10:15 AM – 10:35 AM
David Thompson – Vice President, Technology Research Processing Engineering
10:35 AM – 11:05 AM
Christophe Maleville – CTO & SEVP of Innovation
11:05 AM – 12:00 PM
12:00 PM – 1:10 PM
1:10 PM – 1:20 PM
Afternoon Track
1:20 PM – 1:45 PM
Panel Discussion – Afternoon Track
1:45 PM – 2:15 PM
Panel Discussion – Afternoon Track
2:15 PM – 2:25 PM
Afternoon Track
2:25 PM – 2:50 PM
Panel Discussion – Afternoon Track
2:50 PM – 3:05 PM
3:05 PM – 3:35 PM
Panel Discussion – Afternoon Track
3:35 PM – 3:45 PM
Afternoon Track
3:45 PM – 4:30 PM
Panel Discussion – Afternoon Track
4:30 PM – 4:55 PM
Panel Discussion – Afternoon Track
4:55 PM – 5:00 PM
5:00 PM – 6:15 PM
SOITEC IN BRIEF

Soitec plays a key role in the microelectronics industry. It designs and manufactures innovative semiconductor materials. These substrates are then patterned and cut into chips to make circuits for electronic components. Soitec offers unique and competitive solutions for miniaturizing chips, improving their performance and reducing their energy usage. 

Register Here


Get Ready for a Shakeout in Edge NPUs

Get Ready for a Shakeout in Edge NPUs
by Bernard Murphy on 11-20-2024 at 6:00 am

trackstar in a race min (1)

When the potential for AI at the edge first fired our imagination, semiconductor designers recognized that performance (and low power) required an accelerator and many decided to build their own. Requirements weren’t too complicated, commercial alternatives were limited and who wanted to add another royalty to further reduce margins? We saw NPUs popping up everywhere, in-house, in startups, and in extensions to commercial IP portfolios. We’re still in that mode but there are already signs that this free-for-all must come to an end, particularly for AI at the edge.

Accelerating software complexity

The flood of innovation around neural net architectures, AI models and foundation models, has been inescapable. For architectures from CNNs to DNNs, to RNNs and ultimately (so far) to transformers. For models in vision, audio/speech, in radar and lidar, and in large language models. For foundation models such as ChatGPT, Llama, and Gemini. The only certainty is that whatever you think is state-of-the-art today will have to be upgraded next year.

The operator/instruction set complexity required to support these models has also exploded. Where once a simple convolutional model might support <10 operators, now the ONNX standard supports 186 operators, and NPUs make allowance for extensions to this core set. Models today combine a mix of matrix/tensor, vector, and scalar operations, plus math operations (activation, softmax, etc). Supporting this range requires a software compiler to connect the underlying hardware to standard (reduced) network models. Add to that an instruction set simulator to validate and check performance against the target platform.

NPU providers must now commonly provide a ModelZoo of pre-proven/optimized models (CV, audio, etc) on their platforms, to allay cost of adoption/ownership concerns for buyers faced with this complexity.

Accelerating hardware complexity

Training platforms are now architecturally quite bounded, today mostly a question of whose GPU or TPU you want to use. The same cannot be said for inference platforms. Initially these were viewed somewhat as scaled-down versions of training platforms, mostly switching floats to fixed and more tightly quantizing word sizes. That view has now changed dramatically. Most of the hardware innovation today is happening in inference, especially for edge applications where there is significant pressure on competitive performance and power consumption.

In optimizing trained networks for edge deployment, a pruning step zeroes out parameters which have little impact on accuracy. Keeping in mind that some models today host billions of parameters, in theory zeroing such parameters can dramatically boost performance (and reduce power) because calculations around such cases can be skipped.

This “sparsity” enhancement works if the hardware runs one calculation at a time, but modern hardware exploits massive parallelism in systolic array accelerators for speed. However such accelerators can’t skip calculations scattered through the array. There are software and hardware workarounds to recapture benefits from pruning, but these are still evolving and unlikely to settle soon.

Convolutional networks, for many of us the start of modern AI, continue to be a very important component for feature extraction for example in many AI models, even in vision transformers (ViT). These networks can also run on systolic arrays but less efficiently than the regular matrix multiplication common in LLMs.  Finding ways to further accelerate convolution is a very hot topic of research.

Beyond these big acceleration challenges there are vector calculations such as activation and softmax which either require math calculations not supported in a standard systolic array, or which could maybe run on such an array but inefficiently since most of the array would sit idle in single row or column operations.

A common way to address this set of challenges is to combine a tensor engine (a systolic array), a vector engine (a DSP) and a scalar engine (a CPU), possibly in multiple clusters. The systolic array engine handles whatever operations it can serve best, handing off vector operations to the DSP, and everything else (including custom/math operations) is passed to the CPU.

Makes sense, but this solution requires a minimum of 3 compute engines. Product cost goes up both in die area and possibly royalties, power consumption goes up, and the programming and support model becomes more complex in managing, debugging, and updating software across these engines. You can understand why software developers would prefer to see all this complexity handled within a common NPU engine with a single programming model.

Growing supply chain/ecosystem complexity

Intermediate builders in the supply chain, a Bosch or a ThunderSoft for example, must build or at least tune models to be optimized for the end system application, considering say different lens options for cameras. They don’t have the time or the margin to accommodate a a wide range of different platforms. Their business realities will inevitably limit which NPUs they will be prepared to support.

A little further out but not far, software ecosystems are eager to grow around high-volume edge markets. One example is around software/models for earbuds and hearing aids in support of audio personalization. These value-add software companies will also gravitate around a small number of platforms they will be prepared to support.

Survival of the fittest is likely to play out even faster here than it did around a much earlier proliferation of CPU platforms. We still need competition between a few options, but the current Cambrian explosion of edge NPUs must come to an end fairly quickly, one way or another.

Also Read:

Tier1 Eye on Expanding Role in Automotive AI

A New Class of Accelerator Debuts

The Fallacy of Operator Fallback and the Future of Machine Learning Accelerators


The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 4 of 4)
by Lauro Rizzatti on 11-19-2024 at 10:00 am

Immensity of SW development Part 4 Table 1

The Impact of AI on Software and Hardware Development

Part 4 of this series analyzes how AI algorithmic processing is transforming software structures and significantly modifying processing hardware. It explores the marginalization of the traditional CPU architecture and demonstrates how software is increasingly dominating hardware. Additionally, it examines the impact of these changes on software development methodologies.

From “software eating the world” to “software consuming the hardware”

Energized by the exponential adoption of a multitude of AI applications, the software development landscape is on the brink of a paradigm shift, potentially mirroring the software revolution prophesied by venture capitalist Marc Andreessen in his seminal 2011 Wall Street Journal piece, “Why Software Is Eating The World”[1] (see Introduction in Part 1.) Strengthening this perspective is Microsoft co-founder Bill Gates’ belief in Generative AI’s (GenAI) transformative potential. He positions GenAI as the next paradigm-shifter, alongside the microprocessor, the personal computer, the internet and the mobile phone.[2]

The evolving landscape has given rise to an updated mantra: “Software is eating the world, hardware is feeding it, and data is driving it.”[3] Now, software is consuming the hardware. The outcome stems from the increasingly intertwined relationship between software and hardware. Software advancements not only drive innovation, but also redefine the very fabric of hardware design and functionality. As software becomes more complex, it pushes the boundaries of hardware, demanding ever-more powerful and specialized tools to drive its growth.

Traditional Software Applications versus AI Applications and the Impact on Processing Hardware

It is noteworthy to compare traditional software applications vis-à-vis AI applications to understand the evolving software and hardware scenarios.

Traditional Software Applications and CPU Processing

Traditional software applications are rule-based, captured in a sequence of pre-programmed instructions to be executed sequentially according to the intention of the software coder.

A Central-Processing-Unit (CPU) architecture – the dominating computing architecture since Von Neumann proposed it in 1945 – executes a traditional software program sequentially, in a linear fashion, one line after another, that dictates the speed of execution. To accelerate the execution, modern multi-core, multi-threading CPUs break down the entire sequence in multiple blocks of fewer instructions and process those blocks on the multi-cores and on the multi-threads in parallel.

Over the years, significant investments have been made to improve compiler technology, optimizing the partition of tasks into multiple independent blocks and threads to enhance execution speed. Yet nowadays the acceleration factor is not adequate to meet the processing power demands necessary for AI applications.

Significantly, when changes to traditional software programs are required, programmers must manually modify the code by replacing, adding or deleting instructions.

AI Software Applications and Hardware Acceleration

Unlike traditional software that follows a rigid script, AI applications harness the power of machine learning algorithms. These algorithms mimic the human brain’s structure by utilizing vast, interconnected networks of artificial neurons. While our brains evolved in millions of years and boast a staggering 86 billion neurons intricately linked, in the last decade, Artificial Neural Networks (ANNs) have grown exponentially from few neurons to hundreds of billions of neurons (artificial nodes) and connections (synapses).

For example, some of the largest neural networks used in deep learning models for tasks like natural language processing or image recognition may have hundreds of layers and billions of parameters. The exact number can vary depending on the specific architecture and application.

The complexity of an AI algorithm lies not in lines of code, but rather in the sheer number of neurons and associated parameters within its ANN. Modern AI algorithms can encompass hundreds of billions, even trillions, of these parameters. These parameters are processed using multidimensional matrix mathematics, employing integer or floating-point precision ranging from 4 bits to 64 bits. Though the underlying math involves basic multiplications and additions, these operations are replicated millions of times, and the complete set of parameters must be processed simultaneously during each clock cycle.

These powerful networks possess the ability to learn from vast datasets. By analyzing data, they can identify patterns and relationships, forming the foundation for Predictive AI, adept at solving problems and making data-driven forecasts, and Generative AI, focused on creating entirely new content.

AI software algorithms are inherently probabilistic. In other words, their responses carry a degree of uncertainty. As AI systems encounter new data, they continuously learn and refine their outputs, enabling them to adapt to evolving situations and improve response accuracy over time.

The computational demand for processing the latest generations of AI algorithms, such as transformers and large language models (LLMs), is measured in petaFLOPS (one petaFLOPS = 10^15 = 1,000,000,000,000,000 operations per second). CPUs, regardless of their core and thread count, are insufficient for these needs. Instead, AI accelerators—specialized hardware designed to significantly boost AI application performance—are at the forefront of development.

AI accelerators come in various forms, including GPUs, FPGAs, and custom-designed ASICs. These accelerators offer significant performance improvements over CPUs, resulting in faster execution times and greater scalability for managing increasingly complex AI applications. While a CPU can handle around a dozen threads simultaneously, GPUs can run millions of threads concurrently, significantly enhancing the performance of AI mathematical operations on massive vectors.

To provide higher parallel capabilities, GPUs allocate more transistors for data processing rather than data caching and flow control, whereas CPUs assign a significant portion of transistors for optimizing single-threaded performance and complex instruction execution. To date, the latest Nvidia’s Blackwell GPU includes 208 billion transistors, whereas Intel’s latest “Meteor Lake” CPU architecture contains up to 100 billion transistors.

The Bottom Line

In summary, traditional software applications fit deterministic scenarios dominated by predictability and reliability. These applications benefit from decades of refinement, are well-defined, and are relatively easy to modify when changes are needed. The hardware technology processing these applications are CPUs that perform at adequate speeds and excel in re-programmability and flexibility. Examples of traditional software programs include word processors, image and video editing tools, basic calculators, and video games with pre-defined rules. The profile of a traditional software developer typically requires skills in software engineering, including knowledge and expertise in one or more programming languages and experience in software development practices.

In contrast, AI software applications perfectly fit evolving, data-driven scenarios that require adaptability and learning from past experiences. The hardware technology managing AI applications encompasses vast numbers of highly parallel processing cores that deliver massive throughputs at the expense of considerable energy consumption. Examples of AI applications include facial recognition software (which improves with more faces), recommendation engines (which suggest products based on past purchases), and self-driving cars (which adapt to changing road conditions). The job requirements to become an AI algorithm engineer include a diversity of skills. Beyond specific programming abilities and software development practices, thorough understanding and extensive experience in data science and machine learning are critical.

Table I summarizes the main differences between traditional software applications versus an AI software application.

Software Stack Comparison: Traditional Software versus AI Algorithms

Traditional software applications, once completed and debugged, are ready for deployment. Conversely, AI algorithms require a fundamentally different approach: a two-stage development process known as training and inference.

Training Stage

In the training or learning stage, the algorithm is exposed to vast amounts of data. By processing this data, the algorithm “learns” to identify patterns and relationships within the data. Training can be a computationally intensive process, often taking weeks or even months depending on the complexity of the algorithm and the amount of data. The more data processed during training, the more refined and accurate the algorithm becomes.

Inference Stage

Once trained, the AI model is deployed in the inference stage for real-world use. During this phase, the algorithm applies what it has learned to new, unseen data, making predictions or decisions in real-time. Unlike traditional software, AI algorithms may continue to evolve and improve even after deployment, often requiring ongoing updates and retraining with new data to maintain or enhance performance.

This two-stage development process is reflected in the software stack for AI applications. The training stage often utilizes specialized hardware like GPUs (Graphics Processing Units) to handle the massive computational demands. The inference stage, however, may prioritize efficiency and resource optimization, potentially running on different hardware depending on the application.

AI software applications are built upon the core functionalities of a traditional software stack but necessitate additional blocks specific to AI capabilities. The main differences comprise:

  1. Data Management Tools: For collecting, cleaning, and preprocessing the large datasets required for training.
  2. Training Frameworks: Platforms such as TensorFlow, PyTorch, or Keras, which provide the infrastructure for building and training AI models.
  3. Monitoring and Maintenance Tools: Tools to monitor the performance of the deployed models, gather feedback, and manage updates or retraining as necessary.

Overall, the development and deployment of AI algorithms demand a continuous cycle of training and inference.

Validation of AI Software Applications: A Work-in-Progress

In traditional software, validation focuses on ensuring that the application meets expected functional requirements and operates correctly under defined conditions. This can be achieved through rigorous validation procedures that aim to cover all possible scenarios. Techniques like unit testing, integration testing, system testing, and acceptance testing are standard practices.

In contrast, validating AI software requires addressing not only functional correctness but also assessing the reliability of probabilistic outputs. It involves a combination of traditional testing methods with specialized techniques tailored to machine learning models. This includes cross-validation, validation on separate test sets, sensitivity analysis to input variations, adversarial testing to assess robustness, and fairness testing to detect biases in predictions. Moreover, continuous monitoring and validation are crucial due to the dynamic nature of AI models and data drift over time.

Risk Assessment

Risks in traditional software validation typically relate to functional errors, security vulnerabilities, and performance bottlenecks. These risks are generally more predictable and easier to mitigate through systematic testing and validation processes.

Risks in AI software validation extend beyond functional correctness to include ethical considerations (e.g., bias and fairness), interpretability (understanding how and why the model makes decisions), and compliance with regulations (such as data privacy laws). Managing these risks requires a comprehensive approach that addresses both technical aspects and broader societal impacts.

AI development is rapidly evolving, as these algorithmic models become more sophisticated, verification will become more challenging.

Implications for AI systems development

The suppliers of AI training and inference solutions falls into two main categories. Companies such as NVIDIA develop their own, publicly available programming language (CUDA) and develop faster, more scalable and more energy efficient execution hardware for general purpose use. Hyperscale companies such as Meta develop more specialized AI accelerators (MTIA) that are optimized for their specific workloads. Both require that the software layers and the underlying hardware are optimized for maximum performance and lower energy consumption. These metrics need to be measured pre-silicon, as the AI architecture optimization – as opposed to the traditional Von Neumann architecture – is of central importance for success. Large companies such as NVIDIA and Meta, as well as startup companies such as Rebellions rely on hardware-assisted solutions with the highest performance to accomplish this optimization.

In Conclusion:

The widespread adoption of AI across a variety of industries, from facial/image recognition and natural language processing all the way to self-driving vehicles and generative AI elaboration, is transforming how we live and work. This revolution has ignited a dual wave of innovations. On the hardware side, it is thrusting a massive demand for faster and more efficient AI processing. On the software side, it is driving the creation of ever more complex, and sophisticated AI applications.

While traditional software excels at well-defined tasks with clearly defined rules, AI applications are ideally suited for situations that demand adaptation, learning from data, and handling complex, unstructured information. The evolving nature of AI software presents a new challenge in validation that existing methods are not fully equipped to address. A new wave of innovation in software validation is necessary, opening new opportunities to the software automation industry.

[1] https://www.wsj.com/articles/SB10001424053111903480904576512250915629460

[2] https://www.gatesnotes.com/The-Age-of-AI-Has-Begun.

[3] The quote “Software is eating the world, hardware is feeding it, and data is driving it” is attributed to Peter Levine, a venture capitalist at Andreessen Horowitz, who used it to encapsulate the transformative impact of software, hardware, and data on various industries and aspects of our lives.

Also Read:

The Immensity of Software Development the Challenges of Debugging (Part 1 of 4)

The Immensity of Software Development and the Challenges of Debugging Series (Part 2 of 4)

The Immensity of Software Development and the Challenges of Debugging (Part 3 of 4)


Alchip is Paving the Way to Future 3D Design Innovation

Alchip is Paving the Way to Future 3D Design Innovation
by Mike Gianfagna on 11-19-2024 at 6:00 am

Alchip is Paving the Way to Future 3D Design Innovation

At the recent TSMC OIP Ecosystem Forum in Santa Clara, there was an important presentation that laid the groundwork for a great deal of future innovation. Alchip and its IP and EDA partner Synopsys presented Efficient 3D Chiplet Stacking Using TSMC SoIC. The concept of 3D, chiplet-based design certainly isn’t new. SemiWiki maintains dedicated forums on both Chiplets and 3D IC. There is a lot of buzz on both topics.

And TSMC’s SoIC initiative provides the manufacturing infrastructure and technical support to achieve next-generation innovation. Indeed, all the elements needed for 3D chiplet-based design are taking shape. It has been said that the devil is in the details. And the details and technical challenges to be overcome as we move to a new chapter in semiconductors are daunting. Meaningful progress to reduce these challenges is quite important, and that progress was on full display at the Alchip presentation. Let’s examine how Alchip is paving the way to future 3D design innovation.

Alchip at TSMC OIP

Erez Shaizaf

The presenter from Alchip was Erez Shaizaf, Alchip’s Chief Technical Officer. Erez has been with Alchip for the past two years. He has a long career in semiconductors with companies such as Freescale, EZchip, Mellanox, and Xsight Labs. Erez discussed how Alchip, working with Synopsys and TSMC, has overcome several significant challenges for 3D IC design in the areas of electrical, power, thermal and mechanical design.

Erez described the kind of 3D architecture being addressed as one that contains top dies in advanced nodes (e.g., high-frequency CPU) and bottom dies in older nodes (e.g., memory subsystems). A coherent fabric connects the two layers with an Alchip Micro 3D liteIO PHY interface. Fine pitch hybrid bonding and fine pitch TSVs create high bandwidth interconnect and efficient power delivery between the top and bottom dies. The figure below illustrates this 3DIC folded CPU use case.

Erez also discussed several power delivery challenges, including:

  • Power Integrity Challenges
    • Static and dynamic IR drop
    • Power noise propagation from bottom to top die and vice versa
    • Different power domains among top and bottom dies and a shared ground plane
  • Power Grid Design
    • TSV distribution
    • B distribution
    • PDN design
  • Power Integrity Simulation and Signoff
    • Early analysis (prior to place & route)
    • Early simulation (after place & route)
    • Signoff

The paper also described a sophisticated TSV distribution strategy that uses non-uniform and location-dependent TSV arrays. Using this approach, TSV density is determined by local power density for bottom and top die shared and non-shared power delivery networks (PDNs).  Erez detailed the pros and cons of shared vs. non-shared PDNs. He explained that non-uniform TSV density schemes are friendly to automated place & route. The TSV patterns are compatible with Alchip’s multiple 3D-liteIO micro-PHY P&R and TSMC design rules.

Erez also talked about how to do early PDN analysis and the benefits that result. He also discussed how to achieve 3D data and clock design targets and details of an H-tree strategy for 3DIC clocking. 3DIC thermal characterization challenges and solutions were also presented, along with a set of verification strategies aimed at 3DIC design.

Abhijeet Chakraborty

Abhijeet Chakraborty, Vice President Engineering at Synopsys, followed Erez to the podium. Abhijeet has been with Synopsys more than 18 years. He described how the Synopsys 3DIC Compiler delivers a unified exploration-to-signoff platform. The benefits of this platform include:

  • Extending 2D fusion platform (Fusion Compiler) for 3D heterogenous integration (3DHI) and advanced packaging
  • Delivering a unified environment that supports 3D design exploration, planning, implementation and verification
  • Integrating the golden signoff solutions from Synopsys and Ansys for 3D STA, EM/IR, SI/PI/TI, EMAG
  • Providing full support for TSMC technologies including CoWoS, SOIC, and 3Dblox

Overall, Abhijeet explained that Synopsys and Alchip are collaborating on HPC/AI-optimized physical design for advanced nodes, IP and multi-die packaging. The graphic at the top of this post provides a high-level summary of how Synopsys and Alchip are enabling 3DIC design success.

The Implications of This Work

I had a chance to speak with Erez Shaizaf after the presentation. He gave me some perspective on the implications of the work presented. In a word, it’s transformative.

Erez explained that up to now, most multi-die designs consisted of active devices, like AI accelerators and some HBM memory stacks over passive devices, like caps and interconnect supplied by the interposer. The work presented at OIP opens the possibility for multiple active devices in the stack to come from different technology nodes. He predicted these new options will change the designer’s mindset and system design will take on new meaning.

He explained that the ability to integrate multiple active devices in a true 3D stack with multiple process nodes opens many new options for system architecture and integration. One benefit of this approach is partitioning a subsystem from one large die to multiple smaller dies. This delivers a yield and cost benefit. There are many more examples of how a more unconstrained 3D design flow can change the game.

He pointed out that the yield, thermal, mechanical and power delivery aspects of true multi-dimensional system design are substantial. The way design will be done will change as well. But the opportunities for true system innovation make it all worthwhile.

Erez concluded by saying that Alchip and Synopsys are breaking down the barriers to this new design paradigm. Along with TSMC, they are bringing new opportunities for innovation within reach, and that makes for an exciting future.

To Learn More

You can find out more about the TSMC Global OIP Ecosystem Forum here.  If you are considering the benefits of 3DIC design, you will want to learn more about how Alchip can help. You can access more information about Alchip here. Even better, you can reach out to the company to discuss your future design needs here. And that’s how Alchip is paving the way to future 3D design innovation.


Handling Objections in UVM Code

Handling Objections in UVM Code
by Daniel Payne on 11-18-2024 at 10:00 am

expanded view min

You begin writing some UVM code and there are parts of the code that aren’t done yet, so you begin to use uvm_objection, guarding that code. Rich Edelman, a product engineer at Siemens doing verification debug and analysis, wrote a paper on this topic, which I just read. This blog covers the topic of objections and provides some different approaches.

UVM is founded on processes, and processes can be synchronized automatically or by design during phases. We typically raise an objection, then later on drop the objection during a phase.

Here’s a UVM example using a raised objection to make sure that simulation doesn’t exit until a drop exception happens.

The source code of has over 1,000 lines of code, so it’s recommended to use objections once in a test. Consider a UVM test with four sequences, using raise_objection and drop_objection.

Each of the four environments (e1 – e4) call raise_objection and drop_objection, which is not so efficient.

A simpler objection in UVM is the uvm_barrier.svh, at just 240 lines, but we can define our own barrier function with even fewer lines like this:

This barrier code uses a count to pass the barrier. When the count reaches 0 after a drop, it exits.

Another approach to synchronization is using names like start, middle, and end.

 

This wrapper creates the barrier class if needed, and uses three names: raise, drop, and get.

The next example shows a class and a module, where there are two class instances and three Verilog modules. Three phases are synchronized across the modules and class instances: start, middle, and end. The objects simulate in each phase for some time, then drop the objection. After all objects have dropped, processing continues.

Running this example shows that each object reports after “drop” has returned, then each object moves forward.

Both Class1 and Class2 are SystemVerilog class handles, while A, B, and C are the Verilog module instances. Each of the objects in each phase waits until the next barrier completes, which is our synchronization goal.

Below are visualizations: the “middle” phase and the workload for each object. Each phase—here the middle phase—displays each object: “class1,” “B,” “A,” “class2” and “C,” in order, along with the payload for each object.

This view shows many phase begins and ends, all synchronized.

The expanded view provides details of the objects and payloads in each phase.

Objections and phasing are linked together, so use objections with phasing while limiting their usage to be more efficient. One way to create phasing is through a barrier like uvm_barrier, or using the examples presented. You can solve synchronization with your own code. Adding too many raise_objection and drop_objection pairs in your code will only slow down simulation times.

Summary

Yes, continue to use uvm_objection in your UVM code, being careful to not slow down run times by calling it too often. Alternative approaches were shared in this blog that require less code, are more intuitive, and run quicker.

Read the complete 15 page paper online.

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GaN HEMT modeling with ANN parameters targets extensibility

GaN HEMT modeling with ANN parameters targets extensibility
by Don Dingee on 11-18-2024 at 6:00 am

Modified ASM HEMT equivalent circuit for GaN HEMT modeling with ANN parameters

Designers choosing gallium nitride (GaN) transistors may face a surprising challenge when putting the devices in their context. While the Advanced SPICE Model for GaN HEMTs (ASM-HEMT) model captures many behaviors like thermal and trapping effects, it grapples with accuracy over a wide range of bias conditions. Foundries often define ASM-HEMT parameters from measurements at a specific bias point but don’t solve for different bias values. Keysight device modeling researchers are exploring an improved ASM-HEMT hybrid model, blending measurements with physics and using artificial neural network (ANN) techniques for improving wide-range S-parameter fit in minutes. We spoke with Rafael Perez Martinez, R&D Software Engineer in the R&D Device Modeling group at Keysight EDA, about this new approach to GaN HEMT modeling with ANN parameters.

A choice between lengthy measurements or less-than-accurate simulations

Perez Martinez began his exploration of GaN HEMT modeling at Stanford University, working on his PhD in the Wide-Bandgap Lab (WBGL). “I had an idea in 2022 looking at prior ASM-HEMT publications. It seemed like people weren’t reporting CV characteristics fitting, and they tended to fit the model at one drain voltage bias,” he says. “Measurements are tedious, and measurement-based models such as DynaFET require extensive DC and S-parameter data and large-signal non-linear vector network analyzer (NVNA) measurements that can take one to three months to set up and execute.” Physics-based theoretical models like ASM-HEMT can readily simulate and extend S-parameter predictions across frequency ranges but tend to inaccurately fit parameters at varying bias voltages.

Additionally, many university labs and start-ups don’t have budgets for an NVNA or similar instruments and accessories for GaN HEMT measurements. Perez Martinez parlayed his summer internships at Keysight into a WBGL proposal for grant funding for a Keysight PNA-X, which arrived at the lab in 2023. With coaching from Keysight teams, Perez Martinez dove in, taking PNA-X readings on a 150nm gate length GaN-on-SiC HEMT and capturing its non-linear characteristics. Plugging the measured parameters as-is into a standard ASM-HEMT model highlighted the disparity between the two approaches. The S-parameter fitting performs poorly with VD=5 to 25 V, VG=-3 to -1V, and f = 250MHz to 50GHz (measurements in red, simulations in blue).

Moving to hybrid GaN HEMT modeling with ANN parameters

This persistent mismatch between measurements and simulation gave Perez Martinez the idea of developing a hybrid model example, combining the baseline of a measurement-based model with the extensibility and speed of physics-based modeling. “I had GaN HEMT measurements at 10 GHz with second and third harmonics,” he says. “But starting the hybrid model was difficult initially because you need to know the device model, go through the Verilog code, know what to change – and you can’t just add things randomly. There has to be some physical aspect of any change that makes sense.”

With measurements in the 10 GHz region where the model should be most accurate, Perez Martinez moved into Keysight IC-CAP for modeling with its ANN Modeling Toolkit. “Integrating a neural network into the Verilog model is quite trivial using the ANN toolkit,” continues Perez Martinez. “Looking at some earlier small-signal models, I noticed the ASM-HEMT model was missing something around gate-drain resistance, so that’s where I started, working carefully not to fix one problem and break something else.” A few cycles of replacing parameters with ANN variables and using the IC-CAP optimizer added two resistances and three capacitances to the ASM-HEMT equivalent circuit (inside the dotted pink outlines).

Generalizing results from ANN parameter fitting

A Keysight ADS simulation with hybrid ANN parameters from IC-CAP aligns very closely with measurements, as indicated by the near-perfect overlap between the red lines and the dotted pink lines in this comparison of power-added efficiency, gain versus Pout, and dynamic load lines. In this case, the model modification solves the problem of simulating wide-range bias.

The logical follow-up to this result: are these results device-specific, or will the methodology scale to smaller geometries and higher frequencies? “The first challenge is getting measurements at higher frequencies, which takes access to instrumentation, plus time and care,” observes Perez Martinez. “The next challenge is not every GaN HEMT has the same physical device structure, and people tend to play tricks – maybe the distance between the drain and gate varies, maybe there’s a different field plate, or maybe the gate structure has a different shape.” The implication is that one model may not fit all devices. However, the ANN approach in IC-CAP works with any device model and helps narrow down where modifications can improve and speed up S-parameter fitting – in a matter of hours versus months of measurements.

That’s an important observation since Perez Martinez is not necessarily looking for a formal ASM-HEMT model update. He’s presenting his paper at the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) to raise awareness and generate discussion around the approach. “People always talk about positive results in papers, but rarely do they talk about the failures it took to get there,” says Perez Martinez. “This is really a look at some GaN HEMT model shortcomings we’ve seen, and a hybrid model example in IC-CAP with ANN that we’d like people to look at that might fit their needs.”

To see more details about the methodology for GaN HEMT modeling with ANN parameters and the results, see the BCICTS 2024 paper in the  BCICTS proceedings archive:

A Hybrid Physical ASM-HEMT Model Using a Neural Network-Based Methodology

Also, see more information on the latest in GaN device modeling from Keysight experts:

Electronic Design webinar:   Mastering GaN Device Modeling

Keysight:   Device Modeling IC-CAP   |   W7009E PathWave IC-CAP ANN Modeling Toolkit

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Keysight EDA 2025 launches AI-enhanced design workflows

Webinar: When Failure in Silicon Is Not an Option

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