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Semiconductor Expert Forum

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Perforce at the 2024 Design Automation Conference

Perforce at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 6:00 pm
Categories: EDA, Events, Perforce

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Perforce powers innovation at unrivaled scale. Perforce solutions future-proof competitive advantage by driving quality, security, compliance, collaboration, and speed – across the technology lifecycle. We bring deep domain and vertical expertise to every customer, so nothing stands in the way of success. Our global footprint spans more than 80 countries and includes over 75% of the Fortune 100. Perforce is trusted by the world’s leading brands to deliver solutions to even the toughest challenges. Accelerate technology delivery, with no shortcuts. Get the Power of Perforce.

Visit Perforce At Booth #1421 in the Exhibit Hall

Visit the Perforce booth, #1421 in the Exhibit Hall, to get a demo of our latest enhancements and chat with our experts about how Perforce semiconductor solutions can help solve your biggest chip design challenges. While you’re there, play PLINKO and win some fresh Perforce swag. Plus, scan your badge for a chance to win a TheraGun.

Stop By For Happy Hour

On Tuesday, June 25, we’ll be hosting a happy hour at Perforce booth #1421 from 3 to 5 p.m. Stop by with questions, network, and enjoy some drinks on Perforce.

Don’t Miss This Presentation

Perforce VP of Solutions Engineering, Vishal Moondhra, will be presenting on “The Transformation Model for IP-Centric Design: A Blueprint for Improving IP Reuse, End-To-End Traceability, and Collaboration at Enterprise Scale.”

Attend this session to learn how transitioning to an IP-centric design methodology allows organizations to achieve the goal of a streamlined, fully traceable, horizontally scaling, single source of truth for all design management needs across hardware, firmware, and software projects and platforms. The benefits include improved collaboration, accelerated design, more informed build vs. buy decisions, and a streamlining of efforts across design teams.

This session will be held on Tuesday, June 25 at 11:15–11:45 a.m at the Exhibitor Forum Stage.

Skip the Line – Schedule a Meeting

Want to learn more about Perforce solutions for IP and design data management? DAC attendees can skip the line and schedule a meeting or demo with Perforce staff on their website here: Book a Meeting

Meeting times are available Monday, June 24 through Wednesday, June 26 at our booth.

Find More Resources

Visit our DAC event page for information about Perforce at DAC. Learn why 9 of the 10 top semiconductor companies use Perforce. Plus, find more semiconductor and SoC resources, including information on Perforce solutions, whitepapers on IP-Centric Design and supercharging embedded development with modern data management, and more: Perforce at DAC.

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LIVE WEBINAR: Automating the Integration Workflow with IP Centric Design

2024 Outlook with Adam Olson of Perforce

The Transformation Model for IP-Centric Design

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Applied Materials at the 2024 Design Automation Conference

Applied Materials at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 4:00 pm
Categories: EDA, Events

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What is Applied Materials doing in an EDA trade show?
New semiconductor market segments such as AI, automotive and connected devices are growing at an accelerated pace and placing constant increased pressures on the PPAC (power, performance, area, cost) system requirements. In the past, these growing PPAC demands were addressed by scaling down feature geometries and cost per transistor at a predictable pace, known as Moore’s law. But in recent years, geometry scaling has slowed down around 7nm technology geometry to a point that it cannot keep up with the pace of growing PPAC demands, requiring new approaches and innovations.

Today’s technologies are already at atomic levels and there is no single technology breakthrough we can rely on. We need to explore multiple innovative solutions across the entire semiconductor technology chain and holistically evaluate from the system level, chip design architecture, IP design and circuit design, devices, and interconnect to the fabrication processes and materials that this entire chain is founded upon.

PPAC à PPACt

Applied Materials has already identified these challenges a few years ago and has implemented a corporate-wide effort to address them in an integrative manner that explores potential innovative solutions at different levels. Solutions include new material innovations, processing techniques, new device structures, power delivery schemes, interconnect structures, circuit, foundation IP, chip design, and packaging, all the way to the system level. Multiple combinations of these innovations can be modeled and evaluated at each level. Applied’s goal in this effort is to find and develop new solutions with optimized PPAC for each market segment or application. Furthermore, Applied recognizes the importance of bringing these solutions to the market quickly and added a time-to-market dimension changing PPAC to PPACt.

System To Materials (STM) Group

The STM group at Applied is an essential part of this corporate-wide effort. STM has developed technologies and methodologies to identify system level challenges and bottlenecks through innovative solutions at all levels of the value chain. These innovations are accurately modeled through a complete design flow from materials to system level.

STM DAC Exhibit

STM engagements with the design and EDA community are important to understand and address the current industry challenges. At 2024 DAC, learn about the following products and services that are commercially offered by STM at exhibit booth #1522 (under “Sage Design Automation” which is a part of the STM group).

SLiCTM:  Standardcell Library Compiler

SLiC generates the highest quality standard cells at a fraction of time and effort compared to traditional methods. SLiC’s technology flexibility and quick setup time can accelerate DTCO pathfinding effort from months to weeks.  SLiC high throughput and optimized results enable generation of a complete production level logic library overnight. SLiC supports state of the art technologies from 7nm to 1.4nm, including CFET stacked devices.

iDRMTM:  integrated Design Rule Management system

iDRM is a tool to develop, manage and enable correct-by-construction design rule development with clear rule description and automate creation of error-free DRC decks for third party DRC tools. iDRM’s powerful GUI helps to view and edit design rules, as well as check and verify design rule intent.

DRVerifyTM:  DRC Deck QA and Verification

DRVerify checks and verifies DRC decks to make sure they are complete, correct and error-free. DRVerify automatically creates pass/fail test cases from design rule descriptions, runs the tested DRC deck on these test cases, scans DRC markers, compares to the golden rule intent and highlights any possible errors or mismatch.

Ginestra®: Materials-to-Device Optimizer

Ginestra is a material centric simulation platform which links process material properties (composition, stoichiometry, atomic-defects) to device performances and reliability.  Ginestra integrates relevant physics critical to understanding and managing the complexity of materials-to-device co-optimization from materials discovery through device performance, reliability and variability projection. Ginestra’s design and simulation platform accelerates materials-to-device innovation, providing atomic level insights to improve performance, power, area, cost and time to market.

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Ansys and NVIDIA Collaboration Will Be On Display at DAC 2024

Arteris at the 2024 Design Automation Conference

EasyLogic at the 2024 Design Automation Conference

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Ansys and NVIDIA Collaboration Will Be On Display at DAC 2024

Ansys and NVIDIA Collaboration Will Be On Display at DAC 2024
by Daniel Nenni on 06-18-2024 at 2:00 pm
Categories: Ansys, Inc., EDA, Events

DAC 2024 Banner


Highlights:

In less than two weeks the 2024 Design Automation Conference and Exhibit will start on June 23rd  in San Francisco. Ansys will be showcasing its 3DIC Multiphysics solutions together with NVIDIA in the Ansys booth where Ansys solutions will be shown running natively on NVIDIA GPU hardware.

More collaboration with NVIDIA will be on show at the DAC Exhibitor Forum sessions sponsored by Ansys every day from 1:45pm – 3:00pm:

One of the most difficult challenges for IC designers today is power integrity signoff at advanced nodes and how to achieve comprehensive dynamic voltage drop (DVD) coverage. Attend this session to learn how leading IC design teams no longer rely only on traditional vectored/vectorless analysis but are adopting a radical new SigmaDVD™ technology from Ansys to address urgent DVD issues at advanced nodes . SigmaDVD is becoming the leading method for avoiding DVD voltage and timing problems, shift-left prevention of voltage-drop issues, fixing IR violations, and achieving robust, high-coverage power integrity signoff.

AI/ML is causing sweeping changes in almost every industry, and electronic design and simulation are no exceptions. EDA tools have a long history of using heuristics and numerical approximations to ensure designer productivity keeps pace with Moore’s Law. This session will feature Ansys CTO Prith Banerjee joined by industry speakers to discuss today’s practical application of AI/ML for electronic design and simulation, and how this trend will determine the direction of EDA in the future.

Ansys and NVIDIA collaborate closely to enable designers to bring a new paradigm to IC design: Visualizing and optimizing multi-die designs with NVIDIA’s  Omniverse technology. In combination with Ansys electromagnetic, thermal, and mechanical simulation it can provide capabilities never before seen in IC design. This session features representatives from Ansys and NVIDIA demonstrating Ansys solutions operating with NVIDIA’s Omniverse for practical optimization solutions. The session will also cover key aspects of the companies’ collaborations on AI and GPU design and enablement, as debuted in Jensen Huang’s GTC 2024 keynote.

Ansys’ chief technology officer, Prith Banerjee, will be sharing his insights with the DAC Research panel “Why Is EDA Playing Catchup to Disruptive Technologies Like AI?” on Wednesday at 11:30am.

The Ansys 40×40 booth (#1308) is one of the larger ones in this year’s Exhibit, with its major theme of 3DIC Multiphysics simulation and signoff. NVIDIA will be participating in the Ansys booth with a demonstration of its GPU hardware running Ansys simulations solutions. Customers can also register to attend a series of 6 technical Customer Workshops in the Ansys booth where Ansys customers present detailed technical summaries of their experiences and successes in applying Ansys technology for their production IC designs.

Ansys will be presenting in the Intel Foundry booth on support for Intel 18A and advanced backside power delivery technology. Ansys will also present in the Microsoft booth on the cloud-enablement collaboration with Azure to optimize compute times and costs for designing large AI/ML, HPC, networking , and automotive designs.

The impressively broad usage of Ansys products across the semiconductor industry has once again enabled Ansys customers to submit an equally impressive 24 technical papers that have been accepted by the DAC Conference and will be presented in the Engineering Track.

So please make sure to register to attend the conference and join Ansys at DAC. Register for one of our exclusive events or schedule a meeting as we reach out to our customers and partners in advancing the state-of-the-art in Electronic Design Automation.

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Simulation World 2024 Virtual Event

2024 Outlook with John Lee, VP and GM Electronics, Semiconductor and Optics Business Unit at Ansys

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IC Manage at the 2024 Design Automation Conference

IC Manage at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 12:00 pm
Categories: EDA, Events, IC Manage

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DAC in San Francisco will once again be a can’t miss event for semiconductor professionals seeking to discover the latest developments in EDA solutions that address the wide range of issues encountered in delivering high quality IC products and electronics systems to the market. IC Manage will be exhibiting its latest innovations from its Global Design Platform, IP Central and Holodeck products that address the growing complexities of design management and data explosion that come along with advanced technology nodes that are enabling today’s cutting edge designs in AI, SoC and high performance analog products.

In the realm of design data management, the IC Manage applications team will be showing the latest GDP-XL features that deliver high performance configuration and release management that scale to 1000s of users managing and tracking millions of IP components and design variations. Other new developments extend customization features that enable customers to adapt to new workflows and usage models without complex programming or major software upgrades. Additionally, the new Time machine feature allows full traceability of design and configuration changes as well as comparison of any 2 design states & recovery of previous design states.

GDP-XL support for Git based version control has also been extended and IC Manage will be demonstrating integration with popular Git environments like Gitlab and how to reliably manage 1000’s of Git repos and release states in building complex SoCs.

IP Central has also evolved and the IC Manage team will be showing how to capture IP components and manage their lifecycle along with the customization features that enable user-configurable search pages and automatically generated and searchable IP datasheets. Integration methods with external systems like Jira for bug tracking will also be covered that are essential in delivering a full IP Asset management environment that allows data sharing across any number of enterprise reporting systems.

Helping IC design teams to leverage Cloud computing or to accelerate their internal data center performance, the Holodeck team will be showing “how to” demos of instant cloud bursting of popular EDA tools like Ansys Redhawk, Verilog simulation, Cadence Virtuoso and Siemens EDA Calibre. Holodeck’s key benefits for EDA tool performance acceleration and storage cost reduction results will also be discussed. Holodeck can deliver elastic computing which requires a a true scaleout storage I/O architecture to be able to deliver high I/O performance across 1000s of compute nodes without having to pre-copy data to the cloud or remote data centers.

For more information, please visit https://www.icmanage.com or to sign up for a DAC demo session please click HERE.

About IC Manage
IC Manage provides hybrid cloud and high-performance design management solutions for companies to efficiently collaborate on design and verification across their global enterprises, while maximizing their IP reuse. IC Manage customers include AMD, Infineon, Microchip, Qualcomm, NVIDIA, Samsung and other top semiconductor and systems companies. IC Manage is based in Campbell, CA, with additional offices throughout the U.S., Asia, and Europe. For more information visit us at www.icmanage.com.

Also Read:

WEBINAR: How to Accelerate Ansys RedHawk-SC in the Cloud

Effectively Managing Large IP Portfolios For Complex SoC Projects

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Mirabilis Design at the 2024 Design Automation Conference

Mirabilis Design at the 2024 Design Automation Conference
by Deepak Shankar on 06-18-2024 at 10:00 am
Categories: AI, Chiplet, Events, IP, Mirabilis Design, RISC-V

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This is the first time in 28 years of my visits to DAC that I have seen so many different technologies arrive at DAC in the same year.  Earlier we would have one or possibly two innovative breakthroughs in semiconductors and embedded systems that emerged at DAC. This year I expect six or may be seven to arrive, and I am not including the innovations in EDA software.

At the system-level, new architectures are propelling the need for a shift-left methodology that integrates system-level analysis and exploration, architecture trade-offs, communication with partners and requirements monitoring. Trending technologies include multi-die and Chiplets, RISC-V and ARM co-habiting, power and thermal challenges leading to more complex power management architectures, AI engines vs. GPU for vector and convolution, common architecture for all EV automobiles, micro-assurance experiments, and latency analysis of analog systems.

In the post-Covid era, Mirabilis Design has recognized the emergence of these trends.  To support these trends, we have introduced the concept of validated system-level IP and capabilities on top of performance models.  System-level IP blocks to support Chiplets/UCIe, PCIe6.0, LPDDR_5X, DDR5, DSP, GPU, AI Engines, NoCs, and DSP have been added to the flagship VisualSim Architect. Requirements can be imported from a variety of database and is fully integrated with the simulator, that provides continuous monitoring.  Other new features include thermal characteristics from the power modeling of a cycle-accurate performance model, AI workloads such as DNN partitioning on to AI/GPU/CPU, failures modeling and generation of UPF/UVM/SystemVerilog files for early verification.

We are witnessing a spurt in interest by semiconductor and automotive design communities in exploring the revamped version of VisualSim.  We strongly believe this trend will expand further as more and more designs require AI engines and devices becoming power hungry leading to an increase in thermal cost.

Chiplets have been recognized as the right choice of solution as a rapid response to new customer requirements.  Building a stock/base of different configurations that can be easily assembled for a new application is essential.  The VisualSim model of the application architecture enables a new market for chiplet IP vendors and semiconductor companies. Both can collaborate to create a solution that is optimized for the target application and workload to meet the Power-Performance-Area.  VisualSim hardware builders have been proven to create a new generation of SoC in about 2 weeks, thus enabling rapid trade-off, and dynamic documentation for distribution to OEMs and suppliers.

Power has become extremely important in both traditional processors and emerging applications such as AI, GPU, automotive architecture.  VisualSim Power Digital Twin has been built on top of the VisualSim performance model.  The design can incorporate power management, large number of states, dynamic and leakage, distribution and attenuation, negative impact of power management, batteries, and power generators such as solar panels. The models provides instantaneous and average power plots, power improvement for a new power management architecture, output thermal characteristics for temperature and heat, power for workloads and individual IP and generate SystemVerilog test benches and UPF files.

Inspite of the fact that the large vendors of the EDA industry are missing, I believe it will still be an important one for both the electronics engineers and the EDA companies supporting them.

Website: https://www.mirabilisdesign.com

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Chiplets Open Pandora’s Box

Mapping SysML to Hardware Architecture

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PrimisAI at the 2024 Design Automation Conference

PrimisAI at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 8:00 am
Categories: AI, EDA, Events

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PrimisAI is the premier destination for cutting-edge hardware design automation, offering engineers the ultimate companion with advanced Language-to-Code and Language-to-Verification capabilities. Our interactive AI assistant swiftly addresses complex hardware challenges across the entire design stack, from concept to Bitstream/GDSII. With on-premise deployment and an easily extendable knowledge base tailored to client-specific IPs, PrimisAI ensures an unparalleled hardware design experience.

We are excited to announce our participation in DAC 2024, marking our first attendance at this premier event. At DAC, we will showcase the transformative capabilities of our product, RapidGPT, which is revolutionizing AI-driven EDA.

RapidGPT is a groundbreaking generative AI-based tool and a game-changer in the field of hardware engineering. This innovative solution empowers hardware designers with a natural language interface, enhancing productivity, accelerating time-to-market, and transcending traditional automation. Designed specifically for FPGA engineers, RapidGPT offers a more intuitive interaction for the entire design journey, guiding hardware engineers from concept to implementation.

Key Features of RapidGPT:
1. Intelligent Code Assistant: RapidGPT leverages advanced AI algorithms to provide accurate, context-aware code suggestions, allowing FPGA engineers to write Verilog code more efficiently. It understands your intent and converts it into complete HDL code. Simply describe your desired functionality, and RapidGPT delivers the corresponding code, saving time and effort.

2. Conversational Capabilities: RapidGPT features a user-friendly chat panel for easy communication, enabling users to write or improve HDL code conversationally. Whether you need assistance with a specific design element or want to explore different options, RapidGPT is here to help.

3. Contextual Suggestions: RapidGPT provides intelligent, context-aware suggestions as you write code. It analyzes your code snippets and offers helpful suggestions for completion or optimization, considering your specific design requirements and industry best practices.

4. Code Optimization: RapidGPT detects potential errors and inconsistencies in your code, helping you catch and fix issues early in the design process. This feature improves the reliability of your designs and streamlines the development process, reducing time- to-market and enhancing overall productivity.

We invite you to visit us at DAC 2024 to explore the innovative capabilities of RapidGPT and discover how PrimisAI can help drive your success. Meet our experts at booth #1344 to see live demonstrations, discuss your specific needs, and learn about the latest advancements in AI technology. You can also schedule a personalized consultation to delve deeper into how RapidGPT can be tailored to your unique challenges and opportunities.

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Silicon Creations at the 2024 Design Automation Conference

Silicon Creations at the 2024 Design Automation Conference
by Daniel Nenni on 06-18-2024 at 6:00 am
Categories: Events, IP, Silicon Creations

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Silicon Creations is a self-funded, leading silicon IP provider with development in the US and Poland, and a sales presence worldwide. The company provides world-class IP for precision and general-purpose timing (PLLs), oscillators, low-power, high-performance multi-protocol and targeted SerDes, and high-speed differential I/Os. Applications include smart phones, wearables, consumer devices, processors, network devices, automotive, IoT, and medical devices.

The majority of the world’s top 50 IC companies work with Silicon Creations. 1,000+ chips contain the company’s IP using over 700 unique IP products. Silicon Creations touches over 150 production tape-outs each year with over 400 customers, with 3nm designs in mass production.

This year they are celebrating surpassing 10 million wafers in production in collaboration with TSMC, the world’s largest dedicated independent semiconductor foundry. This achievement – which includes designs from 180nm through 3nm nodes – underscores the breadth and impact of Silicon Creations’ contributions to the semiconductor industry. There are now approximately 10 billion chips with Silicon Creations IP manufactured by TSMC worldwide.

This year at DAC they will be highlighting a large portfolio of PLLs and supporting clocking IP including our highly digital, jitter optimized LC PLL. Stop by DAC booth #2325 to learn about our full line-up of high-performance IP and pick up a Silicon Creations wafer coaster.

Catch one (or both!) of their presentations at the following partner booths:
Intel Foundry (booth #2337) June 24, Mon, 3-3.20pm Clocking Solutions for Intel Foundry Advanced Process Nodes

Siemens (booth #2521)
June 24, Mon, 4-4.30pm
PLL Design and Simulation using Solido SPICE

You can see the full line of high-performance IP available from Silicon Creations here. If you would like to reach out to the company to learn more, you can do that here.

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Truechip at the 2024 Design Automation Conference

Truechip at the 2024 Design Automation Conference
by Admin on 06-17-2024 at 6:00 pm
Categories: Events, IP, Truechip

DAC 2024 Banner

We are excited to announce that Truechip, a leading provider of Verification IP solutions, will be actively participating at DAC 2024, taking place from June 23-25 at Moscone West, San Francisco, CA. This event is a pivotal gathering for professionals in the verification industry, and Truechip’s presence will be a highlight for attendees interested in state-of-the-art verification technologies.

Visit us at our booth 2343 on Level 2 in the exhibition hall where our team will showcase the latest advancements in Verification IP and the NOC Silicon IP. Explore our comprehensive portfolio of products designed to meet the evolving needs of the industry. Engage with our experts to learn how Truechip’s solutions can enhance your verification processes and improve efficiency.

The VIP protocols that are developed by the company are exhaustive and consist of protocols families like Bus, Interface, MIPI, Automotive, USB, Networking, Storage, AMBA, PCIe, Memory, Display, RISC V, Defense and Avionics with some of the distinguished protocols such as PCIE Gen 6, UCIE,APHY, Ethernet 800G, USB 4, Display Port, CXL 3.0 , TileLink, DDR5, LPDDR5, AXI 5, RI5CY, JESD204 C, AHB, CSI, DSI, CPHY, DPHY, , Spacewire, ARINC among many others. All the Verification IP includes comprehensive test suite, monitors, scoreboard etc. along with support and maintenance.

Truechip will be showcasing demo sessions, providing deep dives into the latest trends and technologies in Verification IP. The Verification IP demo will be for products like USB 4, PCIe, CXL, Ethernet, AMBA, Memory and will also showcase the NOC Silicon IP specially designed for AI and automotive applications.

Attend these sessions to gain valuable insights and practical knowledge from Truechip’s experienced engineers and thought leaders.

We invite you to join us at DAC 2024 and take advantage of the wealth of knowledge and resources Truechip has to offer. Be sure to visit our booth, attend our demo sessions, and participate in our workshop to gain a competitive edge in your verification projects.

**Register Now:**

https://www.truechip.net/dac-us-2024.php

We look forward to meeting you in San Francisco and sharing our passion for innovation in Verification IP!

For any questions or additional information, please contact us at Saurabh.agarwal@truechip.net

See you at the conference!

www.truechip.net

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CircuitSutra Technologies at the 2024 Design Automation Conference

CircuitSutra Technologies at the 2024 Design Automation Conference
by Daniel Nenni on 06-17-2024 at 4:00 pm
Categories: CircuitSutra, Events, Semiconductor Services

DAC 2024 Banner

The Design Automation Conference (DAC) is a premier event that focuses on the design and automation of electronic systems. It is an annual conference that has been held since 1964, making it one of the longest-running and most established events in the field of electronic design automation (EDA).

DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors. The conference is sponsored by the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE) and is supported by ACM’s Special Interest Group on Design Automation (SIGDA) and IEEE’s Council on Electronic Design Automation (CEDA).

CircuitSutra is one of the many companies supporting this industry-leading event.

CircuitSutra is in the business of developing fast simulation models of the semiconductor chips, SoC, IP, CPU & systems at a higher abstraction level using high level languages – SystemC, C++, Python. Its mission is to accelerate the adoption of advanced shift-left methodologies in the semiconductor industry.

CircuitSutra provides SoC Modelling Services, by setting up a world class modelling team to work as the extension of the customer;s team, either remotely or onsite at the customer;s office. It provides highly specialised SystemC training, which goes beyond the language teaching and covers the modelling techniques for specific abstraction levels. It also provides re-usable modelling methodology that helps the customers to get started quickly with their SystemC endeavours.

Traditional RTL-GDS flow is not sufficient to design the complex and powerful chips of today, and lots of design activities are being performed at an abstraction level above RTL. CircuitSutra augments RTL-GDS SoC design flow with SystemC / C++ based Shift-Left ESL methodologies to perform: HW-SW codesign, Pre-silicon firmware development through Virtual Prototypes, Architecture Analysis & Optimization,  High Level Synthesis.

At the higher abstraction level, simulation speed is very fast compared to the RTL. It is feasible to simulate the complete SoC or even the electronic system, together with the software.  The higher simulation speed is achieved by deploying the concepts like interface abstraction, timing abstraction and functionality abstraction. Interface abstraction is achieved by implementing the functionality at transaction level instead of pin level. For the SoC bus there is a standard TLM2.0, however for the other interfaces – LPDDR, HBM, UCIe, CAN, PCI, Ethernet etc.., the custom TLM has to be defined. Timing abstraction is achieved by removing the clocks and implementing the functionality in the loosely timed or untimed fashion. For every specific use case of the models, it has  to be carefully  analysed what part of the functionality is required to be implemented and what part need not be implemented. For example for the embedded software use case, we model only that much functionality which is visible to the software

Serving the industry since 2005, CircuitSutra is recognized as the de facto leader in SystemC modelling in India, and has now set up a team in Santa Clara to support the customers in North America. CircuitSutra started the India SystemC User Group conference in India in 2012, which was later merged with DVCon India. CircuitSutra was awarded by Accellera design systems to drive the standards in the Indian ecosystem. It is a highly focussed company with 100% focus on SystemC based shift-left methodologies, and having in-depth understanding of the domain.

Circuitutra invites you to meet them on the DAC exhibit floor booth#1328, and to attend their talk at the exhibit forum. You can contact CircuitSutra here to schedule a meeting.

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Arteris at the 2024 Design Automation Conference

Arteris at the 2024 Design Automation Conference
by Daniel Nenni on 06-17-2024 at 2:00 pm
Categories: Arteris, Events, IP

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Arteris, a leading provider of system IP, will exhibit at DAC 2024, June 23-27, booth #1506. The company will demonstrate its latest technology including network-on-chip interconnect IP and SoC integration automation solutions. The products highlighted include CSRCompiler, Ncore Cache Coherent NoC IP and FlexNoC 5 interconnect IP.

Arteris recently released enhancements to CSRCompiler, a vital software solution in their system-on-chip (SoC) integration automation strategy that also includes Magillem Registers and Magillem Connectivity ( check out the recent SemiWiki blog on the Magillem suite of products here). CSRCompiler reduces manual errors and enhances productivity by streamlining the generation of hardware/software interface (HSI) outputs. CSRCompiler supports rapid, iterative designs and ensures consistency across multiple teams, automating the generation of HSI requirements from high-quality RTL and software to design verification and documentation. This software solution utilizes SystemRDL 2.0, ensuring consistency across various views and organizations without time-consuming manual scripting and editing.

CSRCompiler’s HSI database is essential for architects, RTL designers, verification engineers, software developers, and technical writers, offering centralized and customized HSI information. It compiles thousands of registers within seconds and millions within minutes. The software solution’s adaptable architecture supports various input formats into a single source, ensuring efficient production of all required formats and helping avoid errors in address map deployment. This comprehensive approach reduces the HSI development process by up to one-third.

Recently released, the updated Ncore cache coherent network-on-chip (NoC) IP ensures low latency integration of hardware accelerators into a coherent domain, delivering the speed and efficiency required for cutting-edge applications in complex SoC designs. By using Ncore, SoC design teams can save more than 50 years of engineering effort per project compared to interconnect solutions that are manually generated.

Ncore supports multiple processor IPs, including the recently announced Armv9 Cortex processor and RISC-V. Its multi-protocol support allows seamless integration of IPs connected to the same NoC fabric. It offers flexibility with CHI-E, CHI-B, ACE fully coherent agent interfaces, ACE-Lite IO-coherent interfaces, and AXI for non-coherent sub-systems.

Ncore’s configurability and scalability allow SoC designers to meet specific PPA requirements with flexible fine-tuning of the NoC architecture. It is also certified for use in ISO 26262-compliant from ASIL B to ASIL D for automotive and other mission-critical systems.

Unveiled last year, FlexNoC 5, Arteris’ latest non-coherent NoC interconnect IP, is a game-changer for SoC architecture teams. Its physical awareness eliminates the need for lengthy NoC placement and route iterations, significantly reducing development time. This technology enables 5X faster physical convergence over manual refinements, leading to improved performance, lower power consumption, and reduced die size, all of which are crucial for efficient SoC design. The interconnect enhances compatibility with other SoC IP blocks through the Arteris Magillem connectivity flow.

FlexNoC 5 supports several topologies, as well as Arm AMBA 5 protocols and IEEE 1685 IP-XACT. Additionally, it offers a Functional Safety (FuSa) option compliant with ISO 26262 standards up to ASIL D, enhancing its suitability for safety-critical applications.

Arteris invites you to visit booth #1506 at DAC 2024, to meet their experts and explore how these technologies can benefit your SoC designs. You can also catch the following DAC sessions featuring Arteris:

NoC NoC – Who’s There?
Monday, June 24 from 3:30-5:00 pm
Location: 2012, 2nd Floor

A Single Source Unified Approach to CSR Register Development Poster Presentation
Monday, June 24 from 5:00-6:00 pm
Location: Level 2 Exhibit Hall

Accelerating Timing Closure for Network on Chips (NoCs) using Physical Awareness
Wednesday, June 26 from 1:30-3:00 pm
Location: 2012, 2nd Floor

If you can’t make it DAC, Arteris invites you to learn more at www.arteris.com.

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Arteris is Solving SoC Integration Challenges

Arteris Frames Network-On-Chip Topologies in the Car

Arteris is Unleashing Innovation by Breaking Down the Memory Wall