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Podcast EP229: A Detailed Look at the DAC Engineering Track with Ambar Sarkar

Podcast EP229: A Detailed Look at the DAC Engineering Track with Ambar Sarkar
by Daniel Nenni on 06-21-2024 at 6:00 pm

Dan is joined by Dr. Ambar Sarkar, a member of the Design Automation Conference executive committee and the program chair of the Engineering Tracks. He has a broad background covering both software and hardware R&D. He has contributed to industry standards in areas such as functional verification and IP security. He is the IEEE Computer Society’s representative for IEEE USA’s AI and Autonomous Policy Committee. Ambar is an individual contributor at NVIDIA where he enjoys working on compute and storage resource optimizations across large engineering teams. He is now also exploring the area of generative AI.

Ambar explains the focus and composition of the engineering track program at DAC. This part of the conference is focused on practical considerations for advanced product innovation. It is a peer-to-peer event where practicing engineers can exchange results and ideas. Topics covered include front-end design, back-end design, IP and software development.

Ambar also explains the extensive peer review processes behind both submitted and curated content for DAC. He discusses the many special events that will occur during DAC, including the popular poster gladiator competition that uses a live panel of judges and audience to determine the best poster presentation. He also covers the impact AI is having on chip design.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

June 21, 2024June 26, 2024

Daniel Nenni at the 2024 Design Automation Conference

Daniel Nenni at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 4:00 pm
Categories: 3D IC, Chiplet, Events

This year’s live semiconductor ecosystem conferences have been well attend and I expect the same for #61DAC next week. I will be at the conference from Sunday afternoon to Wednesday evening, if you would like to meet let me know. Networking is an important part of the semiconductor ecosystem so let’s make it happen.

The final opportunity to meet me at #61DAC will be on Wednesday afternoon. I will be moderating a panel on 3DIC, one of the more popular topics on SemiWiki.

Research Panel, Wednesday, June 26 @ 3:30pm – 5:30pm PDT, 3014, 3rd Floor

3DIC Design Ecosystem – The Cats That Need Herding!

At the end of 2D scaling of Moore’s law, 3D integrated circuits that take advantage of advanced packaging and heterogeneous integration offers many prospects of extending the chip density scaling and the system performance improvements for the next decade. Much of 3DIC design activity in the industry today is done via different teams within the same company. 3DICs hold the potential to not only make the chip architecture heterogeneous, but also chiplet sourcing to be highly diversified. Moreover, 3DICs themselves have a few avenues to be realized towards commercial success, ranging from true disaggregated chiplets to sequential stacked processing. This presses us to answer a few key questions:

1. Technology:

a. How will heat dissipation be managed, are new cooling techniques being pursued to mitigate the thermal challenges?

b. How to design the power delivery network from the board to the substrate to the multi-tier of 3D stack with minimal voltage drop and high-power conversion efficiency? How to design the backside power delivery in leading edge node CMOS with 3D stacking?

c. How to ensure signal integrity, yield and reliability between multiple tiers of 3D stacking, and what testing and standardization efforts are needed to embrace the heterogeneous dies from different designers and different foundries?

2. EDA flows and interoperability

a. Will the ecosystem extend the same standards-based interoperability of design tools, flows and methodologies to 3DIC, as enjoyed by system designers today?

b. How can the EDA industry help system designers in planning, managing and tracking their complex 3DIC projects in implementation, analysis, and signoffs?

3. Roadmap:

a. Is the roadmap to sequential monolithic stacked 3DIC inevitable? What factors will lead the industry to it?

b. What are the boundaries between monolithic 3D integration (with sequential processing at BEOL) and heterogenous 3D integration (with die stacking or bonding)?

We as an industry must be able to apply lessons from the past struggles with monolithic chip design and interoperability to this emerging challenge. This panel will discuss the need, scope of solution, and potential candidate efforts already in motion.

I hope to see you there!

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June 21, 2024June 21, 2024

Breker Verification Systems at the 2024 Design Automation Conference

Breker Verification Systems at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 2:00 pm
Categories: Breker Verification Systems, EDA, Events, RISC-V

Breker Verification Systems will demonstrate its new RISC-V CoreAssurance™ and SoCReady™ SystemVIP™ along with its Trek Test Suite Synthesis portfolio during the 61st Design Automation Conference (DAC) in Booth #2447. DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

RISC-V cores require an extensive amount of verification, including capabilities uncommon in general block verification, required to achieve the quality bar set by Arm and X86. RISC-V processor core verification can be considered as a stack of verification tests starting with basic operational tests, ISA compatibility and micro-architectural testing, then leading to integrity and integration testing to ensure system level compatibility, and performance testing.

Breker’s RISC-V CoreAssurance SystemVIP provides the complete range of tests for the entire RISC-V core verification stack. Starting with randomized instruction generation and microarchitectural scenarios, SystemVIP includes tests that check all integrity levels ensuring the smooth application of the core into an SoC, regardless of architecture, and the evaluation of possible performance and power bottlenecks and functional issues.

It can be extended for custom RISC-V instructions to be incorporated into the complete test suite crossed with other tests. It is self-checking and incorporates debug and coverage analysis solutions and can be ported across simulation, emulation, prototyping, post-silicon and virtual platform environments.

The Breker SoCReady SystemVIP extends these capabilities for teams integrating RISC-V processors on SoCs needing to ensure SoC issues such as load store efficiency, interrupt testing, coherency, security and more are fully evaluated. It is also useful to ensure the quality of RISC-V cores obtained from other vendors.

Based on synthesis technology, the SystemVIP amplifies scenario models to improve coverage and bug hunting. An AI technique called Planning Algorithms explores the state space of the various scenarios starting with the desired end space and working backward to initial inputs. This technique allows for precise test execution that tracks from input to specific states leading to more effective bug hunting with fewer tests than a more general hit and miss randomized approach.

Test cross combination is another synthesis technique that combines various scenario components in a multi-dimensional series of tests. For example, crossing different privilege levels with branch prediction and load store scenarios to build combined tests grows the odds of an unusual corner case issue occurring.

Scheduling concurrent scenarios further increases pressure on design components to reveal difficult bottlenecks in design architecture by “torturing” the device to reveal weaknesses. Tests are scheduled together across HARTS and multicore processors that overload SoC resources, allowing the performance of the tests to be examined in a profiling window.

Breker’s SystemVIPs are used for a variety of complex RISC-V core designs, including system coherency in a multicore SoC. integrity test sets, high-coverage core test, power domain switching, hardware security access rules and automated packet generation

Breker’s RISC-V CoreAssurance and SoCReady SystemVIPs are available now as are its Test Suite Synthesis solutions. Pricing is available upon request. For more information, visit the Breker website or email info@brekersystems.com. To arrange a demonstration or private meeting at DAC, send email to info@brekersystems.com.

DAC registration is open.

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June 21, 2024June 21, 2024

Flex Logix at the 2024 Design Automation Conference

Flex Logix at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 12:00 pm
Categories: eFPGA, Events, Flex Logix

The rapid technological evolution and soaring mask set costs have created numerous challenges for designers today. Protocols, algorithms, and cryptography are all advancing at a blistering pace, leaving designers struggling to keep up. While fab suppliers are enhancing performance and reducing power consumption, this progress comes at a price – limiting the number of affordable mask iterations for manufacturers. Flex Logix provides a compelling solution, offering hardware acceleration and reconfigurability that can save designers time and money, arriving at the perfect moment.

Flex Logix’s embedded FPGA IP, EFLX, is highly optimized for SoC and ASIC implementation, providing the performance and functionality of traditional off-the-shelf FPGAs. The scalable EFLX IP ranges from 200 to over 1 million logic cells, enabling IC designers the flexibility to adapt to evolving interfaces, protocols, and algorithms. Furthermore, production products can use this IP to repair bug fixes, provide lasting security, and meet unique regional requirements without costly design respin. Adding eFPGA IP offers additional value by enabling different functions at various stages of the product lifecycle. During IC bring-up, the IP can facilitate built-in self-testing and debugging. In production, the IP can multitask as a cryptographic controller, algorithm accelerator, interface expander, or other desired function.

Flex Logix offers signal processing IP, InferX, which can dramatically accelerate DSP and AI algorithms. Many designers use FPGAs for signal processing due to their abundance of multipliers and localized memory. Flex Logix takes this a step further by enabling advanced mathematical functions like matrix inversions, filters, and transforms in InferX. This IP can achieve exceptional performance at incredibly low power and area. Its scalable AI inference is highly efficient, delivering much higher inference throughput per square millimeter and per watt. Interested parties can visit Flex Logix’s booth to see a live demo of this innovative technology.

We are also thrilled to launch our new eXpreso FPGA Compiler – a powerful upgrade to our EC1 compiler. This cutting-edge tool boosts designer productivity with up to 10x faster compilation, 50% better performance, and 2x logic area reduction. We will also be demonstrating this at our booth, stop by to see how efficiently this tool can implement complex algorithms.

Flex Logix is a leading provider of reconfigurable computing technologies, including its innovative eFPGA and AI Inference solutions for semiconductor and systems companies. Flex Logix’s EFLX eFPGA enables FPGA users to seamlessly integrate the FPGA into their companion SoCs, resulting in a 5-10x reduction in the cost and power of the FPGA while increasing compute density – a critical advantage for applications in communications, networking, data centers, microcontrollers, and more. Flex Logix’s IP integrates seamlessly into any SoC or ASIC, and with over 100 US patents and applications, it offers top-tier power, performance, and area (PPA) metrics, compatible with cutting-edge nodes like Intel 18A, TSMC 7nm, and 5nm. The scalability of Flex Logix’s eFPGA IP empowers users to optimize their resources for enhanced flexibility.

Interested in Flex Logix IP? Visit our website at https://flex-logix.com email us at info@flex-logix.com. We’d love to meet you at the Design Automation Conference in San Francisco from June 24-26 at booth #1327, where we can discuss the many use cases and benefits of our IP.

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June 21, 2024May 27, 2025

Alphacore at the 2024 Design Automation Conference

Alphacore at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 10:00 am
Categories: Alphacore, Events, IP

Alphacore Inc., an industry leader in proven high-performance analog and radio-frequency (RF) design building blocks, end products, and intellectual property (IP) licensing and non-recurring engineering (NRE) design services. Our customers include multi-national corporations to ground-breaking startups. We were founded in 2012 with headquarters in Arizona’s center of technological innovation, the Silicon Desert. Our engineering and leadership team combines long histories of delivering innovative data converter, RF, analog and mixed signal products, and complete imaging solutions for critical systems, through their business success at both startups and multinational companies.

We drive next-generation ultra-high speed, ultra-low power, radiation tolerant validated data conversion technology with IP designs enabling applications such as 5G/6G Communications, Beam Forming, Automotive sensing, Aerospace and Defense.

At Alphacore, our customers appreciate the specialized Design Services we offer for high performance/low power integrated circuit intellectual property (IP), Analog/Mixed Signal, harsh environments/robustness where our knowledgeable designers create novel analog building blocks and complete circuits using established and leading-edge process technology nodes for demanding conventional and harsh-environment applications.

Our designs utilize advanced technologies from broad-based suppliers such as TSMC and GlobalFoundries, as well as multiple specialty foundries, based on customer requirements and best fit for the application. Alphacore is a proud member of the GlobalFoundries® (GF®) FDX^TM Network.

Visit our website (www.AlphacoreInc.com) to view our ever-growing portfolio of IP solutions, including a wide range of megasample and gigasample per second (MS/s and GS/s) ADC and DAC IP products (e.g., 11-bit, 5 GS/s ADC A11B5G; 6-bit, 5 GS/s DAC D6B6G).

We specialize in designing high performance solutions for the niche needs of demanding market segments that address harsh environments, including scientific research, aerospace, defense, medical imaging, and homeland security. Accordingly, our engineering team includes seasoned device physics and “Radiation-Hardened-By-Design” (RHBD) experts.

At Alphacore, we offer products that focus on delivering uncompromised world-class performance while also meeting strict size, weight, power, cost (SWaP-C), and environmental constraints. Our customers get the best of both worlds.

Strategic core business areas include:

High performance and low power analog, mixed signal, and RF electronics
High-speed visible light and infrared Readout ICs (ROICs) and full camera systems
Robust Power Management ICs (PMICs) for space and high-energy physics experiments
Innovative devices ensuring supply chain and IoT cybersecurity

Our customers benefit from prioritized focus on their projects, keen attention to detail, and a higher level of care and responsiveness that we deliver. It is crucial for us to ensure the complete satisfaction of our customers, both in our products and in the way we do business. That is why we work with companies to create adaptable plans of action, and provide flexibility in our commercial contracts and agreements. We adhere to International Traffic in Arms Regulations (ITAR) and maintain Cybersecurity Maturity Model Certification (CMMC) compliance.

Alphacore is a regular participant supporting this industry-leading event, and we invite you to meet with our Alphacore experts on the exhibit floor. You can contact Alphacore here to schedule a meeting at booth #2332. We hope to see you there!

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June 21, 2024September 24, 2024

Pragmatic at the 2024 Design Automation Conference

Pragmatic at the 2024 Design Automation Conference
by Daniel Nenni on 06-21-2024 at 8:00 am
Categories: EDA, Foundries, Pragmatic Semiconductor

Pragmatic is pioneering a fundamental shift in semiconductor technology, delivering lower-cost, lower-carbon intelligence to power the Internet of Everything. Its FlexIC – flexible integrated circuit – technology delivers connect, sense and compute capabilities at a fraction of the cost and carbon footprint of silicon chips.

The FlexIC Foundry® enables rapid, high-volume fabrication with a high level of customisation, taking designs from tape-out to delivery in just weeks. The unique, low-temperature processes consume less energy and water, with fewer harmful chemicals, making Pragmatic one of the most sustainable semiconductor manufacturers in the world.

This year, Pragmatic Semiconductor will be setting up stall at the Design Automation Conference (DAC) for the first time.

Visit stand 1534 to discover their new, industry-standard 300mm wafers, as well as demos including:

PlasticARM
The groundbreaking ultra-minimalist Cortex-M0-based SoC boasting 128 bytes of RAM and 456 bytes of ROM – 12x more complex than previous state-of-the-art flexible electronics
Electronic nose
The world’s first machine-learning-based flexible mixed-signal chip, integrated with a flexible electronic nose sensor array.
Temperature sensors
A selection of Flex-IC based sensors in a thin, flexible form factor:
- Standalone temperature sensor
  A discrete linear PTC temperature sensor, supporting a wide operating window
- I2C temperature sensor
  Integrated analogue front-end and digital I2C temperature readout, enabling wide-array sense capability
- Temperature sensor with heating element and control logic
  Fully integrated heater FlexIC with on-chip sensor, control logic and heating elements
NFC products
For applications including consumer engagement, authentication and tamper detection

About Pragmatic

Pragmatic has developed an integrated circuit (electronic ‘chip’) platform that doesn’t rely on silicon. Our revolutionary technology uses thin-film semiconductors to create flexible integrated circuits that are thinner than a human hair and are significantly cheaper and faster to produce than silicon chips. This provides a compelling alternative for many mainstream electronics applications, as well as enabling new applications not possible with silicon.

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June 20, 2024June 20, 2024

Empyrean at the 2024 Design Automation Conference

Empyrean at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 8:00 pm
Categories: EDA, Empyrean, Events

Empyrean Technologies is excited to introduce our comprehensive and highly productive Custom IC design solutions at DAC 2024. Our suite of tools is fully integrated within a design environment tailored for AMS (Analog/Mixed-Signal) designs, covering every step from initial design specification to tape-out. These tools support advanced nodes like 5nm and 3nm and are widely adopted by major semiconductor companies.

Comprehensive Custom IC and PMIC Design Solutions

Key Features:

Seamless Integration: Integrates smoothly with the SPICE simulator ALPS suite, physical verification tool Argus, transistor-level dynamic Electromigration and IR drop (EMIR) analysis tool Patron™, and parasitic extraction tool RCExplorer. This ensures a highly efficient workflow that mitigates risk and boosts productivity.

Comprehensive Reliability Analysis: Our specialized tools provide extensive solutions for EMIR with thermal awareness analysis, ESD/ERC, Monte Carlo, Failure in Time (FIT) calculation, and DSPF-based RC Analysis, enabling early detection of potential design issues.

Fast GPU-Accelerated SPICE Simulator

Empyrean ALPS-GT is a heterogeneous simulation system based on the CPU-GPU platform architecture. Compared to traditional CPU architecture, ALPS-GT offers accelerated processing power and significantly improves performance with GPU Turbo Smart Matrix Solving (SMS-GT) technology. Utilizing the ALPS engine, it provides SPICE accuracy and breaks the bottleneck in large-scale analog and mixed-signal circuit simulation performance, achieving a 10x performance improvement over current CPU-based parallel SPICE for post-layout simulation.

Extraction and Verification Tools

Empyrean RCExplorer: Supports transistor-level and standard cell-level post-layout extraction for analog designs. It also supports point-to-point RC analysis and timing delay analysis.
Empyrean Argus: A physical verification tool that includes DRC and LVS, helping improve verification quality and efficiency.

PMIC Design Solutions

Empyrean Technologies offers a comprehensive design flow specifically tailored for PMIC (Power Management IC) designs. This suite of tools is fully integrated within a design environment covering every step from initial design specification to tape-out, delivering performance, accuracy, and user-friendliness.

Key Features:

Comprehensive Power Device Analysis: Specialized tools for analyzing power devices, including accurate Rds(on) value calculations, ensuring PMIC efficiency and avoiding costly re-spins.
Efficient EMIR Analysis: Advanced Electromigration and IR Drop (EMIR) analysis tools provide deep insights into power integrity and noise, optimizing designs for robust performance.
Key Network RC Analysis: A fast DSPF-based RC Analysis tool evaluates critical RC effects in large power networks, detecting potential issues early in the design process.

Highlighted Products:

Empyrean Patron™: A state-of-the-art power integrity tool designed to ensure the performance and reliability of analog and mixed-signal designs. It specializes in transistor-level power and signal net electromigration (EM) analysis and power net IR-drop analysis.
Empyrean Polas™: Offers a powerful solution for analyzing and optimizing power devices. It is designed to handle the complexities of PMIC designs, providing a highly integrated system that includes extraction, simulation, results viewing, and analysis.

Digital SoC Design Solution

Empyrean Technology also provides a comprehensive SoC (System on Chip) solution, including:

Standard cell library characterization
Memory characterization
Mixed-signal IP characterization
Standard cell library and IP validation
Clock diagnosis and analysis
Accurate timing simulation and analysis
Timing and power optimization
Layout integration and analysis
Digital physical verification
Parasitic RC extraction

These solutions ensure that designers can meet the stringent demands of modern electronic designs with confidence and efficiency. Empyrean’s participation at DAC 2024 will showcase its commitment to pushing the boundaries of electronic design automation and providing cutting-edge solutions to the semiconductor industry.

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June 20, 2024May 27, 2025

AMIQ EDA at the 2024 Design Automation Conference

AMIQ EDA at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 6:00 pm
Categories: AMIQ EDA, EDA, Events

AMIQ EDA is a pioneer in integrated development environments (IDEs) for hardware design and verification and a provider of platform-independent software tools for efficient code development and analysis. We’ve been attending DAC for many years and are pleased to do so again in 2024. We exhibit at this show for several reasons. We’re always looking for new users and our booth is a great place for them to check us out. We also meet with many current users, providing updates on what we’re doing and sometimes just saying hello.

As veterans in the EDA industry we know many people from other vendors and organizations, so DAC is a great opportunity to catch up. Finally, the location in San Francisco is just an hour from the heart of Silicon Valley, so we always stay a few extra days to visit users at their facilities. Quite often we will offer a short training course for new users or a presentation on the latest features for those who already know us. Everyone is interested in what’s new and what we’re working on for the future.

So what is new this year? For a start, we have added some cool features for SystemVerilog users to our Design and Verification Tools (DVT) Eclipse IDE and DVT IDE for Visual Studio (VS) Code. We now offer runtime elaboration of Universal Verification Methodology (UVM) code, making it easier to find and fix coding errors within the IDE editor. UVM is a complex verification library with lots of SystemVerilog macros, so the ability to elaborate and check code on the fly is valuable.

We’ve added the ability to precompile or “shallow compile” portions of code to speed up the full build process. This is helpful because verification environments for huge chips are also huge. Not having to compile the full code set all at once saves time and shortens the find-fix-verify loop for coding errors. We’ve also added support for SystemVerilog AMS, reflecting the fact that many of our users are designing mixed-signal chips.

We’ve also significantly improved our ability to handle SystemVerilog files that contain “preprocessor” statements in other languages such as Perl or Python’s Jinja2 library, or even in proprietary languages. Users can edit such files just as if they were pure SystemVerilog. They can take advantage of all their favorite IDE capabilities: navigational hyperlinks, autocomplete, on-the-fly incremental compilation and error detection, quick fixes, refactoring, and more.

We’ve not forgotten our other products. Our Verissimo SystemVerilog Linter now checks around 900 rules, more than 100 of which were added in the past year. Our Specador documentation tool now has a new HTML interface plus support for the PDF and Markdown formats. So, yeah, there’s a lot new to see at DAC. We’re happy to show demos of any features in our booth or to arrange a virtual or physical visit with design and verification teams who may not be at the show.

As we did last year, we’re sponsoring the City Bytes & Beverages Hospitality Zone, where attendees can buy a quick lunch that’s a lot more interesting than the usual convention center hot dogs and frozen pizza. There will be AMIQ EDA signs around to remind everyone that we are long-time supporters of DAC. We invite everyone to stop by our booth!

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June 20, 2024January 9, 2025

proteanTecs at the 2024 Design Automation Conference

proteanTecs at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 4:00 pm
Categories: Analytics, Events, proteanTecs

Meet with proteanTecs at DAC. Explore our full set of health and performance monitoring solutions. We’ll be showcasing our latest products and solutions, and we’d love to connect while you’re there. Visit booth #2417 to explore our health and performance monitoring solutions.

Also – Don’t miss out on our daily sessions in our in-booth theater, featuring guest speakers from top companies in ASIC, design, IP, services, cloud, and proteanTecs.

We are also accepting booking for a private session in our meeting room, presenting new solutions and features tailored to your needs

proteanTecs offers a first-of-its-kind, in-system self-monitoring solution. With machine learning, we unlock deep insights increasing reliability, optimizing power, and enhancing quality.

During the show, we will be presenting multiple solutions, including:

Power and Performance
Reliability, Availability, Serviceability
Functional Safety & Diagnostics
Product Bring-Up
Operations & Quality
Die-to-Die Interconnect

Meet us at Booth 2417, 2nd floor

See the full booth agenda, and book a meeting at –

Meet proteanTecs at DAC 2024

About proteanTecs

proteanTecs is the leading provider of deep data analytics for advanced electronics monitoring. Trusted by global leaders in the datacenter, automotive, communications and mobile markets, the company provides system health and performance monitoring, from production to the field. By applying machine learning to novel data created by on-chip monitors, the company’s deep data analytics solutions deliver unparalleled visibility and actionable insights—leading to new levels of quality and reliability. The company is headquartered in Israel and has offices in the United States, India, South Korea and Taiwan. For more information, visit www.proteanTecs.com.

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June 20, 2024June 20, 2024

Sigasi at the 2024 Design Automation Conference

Sigasi at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 2:00 pm
Categories: EDA, Events

Sigasi® will demonstrate its Sigasi Visual HDL™ (SVH™) portfolio during DAC, showing how it supports the shift-left methodology for chip design, catching specification errors early in the design cycle and fixing the inefficient HDL-based design flow.

The traditional HDL workflow cannot accommodate the massive amounts of design specifications from GenAI creations, high-level synthesis results, and other complex SoC IP. These new levels of abstraction need to plug and play alongside large HDL files—that contain functionality created with domain-specific knowledge—to integrate hundreds of billions of transistors on a chip.

The comprehensive Sigasi Visual HDL portfolio is an HDL platform able to take advantage of the shift-left methodology and give hardware designers and verification engineers better insight during the design progress. They can easily manage HDL specifications by validating code early in the design flow, well before simulation and synthesis flows. SVH does so by standardizing the concept of an HDL design project, bringing simulation and synthesis projects into a world of integrated development, synchronous visualization, and shift-left validation.

Integrated Development: SVH is fully integrated with Microsoft’s Visual Studio Code (VS Code), the most popular IDE, according to Stack Overflow’s 2019 survey, with a rich marketplace of productivity tools. It includes sophisticated applications to easily use git and GitHub Source Control Management, as well as a selection of utilities to facilitate mundane tasks like extracting TODO comments or bookmarking important sections in HDL code.

Synchronous Visualization: SVH lets users move seamlessly through hierarchy views and graphics that update instantaneously as they make changes in their code.

Shift-Left Validation: SVH flags problems while users enter HDL code. Starting with syntax and semantics, it enforces coding styles as recommended by safety standards such as DO-254 or ISO 26262 and catches UVM abuses.

SVH comprises a tiered portfolio, offering three commercial editions meant to meet specific SoC design and verification challenges. The new offering also unveils Sigasi’s new AI chatbot, SAL, a chatbot that works with a local model or a remote OpenAI API and can generate, check, and explain HDL code. Each tier of SVH offers a comprehensive package of features, including type-time syntax and semantic checks and guardrails that enforce coding styles, policies, and standards. Regardless of which tier they use, engineers receive instant feedback and warnings for all files associated with a project.

Additionally, Sigasi offers a fully functional Community Edition that lets users explore its features for non-commercial uses, especially students and teachers learning and teaching the fundamentals of HDL design.

Sigasi will fly its new logo and tagline “Put Your Semicolons to Work” while exhibiting and demonstrating Sigasi Visual HDL at DAC Booth #2416 (second floor). DAC will be held from Monday, June 24, through Wednesday, June 26, from 10 a.m. until 6 p.m. at Moscone West in San Francisco.

More details can be found on the Sigasi website or by emailing sales@sigasi.com.

To arrange a demo or private meeting to talk about Sigasi Visual HDL, send an e-mail to: dacmeeting@sigasi.com.

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