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Semiconductor Expert Forum

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CEO Interview with Dr. William Wang of Alpha Design AI

CEO Interview with Dr. William Wang of Alpha Design AI
by Daniel Nenni on 02-21-2025 at 6:00 am
Categories: AI, ChipAgents AI, EDA

profile20

William Wang is the CEO and founder of Alpha Design AI, a generative AI startup transforming chip design and verification through ChipAgents, an agentic AI development tool for RTL and verification engineers. ChipAgents accelerates design, debugging, and verification of hardware description languages (HDL), integrating AI-driven automation into Electronic Design Automation (EDA) workflows. Under his leadership, Alpha Design AI has secured strategic partnerships and enterprise contracts with major semiconductor companies.

William is also the Director of the Natural Language Processing Group and Center for Responsible Machine Learning at UC Santa Barbara, where he holds the Duncan and Suzanne Mellichamp Professorship in Artificial Intelligence and Designs.

He has received numerous prestigious awards, including the DARPA Young Faculty Award (2018), IEEE AI’s 10 to Watch (2020), NSF CAREER Award (2021), British Computer Society Karen Spärck Jones Award (2022), the CRA-E Undergraduate Research Faculty Mentoring Award (2023), and IEEE SPS Laplace Award (2024). His research has been supported by major tech companies, securing large contracts and gifts from all major big tech companies around the world.

William completed his PhD in Computer Science at Carnegie Mellon University and has published ~250 papers in AI, machine learning, and NLP. His insights and research have been featured in Wired, VICE, Scientific American, Fortune, Fast Company, NASDAQ, The Next Web, Law.com, and Mental Floss.

Tell us about your company?

We are building the next generation of Agentic AI EDA tools for chip design and verification. Our flagship product, ChipAgents, is a suite of intelligent AI agents designed to enhance the productivity of hardware engineers working with HDL (Hardware Description Languages) like Verilog and SystemVerilog. We leverage generative AI and agentic workflows to accelerate debugging, verification, and design iteration, ultimately reducing time-to-market for semiconductor companies.

AI is transforming EDA workflows faster than ever, and we are at the forefront of this shift. AI agents will be able to empower engineers to significantly improve their productivity for complex designs. For example, for a DDR5 project, instead of four engineers working for a whole year, it will be 2 months with the help of ChipAgents.

We’ve been laser-focused on making AI truly useful in EDA by integrating the best agentic AI solutions with industry-standard tools, and addressing real engineering pain points. Since launching ChipAgents, we’ve successfully deployed it to leading semiconductor companies, startups, and AI accelerator firms to refine and deploy our technology. Our technology is being used by semiconductor leaders responsible for billions of chips shipped worldwide.

With ChipAgents, I’m bringing THE best AI to EDA, leveraging my experience in agentic AI automation to transform RTL design, verification, and debugging with agentic workflows and deep integration with industry standard tools. Our goal is to redefine chip development, making it faster, smarter, and more efficient with AI.

What problems are you solving?

Chip design and verification are some of the most expensive and time-consuming aspects of semiconductor development. Verification alone can consume over 80% of the total design cycle, and debugging RTL code is an arduous process that hasn’t seen much innovation in decades.

We’re solving three key pain points:

  1. Reducing Debug Time: Engineers spend countless hours troubleshooting RTL and testbenches. Our solution helps users understand their design requirements, the RTL code, testbenches, and accelerates bug resolution by working with ChipAgents and automating tedious tasks.
  2. Improving Verification Efficiency: Traditional verification relies on manual testbench creation and constraint tuning. ChipAgents can generate, optimize, and validate testbenches, boosting functional coverage.
  3. Enhancing Productivity with AI-Driven Insights: Unlike generic coding assistants, ChipAgents understands semiconductor-specific workflows, integrating deeply with EDA tools to provide actionable insights rather than generic code completions.
What application areas are your strongest?

Our strongest application areas include:

  • RTL Design & Debugging – Helping both ASIC and FPGA engineers write, optimize, and debug Verilog/SystemVerilog more efficiently.
  • Functional Verification – Automating UVM testbench generation and improving coverage.
  • EDA Tool Scripting – Assisting with tool automation for top vendors, and other industry platforms.
    AI-Accelerated Semiconductor Design – Exploring new workflows for AI-assisted chip development, including PPA (Power, Performance, Area) optimization.

Our early adopters include teams designing AI accelerators, custom ASICs, RISC-V processors, and memory chips—all areas where reducing verification cycles and debugging complexity translates directly to faster time-to-market.

What keeps your customers up at night?

A few key challenges dominate our customers’ minds:

  • Verification bottlenecks – Engineers struggle to hit coverage goals without significantly extending design schedules.
  • Time-to-market pressure – AI, automotive, and HPC chip companies are in an arms race; delays mean losing competitive advantage.
  • Tool complexity – EDA tools are incredibly powerful but often require deep expertise and cumbersome scripting to maximize their value.
  • AI and automation skepticism – Many engineers are skeptical about how well AI can integrate into their existing workflow without disrupting their rigorous design methodologies.

We designed ChipAgents to address these concerns head-on by providing practical human-in-the-loop solutions without disrupting proven verification methodologies, and our fully agentic AI solutions will demonstrate the promise of this technology.

What does the competitive landscape look like and how do you differentiate?

The EDA space is dominated by Synopsys, Cadence, and Siemens, which provide powerful but complex toolchains. Several AI startups are trying to introduce LLMs for hardware development, but most are either too general-purpose or lack deep integration with industry tools.

We differentiate in three ways:

  1. Deep Technical Expertise in AI – We started training the first neural language model back in 2011 (Yes, even before ImageNet), and the team has 15 years of experience in training and working with language models: this is the absolute unique differentiator in the market.
  2. Purpose-Built for EDA, Seamless Integration – ChipAgents is optimized specifically on chip design and verification workflows, unlike generic AI coding assistants. We work within engineers’ existing tools rather than forcing them to switch platforms.
  3. Agentic Workflows – Beyond just providing suggestions, ChipAgents can take actions, such as running simulations, modifying testbenches, and optimizing assertions.

For now, we’re not trying to replace existing EDA tools—we’re augmenting them with AI to make engineers exponentially more productive. This paved the way for future fully agentic solutions.

What new features/technology are you working on?

We’re continuously enhancing ChipAgents with AI-driven innovations focused on improving design, verification, and optimization workflows. Our upcoming advancements include:

  • Intelligent Debugging Support – AI-powered assistance to streamline troubleshooting and accelerate issue resolution in complex designs.
  • Automated Verification Optimization – AI-driven enhancements that adapt to engineering workflows, improving functional coverage and verification efficiency.
  • AI-Guided Design Insights – Advanced analysis tools that provide engineers with real-time feedback on design modifications, including key performance trade-offs.

Our vision is to establish AI as a trusted co-engineer, enabling hardware designers to focus on high-value problem-solving while reducing the burden of manual debugging and verification.

How do customers normally engage with your company?

We offer three ways for customers to engage:

  1. Pilot Programs & Trials – Customers can deploy ChipAgents on a pilot to evaluate its impact on their design and verification workflow.
  2. Enterprise Licensing – We provide flexible licensing options for startups, mid-market, and large semiconductor firms, with dedicated onboarding and support.
  3. Strategic Collaborations – We work closely with select big tech that pushes the boundaries of automation in chip design.

Our early traction has been strong, and we’re expanding collaborations with semiconductor leaders, companies, and EDA innovators who see AI as the future of hardware design. Feel free to reach out to us at chipagents.ai and Book a Demo with us.

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2025 Outlook with Sri Lakshmi Simhadri of MosChip

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2025 Outlook with Sri Lakshmi Simhadri of MosChip

2025 Outlook with Sri Lakshmi Simhadri of MosChip
by Daniel Nenni on 02-20-2025 at 10:00 am
Categories: CEO Interviews

Srilakshmi Simhadri VP Semicon BU Head MosChip®

Tell us a little bit about yourself and your company. 

I am Sri Lakshmi Simhadri, and I head Semiconductor BU at MosChip® Technologies, responsible for Semiconductor Design Services. I have 30+ years of Semiconductor Industry experience. Held leadership and project management roles with multi-national companies like Cyient and Time-To-Market. I have worked with both Product and Design Services companies, with hands on experience spread across multiple domains of chip design (Design, CAD, Emulation, Synthesis, DFT, PNR & Timing) and managing engineering teams distributed across the globe.

I graduated from New Jersey Institute of Technology, Newark, NJ with a Master’s in Computer Science, and did Bachelor’s in Electronics & Communication Engineering from Nagarjuna University, A.P., India.

MosChip® Technologies, established in 1999 is the first fabless semiconductor company with 1250+ engineers located in Silicon Valley-USA, and India. It provides engineering solutions encompassing end-to-end silicon design, verification, systems, software, and device engineering, multimedia, mobility, connectivity, AI/ML, and test automation, along with Mixed Signal IP and Turnkey ASIC design services. MosChip® has developed and shipped millions of connectivity ICs and has an excellent track record of first-time silicon success of 200+ SoC tape-outs.

What was the most exciting high point of 2024 for your company? 

MosChip® has reached new heights in the year 2024, with some remarkable achievements. It marked key project win where MosChip® in consortium with Socionext will be developing high-performance computing processor for C-DAC. MosChip® also received an approval under DLI scheme for developing a Smart Energy Meter IC, catered for domestic and international markets. In March, MosChip® and Tenstorrent announced their partnership to design SOCs using Tenstorrent’s cutting edge RISC-V solutions. With exceptional expertise and commitment, this further solidifies MosChip®’s position as a trusted technology partner for semiconductor solutions.

In addition, MosChip® also successfully launched MosChip DigitalSky™ offering digital solution suite, to build intelligent and connected enterprises. This milestone underscored our commitment to driving digital transformation through innovative, human-centric, and AI-driven solutions.

Moreover, we are honoured to have won the “Partner Par Excellence Award” from Qualcomm for our outstanding work in Software Development. Also, MosChip® was recognized among Asia-Pacific’s Top 500 high-growth companies by institutions like Financial Times and Statista. This recognition shows our ongoing dedication to excellence and innovation in the semiconductor industry.

These milestones of 2024 encourage our determination to continue pushing boundaries, driving growth, and making a positive impact in the semiconductor and product engineering sectors.

What was the biggest challenge your company faced in 2024 from semiconductor industry perspective?

In 2024, MosChip® faced a complex challenge of adjusting to the shifts in market trend, that led to evolving customer requirements. It was extremely hard to find skilled senior technical leads and professional managers to address competitive market requirements for navigating an evolving global semiconductor market. Balancing the need for innovation with operational scalability required us to think through the strategies. However, despite these challenges, MosChip® was committed to deliver value to customers and stay ahead in the market with strategic collaborations, optimizing resources, and strengthening partnerships.

How is your company’s work addressing this biggest challenge? 

MosChip® has taken significant initiatives to groom qualified engineers internally, help them grow technically and lead the projects. We also develop new talent in the semiconductor and software fields with our indigenous institute, the “MosChip® Institute of Silicon Systems (M-ISS)”. With our industry connections and credibility in the market, we are able to utilize our resources efficiently with on-going and new engagements. Moreover, we also prioritized close collaboration with customers, tailoring solutions to meet their evolving needs, building trust with technical talent, successful execution and creating value through future-ready technologies.

What do you think the biggest growth area for 2025 will be, and why?

The demand for specialized AI processors, such as GPUs, TPUs, and custom AI accelerators, will continue to grow, as the industry integrates AI into applications like autonomous vehicles, robotics, healthcare, and edge computing. With the rise of real-time data processing needs, semiconductors designed for edge computing offering low power consumption, high efficiency, and robust security will see significant growth. Moreover, the shift towards electric vehicles (EVs) and advanced driver-assistance systems (ADAS) is creating demand for high-performance chips for power management, in-vehicle networking, and autonomous driving capabilities. With growing cyber threats, there will be heightened demand for semiconductors with built-in security features, such as hardware-based encryption and secure processing units. Emerging trends such as Chiplets, RISC-V, and AI/ML offer promising opportunities for innovation, empowering MosChip® to strengthen its position and play a significant role in the industry.

How is your company’s work addressing this growth? 

MosChip® is well positioned to capitalize on the key growth areas projected for 2025 by leveraging its expertise in semiconductor, digital and product engineering solutions.

By adopting RISC-V architectures, advanced chiplet-based designs, MosChip® drives scalability and performance improvements for semiconductors that meet the demands of modern applications. Moreover, through MosChip DigitalSky™ launch, we are driving the integration of next-gen technologies like AI, GenAI, RPA, AIoT, cybersecurity and more into digital solutions, empowering industries with real-time decision-making, human-centric and persona-specific solutions. Overall, we aim at capitalizing on growth prospects under semiconductor industry as well as next-gen digital era.

What conferences did you attend in 2024 and how was the traffic?

In 2024, MosChip® actively participated in several conferences and industry forums, highlighting our expertise in semiconductor engineering, product engineering and digital transformation. Some key events included Embedded World North America, Electronics Asia Conference, Lattice DevCon, TSMC North America Technology Symposium, Semicon India, VLSI Design Conference, IESAVision Summit and ChipEx 2024.

Many intrigued attendees from the conferences visited our booth to look at the exhibits and talked to our team regarding competitive skillset, projects and our execution methodology. These events not only amplified our brand visibility but also strengthened our global reach.

Will you attend conferences in 2025? Same or more?

We plan to participate in more conferences/events in 2025 to show case our product and digital engineering along with semiconductors, and to meet global customers (USA, Asia-Pacific & Europe. We do understand the value of participating in events, to keep ourselves up to date on the latest technology, emerging products in the market, CAD tools and methodology. We will attend/participate in all the events that are relevant and help expand our business.

Contact Moschips
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Soitec: Materializing Future Innovations in Semiconductors

Soitec: Materializing Future Innovations in Semiconductors
by Kalar Rajendiran on 02-20-2025 at 6:00 am
Categories: 5G, AI, Automotive, FD-SOI, Foundries, Quantum Computing, Silicon Photonics, Soitec

ESG in the DNA of Soitec

The semiconductor industry continues to evolve rapidly to meet the escalating demands for speed, power efficiency, and miniaturization. As traditional silicon-based technologies reach their physical and performance limits, engineered substrates and advanced material innovation have emerged as pivotal drivers of the semiconductor revolution. These advancements are enabling breakthroughs in chip performance, power efficiency, and cost-effectiveness, while opening doors to transformative applications in mobile, automotive, artificial intelligence, and quantum computing.

Engineered substrates are specialized wafers designed to enhance device performance by tailoring the material properties to specific applications. These substrates often integrate multiple materials to create a hybrid platform that outperforms single-material alternatives. Silicon-on-Insulator (SOI) wafers are a prime example of engineered substrates that enhance performance by reducing parasitic capacitance and power consumption. SOI technology is widely used in high-performance and low-power applications, such as mobile processors and radio frequency (RF) devices.

Soitec has carved out a unique position at the intersection of materials science and semiconductor device manufacturing. With a commitment to innovation and sustainability, the company is playing an increasingly critical role in shaping the future of technology. It recently hosted its inaugural Substrate Vision Summit, and intends to hold it on an annual basis.

Pierre Barnabe, the CEO of Soitec, kicked off the Summit with his keynote talk to an audience of industry leaders and innovators exploring advancements in substrate technology and its future impact.

Soitec’s Leadership in Engineered Substrates

The company’s proprietary Smart Cut™ technology combines different layers of semiconductor materials at an atomic scale, unlocking unique properties tailored to a wide range of applications. This engineering approach enhances device intelligence, improves energy efficiency, and promotes a more responsible use of global resources.

Expanding Beyond Mobile to a Broader Semiconductor Market

Soitec initially gained recognition as a specialized provider of RF-SOI (Radio Frequency Silicon on Insulator) substrates for the mobile industry, particularly in smartphones. However, the company has significantly expanded its portfolio, reaching into new and diverse segments. Today, Soitec’s advanced materials are powering critical technological advancements in mobile communications, automotive applications, and artificial intelligence (AI).

Soitec’s Bold Vision for the Next Decade

Beyond its technological contributions, Soitec also stands out for its strong commitment to Environmental, Social, and Governance (ESG) principles, ensuring sustainable and responsible growth in the semiconductor industry. Soitec has set an ambitious goal for the coming decade: “to be the undisputed sustainable leader in engineered substrates, supplying the world with energy-efficient semiconductors.” This vision aligns with their commitment to sustainability and innovation, ensuring that the company continues to lead the industry in delivering high-performance, eco-friendly semiconductor solutions. Their team is continuously pushing boundaries, leveraging their leading technology and patent portfolio for a sustainable future.

Addressing Three Key Segments: Mobile, Automotive, and AI

Soitec’s expertise spans three primary market segments. In the mobile sector, the company is well known for its RF-SOI products, which are widely used in the smartphone industry, ensuring high-speed connectivity and performance. In the automotive industry, Soitec enhances system efficiency and extends the range of applications through FD-SOI (Fully Depleted Silicon on Insulator) technology, contributing to the growth of electric and autonomous vehicles. Additionally, in artificial intelligence, Soitec is driving advancements by equipping next-generation data centers with silicon photonics technology, a crucial component for enhancing AI processing capabilities.

Summary

As a leader in engineered substrates, Soitec is driving innovation that enables the next generation of semiconductors while also setting new benchmarks for sustainability and corporate responsibility. Its advanced SOI and Gallium Nitride (GaN) technologies are pivotal for the growth of AI, 5G, and automotive applications, all while reducing energy consumption and environmental impact.

With a strong ESG framework, Soitec is proving that technological excellence and sustainability can go hand in hand, reinforcing its role as a key player in both the semiconductor revolution and the global push for responsible business practices.

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Weak Semiconductor Start to 2025

Weak Semiconductor Start to 2025
by Bill Jewell on 02-19-2025 at 6:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

Semiconductor Market Change 2025

WSTS reported the global semiconductor market in 4th quarter 2024 was $170.9 billion, up 17% from a year earlier and up 3% from 3rd quarter 2024. The full year 2024 market was $628 billion, up 19.1% from 2023.

We at Semiconductor Intelligence give a virtual award for the most accurate semiconductor market forecast for the year. The criteria are publicly available forecasts released between October of the previous year and release of the WSTS January data in early March. For 2024 we have a tie. IDC in November 2023 projected growth of 20.2% in 2024. In February 2024, our Semiconductor Intelligence forecast was 18.0%. Thus, the final 2024 growth of 19.1% is halfway in between. Other forecasts made in this period ranged from 5% to 16%.

The 4Q 2024 revenue reports from sixteen major semiconductor companies varied widely. Nine companies reported increased revenues in 4Q 2024 versus 3Q 2024. Three companies – SK Hynix, Qualcomm and AMD – reported double-digit growth. Seven companies reported declines, with Infineon Technologies and Renesas Electronics reporting double-digit declines.

The companies providing guidance for 1Q 2025 revenue mostly expect declines from 4Q 2024. MediaTek, Infineon, Analog Devices, and Renesas expect low-to-mid single-digit growth. The other eight companies providing guidance expect declines, ranging from minus 2.4% for Texas Instruments to minus 27% for Kioxia. Factors cited for the declines included seasonality, excess inventories, weak demand, lower production and economic uncertainty. The weighted average revenue change for 1Q 2025 versus 4Q 2024 from the twelve companies providing guidance was a 9% decline. Over the last ten years, the semiconductor market has declined in the first quarter versus the fourth quarter nine times, ranging from minus 14.7% to minus 0.5%, averaging minus 5%. The only first quarter increase during this period was 3.8% growth in 1Q 2021 during the recovery from the 2020 pandemic. Thus, the 1Q 2025 revenue guidance appears worse than typical seasonality.

Given the expected slow start to the year, what is the outlook for the semiconductor market for the full year 2025? Forecasts released over the last three months range from our Semiconductor Intelligence’s 7.0% to 15% from IDC and Future Horizons. Our 7% forecast is an outlier, with other forecasts in the 11% to 15% range.

The factors driving our conservative outlook for 2025 are:

AI servers drove most of the semiconductor market growth in 2024 as shown in our December 2024 newsletter. They should remain strong in 2025, but at a significantly lower growth rate.

Key market drivers such as smartphones, PCs, automotive and industrial remain weak.

The global economy is uncertain in 2025 with the U.S. threatening increased tariffs on imports and other countries promising retaliatory tariffs. Increasing tariffs will increase costs for consumers, potentially resulting in decreased demand and/or increased inflation.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com

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Webinar: RF design success hinges on enhanced models and accurate simulation

Webinar: RF design success hinges on enhanced models and accurate simulation
by Don Dingee on 02-19-2025 at 10:00 am
Categories: EDA, Events, Keysight EDA

Modelithics 3D Library for RFPro increases the chances for RF design success

Traditional RF board design strategies based on circuit simulation worked at lower frequencies and relatively large spacing between components. Higher frequencies and densification dominate RF designs now, where corresponding wider bandwidths and tighter layouts with closely spaced components produce more complex 3D electromagnetic (EM) interactions. Relying on circuit simulation alone with simplistic models lacks sufficient accuracy and can result in costly re-spins. Keysight and Modelithics have teamed up for an advanced RF board simulation workflow in Keysight ADS and RFPro with 3D passive vendor component models supporting highly accurate, automated 3D EM-circuit co-simulation seeking better chances of RF design success.

WATCH REPLAY NOW: Maximizing RF Board Accuracy with 3D EM and Scalable SMD Circuit Models

Why 3D passive component models are needed

Keysight RF design teams often quote the phrase, “At high frequencies, with every resistor you buy, you get a free inductor.” It’s a bit of an oversimplification, but the point is valid. Packaged and soldered to a board, every passive resistor, capacitor, and inductor can introduce non-schematic parasitic resistance, capacitance, and inductance values. Higher frequencies and layout densities also increase the chances of electromagnetic coupling between components.

Unaccounted for, these parasitics and proximity EM coupling effects can shift circuit performance and frequencies. Circuit simulation alone might get spoofed into thinking all is well. Ultimate high-frequency RF board simulation accuracy depends on circuit and EM modeling and simulation working together. Without both simulation modes, the risks of board re-spins skyrocket. Designers may still be hesitant about increased simulation times in their workflow. Circuit simulation typically runs quickly, while EM simulation with more complex models, solvers, and a 3D volume to analyze usually takes longer.

Modelithics specializes in accurate equivalent circuit models for passive components. Each measurement-based model captures a part’s parasitics. Models then scale across all values of a part series. They also scale with respect to the substrate the part mounts on and the solder pad dimensions.

However, Modelithics goes a step further. “Our models fit directly into the ADS and RFPro workflow, allowing fast initial circuit simulation and optimization, followed by detailed EM simulation for highly accurate results,” says Chris DeMartino, Application Engineer at Modelithics. ADS and RFPro integration eliminates the need to manually connect EM simulation data to passive component models, building all required connections automatically to enable seamless EM-circuit co-simulation at will.

Moving from simulation to real-world board producibility

Both Keysight and Modelithics keep the goal in mind – simulation is a means to an end in producing an RF board assembly that works, and accuracy often is the difference between first-pass RF design success and a re-spin. Keysight uses Modelithics models and ADS with RFPro internally, with a recent example of an RF board design for the Keysight UXA Signal Analyzer. The 16-layer, 50 GHz design thoroughly illustrates RF board assembly complexity.

“Two things have to happen to make real RF board hardware – you need to find purchasable parts and then run accurate circuit-EM co-simulations with those parts in dense, multi-layer, high-frequency layouts,” says How-Siang Yap, Keysight EDA Marketing Manager for RF/MW solutions including ADS and RFPro. “Sweeping parameters like etching width, dielectric constant, and thickness and analyzing performance with the Modelithics component models get us first-pass layout success and confidence these RF board assemblies perform as advertised when produced in volume.”

Modelithics component modules start with actual manufacturer parts, such as TDK, Murata, or Coilcraft. Keysight ADS can use gradient followed by discrete optimization to find purchasable part values for resistance, capacitance, or inductance. These discrete values drive the selection of 3D components from the Modelithics library for highly accurate circuit-EM co-simulation with RFPro. The result is an accurately analyzed, sign-off-ready bill of materials for producing an RF board with first-pass success.

Stepping through component models and RF board simulation

Yap and DeMartino discuss the details of modeling and the need for 3D EM simulation in a SemiWiki webinar illustrating this enhanced RF board design workflow. One crucial finding they show is that circuit simulation diverges from EM simulation in dense layouts as EM coupling effects increase between passive components, missing the performance degradation.

The integrated circuit and EM simulation workflow of Keysight ADS, RFPro, the Modelithics Microwave Global +3D model library, and the discrete optimization capability give designers a significant advantage for RF design success no other EDA environment offers today. Registration for this webinar is open now:

WATCH REPLAY NOW: Maximizing RF Board Accuracy with 3D EM and Scalable SMD Circuit Models

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2025 Outlook with Paul Wells of sureCore

2025 Outlook with Paul Wells of sureCore
by Daniel Nenni on 02-19-2025 at 8:00 am
Categories: IP, sureCore

Paul Wells sureCore photo

Paul Wells, CEO at sureCore, an ultra-low power memory specialist, has been involved in the semiconductor industry for over 35 years. Previously, he has worked as Director of Engineering for Pace Networks where he led a multidisciplinary product development team creating a broadcast quality video and data mini-headend. Before this, he worked for Jennic Ltd as VP Operations, successfully building the team from scratch as the company transitioned to a fabless model. Prior to this, he was responsible for a team at Fujitsu Microelectronics supporting ASIC customers in Europe and Israel.

Tell us a little bit about yourself and your company. 

I’ve been in the semiconductor industry now for over 35 years. I began my career at Ferranti Electronics in Manchester, UK, as an ASIC engineer delivering custom chips for a wide range of innovative consumer applications. Ferranti had invented the gate array and the possibilities for its use seemed endless. I also worked for Fujitsu, Jennic and Pace Networks, holding senior engineering and operations positions, before co-founding sureCore and taking on the role of CEO back in 2011.

SureCore started out by taking a radically different view of memory. All SoC devices need embedded memory, usually SRAM, but also register files, and occasionally ROM. With the growing trend to even more integration, and the need to be able to accommodate larger software footprints, the demand for on-chip memory just kept increasing until for some devices it reached 70% die area! SRAM whilst fast is also power hungry and by analysing the traditional architectures we were able to identify some key power saving strategies that resulted in up to 50% dynamic power savings.

For many consumer and medical products, the performance delivered by modern process nodes is often overkill. Very significant power savings can be achieved by operating at much lower voltages and sureCore have been able to develop and demonstrate in silicon the industry’s lowest operating voltage SRAM. These power optimising technologies are embedded in our market-leading PowerMiserTM and EverOnTM product families. By exploiting our ultra-low power design expertise, we have created our sureFITTM custom memory development service that provides our customers with the optimal solution for their application.

What was the most exciting high point of 2024 for your company? 

Throughout 2024 sureCore delivered a number of custom advanced memory implementations, including a low power memory compiler for 16nm FinFET.

SureCore also continued to lead on the cutting-edge government funded InnovateUK project to develop cryogenic IP for quantum computers. We successfully taped-out a cryogenic IP demonstrator – our test chip which included cryogenic SRAM, register files and ROM based on the GlobalFoundries 22FDX process. As part of the seven member consortium transistor parameters were measured at both 77K and 4K, and SPICE models updated using advanced TCAD. We received samples in November and the great news is that the devices are working extremely well. We already have a lead customer who has proven that the IP works at 3.3K and we just need to complete the full chip characterisation to fully validate the compiler space.

What was the biggest challenge your company faced in 2024? 

After a buoyant 2022, 2023 and early 2024 presented very challenging market conditions for the semiconductor industry. Geopolitical issues and the ever increasing importance of semiconductors to the global economy turned out to be a double-edged sword, with restrictions being imposed on advanced manufacturing equipment sales whilst the Chips Acts in both Europe and the US pumped money into the industry. However, this funding seems so far to have done little to stimulate the sector. Despite these challenges, sureCore have managed to successfully navigate the downturn. In fact, we saw an upsurge in business, especially our specialist design services, in the third and fourth quarters.

How is your company’s work addressing this biggest challenge? 

SureCore’s ultra-low power memory solutions can provide our customers with a competitive advantage in the market. Battery powered products in particular continue to evolve, with Edge AI applications, smart watches and health monitors pushing the boundaries of what is possible in small form factor devices. With the upturn in the 2nd half of 2024 and extending into 2025 we are now seeing increased interest in how our novel power saving technology can help developers meet their ever tightening power budgets. We have global representation and continue to attract new customers from across Asia, the US and Europe.

What do you think the industry’s biggest growth areas will be in 2025?

Unfortunately, the outlook for the global economy is still not very encouraging. However, the current enthusiasm for AI continues unabated and this will almost certainly be the big growth driver in the semiconductor industry in 2025. Edge AI is likely to progress if only as a way to offload some of the pressure on data centres. We also believe that smart medical and healthcare solutions will gain further traction as the baby boomer generation starts to really focus not just on ‘life-span’ but on ‘health-span’ extension.

What about industry conferences and events?

Last year we prioritised the foundry events, attending TSMC Technology Symposiums and OIP events, in addition to the GF Technology Summits. As usual these events were well attended and provided excellent networking opportunities. In 2025, we plan to attend several industry events – certainly the foundry events. We are also looking at Embedded World and DAC.

What will be the main product focus areas for your company in 2025? 

The sureCore team will continue to innovate in the ultra-low power memory market, addressing the key issues of both dynamic and leakage power. The cost-effectiveness of both 16nm and 12nm technologies is becoming a key focus for us as product companies are increasingly recognising their benefits. We are also working with lead customers down to 4nm and it is encouraging that our power saving technology seems to migrate well to these more advanced nodes. In addition, although the quantum computing market is still in its infancy, we will continue to push our cryogenic design expertise and engage with as many companies in this sector as possible. 2025 looks set to be another exciting year for sureCore, with many interesting customer projects and deliveries in the pipeline – so watch this space!

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Arteris Raises Bar Again with AI-Based NoC Design

Arteris Raises Bar Again with AI-Based NoC Design
by Bernard Murphy on 02-19-2025 at 6:00 am
Categories: AI, Arteris, IP

Arteris FlexGen example min

Modern semiconductor devices, a far cry from the chips we once knew, are now highly complex intelligent systems used in datacenters, communications infrastructure, in consumer electronics, automotive, home and office automation, almost everywhere. All such applications build around large subsystems, invariably compute, often AI, sometimes vision/audio engines, always memory and communications subsystems, and more. Each subsystem hosts its own network-on-chip (NoC) connecting sub-functions together, as does the top-level design to connect between subsystems. These structures commonly incorporate a hierarchy of 5-20 NoCs per die/chiplet.

Even when the full system builds entirely on subsystems proven elsewhere, new spec and floorplan constraints may require several of these NoCs to be redesigned or refined, a potentially huge task impacting product schedules. Arteris’ AI-based NoC IP generator, FlexGen, aims to address this challenge. Rick Bye (Director of Product Management, Arteris) and Andy Nightingale (VP Product Management, Arteris) shared their insights with me.

(Source: Arteris, Inc.)

AI for Full-Chip NoC Optimization

We’re already seeing a trend to use AI in global optimization for electronic design: in physical design, in board design, in multiphysics analysis and optimization. These are all problems with huge search spaces, not amenable to traditional optimization techniques, better suited to heuristics learned over trials on historical data.

NoC optimization over a hierarchy of NoCs looks like a very similar problem. Optimizing based on learning over a range of topologies, floorplans, performance and QoS goals, drawing on prior experience which I bet Arteris has in abundance given the years they have been in this business. Then given a new design and network objectives with constraints defined at least to initial estimates, they are able to generate implementations of all those NoCs at the push of a button. I am told this is exactly what their field AEs do to launch evaluations. Pretty neat.

The Caveat

Automating the whole NoC design task through to signoff sounds ideal but reality is never quite that simple. Others have offered this hope but always fall short in lack of repeatability. Optimization may generate significantly different solutions between different design drops, improved certainly in some respects but adding new chaos in floorplanning, timing, QoS, on each new drop. Moreover, constraints provided to guide optimization are never complete, and lack understanding of some system objectives, design expert experience, even future product line objectives.

Automating generation is a very important step forward but it must allow for experts to provide incremental manual overrides where they see a need, and those manually supplied constraints should persist as the design evolves. The Arteris team stressed that this repeatability is why the current FlexGen is based on ML rather than a fancier AI foundation model. Given what I know of AI today, I can understand their caution.

That said, the objective of AI-centric generation is still to find a better PPA solution, faster. On the “faster” metric, Arteris claim generation times dropping from 20 hours to 4 hours, early optimization time (initial trials against a rough floorplan) dropping from 3 hours to 10 minutes and final optimization dropping from 2 weeks to 100 minutes. Even better, such turnaround times enable design teams to explore a wider range of options, getting to better global optima from topology generation to final signoff.

Results

Those are the claims, how does FlexGen deliver in practice? Arteris ran trials on an in-house design (shown above), comparing on manually optimized FlexNoC implementations, tuning against different objectives to explore a range of possibilities. Optimizing just for wire length, they were able to drop total length from over 300 meters to just over 100 meters. Not a very realistic objective of course since this does not factor in performance but is still useful to see where the boundary is. An optimization acknowledging all performance goals still dropped total wirelength to 280 meters, a 10% reduction, with consequences for latency, power and area – improved PPA. Incidentally, a 10% optimization is very much in line with other AI optimizers in EDA.

Dream Chip Technologies used FlexGen on one of their designs, again comparing with a prior FlexNoC implementation. They found a 26% reduction in total wire length, 28% reduction in the longest wire, a 5% reduction in latency, 51% reduction in max latency and a 3% reduction in area. Again, improved PPA. All with a 10x boost in productivity versus effort invested on the manual implementation.

I’m impressed. Automated optimization delivering real improvements but within tightly controlled bounds to preserve repeatability. You can read the press release HERE and explore the product in more detail HERE.

Also Read:

Arteris Raises Bar Again with AI-Based NoC Design

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2025 Outlook with Veerbhan Kheterpal of Quadric

2025 Outlook with Veerbhan Kheterpal of Quadric
by Daniel Nenni on 02-18-2025 at 10:00 am
Categories: AI, IP, Quadric

Veerbhan Kheterpal

Quadric Inc. is the leading licensor of general-purpose neural processor IP (GPNPU) that runs both machine learning inference workloads and classic DSP and control algorithms.  Quadric’s unified hardware and software architecture is optimized for on-device ML inference. Veerbhan Kheterpal is the CEO and one of the co-founders of Quadric.

Tell us a little bit about yourself and your company.

Quadric is a startup processor IP licensing company delivering a unique general-purpose, programmable neural processor (GPNPU) IP solution. In a marketplace with more than a dozen machine learning “accelerators,” ours is the only NPU solution that is fully C++ programmable. This means that it can run any and every AI/ML graph without the need for any fallback to a host CPU or DSP.  I am one of the three co-founders of the company, which we started back in late 2017.

What was the most exciting high point of 2024 for your company?

2024 was a year of tremendous momentum building for Quadric.  We introduced and began customer deliveries of the 2nd generation of our Chimera GPNPU processor, which now scales to over 800 TOPs.  We also dramatically expanded the size of our model zoo (available in our online DevStudio at our quadric.io website) from only 20 models at the start of the year to over 200 by the close of 2024 thanks to the rapid maturation of our compiler stack.  And that maturation of the technology was accompanied by a growing customer base, that included a public announcement by Denso Corp of Japan that they are basing their future ADAS systems on our GPNPU processors.

What was the biggest challenge your company faced in 2024?

2024 witnessed the beginning of the thinning of the herd of rival NPU architectures in the marketplace.  Far too many IP startups and large IP players all launched AI/ML accelerator efforts from 2020 through 2023 – too many for the market to support them all.   Quadric’s goal in 2024 was to gain the necessary traction in the market to become one of the survivors of the shakeout, and to thrive amid that big shakeout.

Indeed, we did thrive!  We grew the team. We grew the customer base.  We greatly expanded the scope of the product.  We grew revenues by over 600%. And we just kicked off 2025 by forming a Japanese K.K. subsidiary and opening a physical office in Japan – so I think we met the challenge of 2024 head-on and succeeded!

How is your company’s work addressing this biggest challenge?

The challenge of surviving the inevitable thinning of the herd was really a question of highlighting and enhancing the thing that makes Quadric unique among AI/ML solutions: the Quadric Chimera GPNPU is 100% programmable, capable of running any and all ML workloads.  In detailed evaluation after detailed evaluation, we shined by rapidly porting dozens of new, leading-edge models to the platform – many of which compiled straight out of the box with no manual intervention.  The resulting massive increase in the size of the known-working model zoo throughout 2024 cemented in customers’ minds that the promise of full programmability with high performance was a reality, not just a promise.

What do you think the biggest growth area for 2025 will be, and why?

Every year we marvel at how fast AI models changed the previous year.  And every year the industry buckles up for a wild ride to see how much change hits in the coming year.  2025 is no different – in fact, 2025 has already seen huge changes.  DeepSeek so disrupted the conventional wisdom that stock markets quaked, politicians pontificated, and technologists paused to wonder.  And that was only within the first 4 weeks of the year!

These changes won’t slow down.  Look at the automotive market, for instance.  One year ago none of the leading OEMs and Tier 1s had vision-language models (VLMs) on their Must Have list.  VLMs at the time were barely registering in academia.  Now, VLMs are fast becoming requirements.

How is your company’s work addressing this growth?

Quadric welcomes rapid change in AI models.  Quadric processors can run every ML operator, every ML graph.  The more change the better for our business!   Quadric is continuously adding ports of new algorithms to our processors. Today we support all the major modalities of ML inference, including a variety of leading-edge transformers.  Adding a demonstration of a new ML model is a pure software effort for us, and we are focused in 2025 on widening the array of models further with each periodic software release.

What conferences did you attend in 2024 and how was the traffic?

In 2024 we attended quite a few smaller, focused technical conferences: Embedded Vision Summit, IPSoC, ACC, Innovex (part of Computex), Design Solution Forum, EdgeTech, and we held two of our own private seminars.   Those tailored conferences were robustly attended and the big mega shows – such as CES – also did well.

Will you attend conferences in 2024? Same or more?

Quadric will be expanding our outreach marketing programs in 2025 commensurate with our business growth.  Look for us to be at more events and more prominent sponsors of those venues that bring together the chip and systems architects that make programmable processor IP decisions.

How do customers engage with your company?

The first step is easy: visit our online DevStudio at www.quadric.io.  We have hundreds of benchmark performance figures – and full source code of all those benchmarks – right on the website in Studio.  And our worldwide sales and applications team stands ready to follow-up with training and support to help you decide if Quadric’ Chimera GPNPU processor is right for your next SoC design.

Also Read:

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Samtec Advances Multi-Channel SerDes Technology with Broadcom at DesignCon

Samtec Advances Multi-Channel SerDes Technology with Broadcom at DesignCon
by Mike Gianfagna on 02-18-2025 at 6:00 am
Categories: Events, Samtec, Semiconductor Services

Samtec Advances Multi Channel SerDes Technology with Broadcom at DesignCon

There were many announcements and significant demonstrations of new technology at the recent DesignCon. The show celebrated its 30th anniversary this year and it has grown quite a bit. As in past years Samtec had a commanding presence at the show. There will be more about that in a moment, but first I want to focus on a substantial demo that teamed Samtec’s interconnect technology with Broadcom’s SerDes technology for the first time. I have many memories of my time at eSilicon. Some of those memories center on how difficult it was to compete with Broadcom’s SerDes. The demo at DesignCon brought together this substantial capability with Samtec’s industry-leading interconnect to open new horizons. Let’s examine how Samtec advances multi-channel SerDes technology with Broadcom at DesignCon.

Interconnect Technology

The key enabling technology from Samtec for the DesignCon demo with Broadcom was its Si-Fly® HD 224 Gbps PAM4, co-packaged and near chip capabilities. As the name implies, these products offer the system designer flexibility with either co-packaged interconnect with the chip on the same substrate or near-chip interconnect. The die and connector on substrate configuration creates the need for broader ecosystem collaboration since the silicon provider, interconnect provider and OSAT all need to work together to achieve a reliable product. Broader collaboration is a trend in advanced design styles like this.

The image at the top of this post shows what these connectors look like.

To get to high-density 224 Gbps PAM4 channel capability, the co-packaged option offers the lowest loss signal transmission from the package to the front panel or backplane while providing the highest density. Samtec’s Eye Speed® Hyper Low Skew Twinax cable technology supports 224G signaling with an industry leading 1.75 ps/m max intra-pair skew. Digging a bit deeper, placement of Flyover® cable solutions on, or near, the chip package improves transmission line density and extends signal reach in high-performance applications. More information on this technology and the demo is coming.

The Demo

The demo at DesignCon showcased an evaluation platform with Broadcom’s 200 Gbps SerDes technology. The Samtec Si-Fly HD CPC on-package high-speed cable systems and OSFP front panel connectors were used for the interconnect. The Broadcom 200 Gbps chips and these connectors were attached to the package to maximizes system performance.

For those who want the details, here they are for the two demo platforms that were used.

Platform #1

  • Evaluates the performance of the new Si-Fly HD cable assembly
  • The 200 Gbps signal routes through 30 mm of substrate and loops back through 150 mm of Samtec Eye Speed Hyper Low Skew twinax cable
  • BER is e-13, error-free. Total channel loss is 20 dB at 212.5 Gbps

Platform #2

  • Mid-board to front panel and back
  • 200 Gbps signal travels through Si-Fly HD cable assembly (25 cm Eye Speed Hyper Low Skew Twinax) with OSFP front panel connector
  • One meter DAC cable, rated at 224G
  • BER e-9, total channel loss 48 dB at 212.5 Gbps
  • Performance will improve with release of 224G Flyover OSFP

A photo of the demo running live at the show is shown below. Note there is a link coming to a detailed video of this demo done live from the Samtec booth at DesignCon.

Samtec/Broadcom Demo at DesignCon

Samtec at DesignCon

As I discussed previously, Samtec has a tendency to dominate DesignCon. This year was no different. Beyond the compelling demos at the Samtec booth, Samtec products were also featured in demos with its partners throughout the show floor. In particular, there were noteworthy demos at the Rohde & Schwarz and Keysight booths.

Samtec was also quite visible in the technical program with the following contributions.

Panels

  • PCI Express & PAM4: Balancing Silicon & Interconnect Interdependencies for 128 GT/s
  • Expert Discussion: How Will AI Applications Affect High Speed Link Design?

Presentations

  • Reduced Order Geometric Macro Model of PCB Fiberglass Spatial Variation for Skew & Impedance Prediction
  • Transmitter Power Spectral Density Noise Impact for 200 Gb/s PAM 4 per Lane
  • Direct to Substrate 200G-PAM4 Co-Packaged Connectors: Is it a Reality?
  • Beyond 200G: Brick Walls of 400G links per Lane
  • Accurate Adapter Removal in High Precision Low Loss RF Interconnect Characterization
  • Determining the Requirements, Die vs Package vs Board: Multi-Level Power Distribution Network Design

To Learn More

You can learn more about Samtec’s Si-Fly HD co-packaged and near-chip systems here. You can also learn about another 224 Gbps PAM4 effort with Synopsys here. And finally, you can check out the live video of the important demo with Broadcom here.  And that’s how Samtec advances multi-channel SerDes technology with Broadcom at DesignCon.

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Outlook 2025 with David Hwang of Alchip

Outlook 2025 with David Hwang of Alchip
by Daniel Nenni on 02-17-2025 at 10:00 am
Categories: 3D IC, AI, Alchip, Chiplet, Semiconductor Services

Dave Huang

Dave Hwang joined Alchip in 2021 as General Manager of Alchip’s North America Business Unit.  He also serves as Senior Vice President, Business Development.  Prior to join Alchip, Dave served as Vice President, Worldwide Sales and Marketing for Global Unichip and in a variety of management and technical roles at TSMC.  He holds a Ph.D. in Material Science and Engineering from North Carolina State University.

What was the most exciting high point of 2024 for your company?

That’s a great question.  It’s been a very hectic year, for sure.  Alchip will, more than likely, achieve over $1 billion in revenue in 2024. That’s a huge milestone for any company.  But the biggest, most important milestones are our 2nm shuttle tape-out in September and our 3DIC design flow readiness, which we will announce in January.

What was the biggest challenge your company faced in 2024?

By far, the biggest challenge has been finalizing the design flow for advanced packaging, which has its own set of unique challenges.  We’ve brought a new level of flexibility to our design platform to accommodate increasingly specific targets for both power consumption and high performance.

How is your company’s work addressing this biggest challenge?

Ultimately, in the end, we introduced, and are now accepting designs, for our 3DIC design flow that has both flexibility and robustness.  Alchip’s silicon-proven 3DIC design flow optimizes 3DIC designs along three critical dimensions: power delivery, die-to-die electrical interconnect, and system-wide thermal characterization.

What do you think the biggest growth area for 2025 will be, and why?

System companies, no doubt have become huge consumers of ASICs.  They see them as critical differentiators, particularly in AI and HPC applications.  We’re fairly aligned with the thinking that, in the not-too-distant future, system company investments in the development of ASICS are estimated to reach over several million AI chips in 2027-2028, creating a $60-$90 billion market.

How is your company’s work addressing this growth?

We are taking a holistic systems approach, developing a design platform to accommodate advanced packaging, advanced chiplet, and advanced process technologies.  We’re doubling down on adding engineering and resources throughout our global design centers to address market-specific HPC, AI, and automotive demand.

What conferences did you attend in 2024 and how was the traffic?

We take a significant presence in all TSMC events … The TSMC Technology Symposiums and OIP.  And we do it globally.  We also exhibit at industry events like Chiplet Summit and the AI Hardware Summit.

Will you attend conferences in 2025? Same or more?

We’ll add the Open Compute Platform to our plan, and we’ll look next to expand our presence in industry events and conferences.

How do customers engage with your company?

There is no one way.  Nearly every company is different, so we take a true ASIC approach and have a strategic flexible engagement model.  This allows companies to engage in multi-ways, through many entry points along the value chain.  Essentially, we customize the ASIC value chain to meet the specific needs.

Additional questions or final comments? 

Without a doubt, the AI/HPC market is the place to be.  The key differentiator will be advanced packaging, which will be absolutely required in all high-performance computing applications.  We see ourselves as leaders in this area.

Also Read:

Alchip is Paving the Way to Future 3D Design Innovation

Alchip Technologies Sets Another Record

Collaboration Required to Maximize ASIC Chiplet Value

Synopsys and Alchip Accelerate IO & Memory Chiplet Design for Multi-Die Systems