If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
Continue reading “TSMC’s DFM Announcement”
So, Why Not Just Write Better Rules?
In my submission about TSMC making some DFM analysis steps mandatory at 45nm (see “TSMC’s DFM Announcement”), I ended with a question about why the foundries can’t just write better design rules (and rule decks) to make sure all designs yield well. Here’s my take on this complicated question.
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TSMC’s DFM Announcement
If you are a TSMC customer, no doubt you have heard TSMC is requiring lithography and planarity analysis for all 45nm designs. Their website says customers can either run it themselves, or contract TSMC services to do it. The most cost-effective way would be for the customers to run it themselves, but some might not have the resources to do that. Of course, by the time you pay TSMC to do it 3 or 4 times, you could have bought some tools and run it yourself. That’s good for Mentor and other EDA vendors, right? Probably, but there has to be more to it than that.
Continue reading “TSMC’s DFM Announcement”
Effects of Inception
I finally got to watch the critically acclaimed sci-fi movie “Inception” last weekend and life has not been the same since. Without giving away too much detail for the benefit of those who have not watched it yet, the main plot involves dreams within dreams within dreams – three levels to be precise—to “incept” an idea into someone’s subconscious mind. Are you still with me? Never mind, the first thing that came to my mind when I was exposed to the concept of dreams within dreams was – nested domains in multi-voltage (MV) designs. Blame the nerd gene for triggering this reaction, but the truth remains.
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Semiconductor Manufacturing International Corporation 2010
In celebrating the 10th anniversary of SMIC, CEO David Wang ushers in a new era of China semiconductor manufacturing with triumphs versus promises. By triumphs David means profits, which SMIC saw for the first time in Q2 2010. The future looks even brighter for SMIC as the China semiconductor demand versus supply gap is an estimated $30B versus $3B.
SMIC is definitely positioned for growth with 10k+ people and $1.5B in 2010 revenue versus $1B in 2009. 2010 has been a banner year for the foundry industry with close to $30B in total revenues, which is approximately 10% of the $300B in total semiconductor revenue. Outsourcing from semiconductor IDM’s (fab-light strategy) continues to push foundry growth as well as mobile internet devices and emerging markets in China, India, and South America. It is interesting to note that Cadence CEO Lip-Bu Tan is on the SMIC board of directors. Lip-Bu’s Walden Venture Fund is heavily invested in the China fabless semiconductor market and he can spell cloud computing, so expect a strong move from Cadence in China.
Other interesting datapoints:
2010 Numbers
Electronics $1.36T +12%
Semi $300B +31.5%
EDA $5B +0%
CAPS $41.8B +90%
Fab Equip $28B +120%
SMIC Revenue
60% USA
30% China
10% Taiwan, UK, Israel, Korea
20% 90nm and below
Capacity Expansion Plans
8” 150k per month
12” 130/90nm 20k
12” 65/55nm 60k
12” 45/40nm 50k
12” 32/28nm 60k
Aart De Geus was the keynote speaker with an updated version of his: Systemic Collaboration: The New Smart Skill presentation. This presentation is looking more and more like an EDA360 pitch! I actually experienced déjà vu from conversations with EDA360 Chief Anarchist John Bruggeman!
One of Aart’s slides highlighted the System, SoC, and Silicon Realization companies Synopsys had acquired over the years, an impressive list for sure. In fact, Synopsys dedicates 20%+ of revenue on M&A activity (inoraganic growth) versus 30%+ on R&D (organic growth). Unfortunately the Synopsys “Realization” strategy is FPGA based which will never work for bleeding edge semiconductor products that account for 90% of the silicon shipped in a year. The Cadence EDA360 vision is simulation/emulation based which is much better suited for “Realization”. Correct me if I’m wrong here Synopsys fans, this is just my impression/opinion.
The importance of IP re-use was also mentioned in regards to the increasing quality (yield) and time to market pressure the semiconductor industry faces. Better IP equals better yield, better yield equals time to market and better margins. As Aart says, the semiconductor design ecosystem is systemic. The results are not a SUM but a PRODUCT. If anywhere in the semiconductor design and manufacturing equation there is a zero, the results will be a bad wafer, die, chip, or electronic device, which supports the increasing importance of IP re-use.
I’m a Semiconductor IP person by experience and have blogged about it many times, and will do it again next week. Soft and hard IP cores continue to have a profound impact on SoC design. The trend I see is more soft IP versus hard, which presents a different type of qualification and integration challenge, but more on that next week.
TSMC OIP Conference 2010 Critique!
Okay, this is more of a, “What I would do if I was TSMC” than a critique, but I needed a one word descriptor for the title. This was the third TSMC OIP Conference and I would guess about 250 people attended. This was the first time I have seen TSMC in “reactive” mode versus “proactive” leadership mode, so I was a bit disappointed. TSMC is THE industry leader and should NOT be looking in the rear view mirror at competitors that are barely visible.
The semiconductor landscape has dramatically changed during the contraction phase of the current business cycle. The strong got stronger by acquisition and aggressive business practices, and the rest of the fabless semiconductor companies either were: acquired, got smaller, or became IP companies. So TSMC, being a customer driven company, must also change strategies and the Open Innovation Platform IS the delivery system for that change.
The Pareto principle (also known as the 80-20 rule or the law of the vital few) states that, for many events, roughly 80% of the effects come from 20% of the causes. For semiconductors this is definitely the case. In fact, as a result of the recent economic chaos and consolidations I would guess that 90% of the silicon is shipped by 10% of the companies.
The foundry strategy for the top semiconductor companies is three-fold: Early Access, Capacity, and Wafer Pricing. TSMC is working hard on capacity and wafer pricing 24/7, believe it! There is no doubt in my mind that TSMC will continue to be the capacity and margin leader for 40nm, 28nm, and 20nm, which will keep the top foundry customers engaged. Early access however is a continuing challenge. For example, Design Rule Manuals (DRMS) are still in PDF format, 1,300+ pages long, and rapidly changing. Some of the rules are so complicated they are impossible to describe, and even harder to code and communicate, even within the foundry teams. This should be the focus of the TSMC OIP for the top semiconductor companies, a more automated and simplified information exchange, one that uses vendor neutral formats so customers cannot be held hostage by short sighted EDA vendors. The iPDK initiative is an excellent start but there is much more that can be accomplished.
For the other 90% of the semiconductor companies, the ones that cannot afford to develop custom design flows, PDK’s, and IP, the ones that cannot afford an in-house foundry team for early access, TSMC OIP is a critical enabler. Unfortunately, one of the messages of the conference was, “TSMC will not compete with partners”, which was a clear response to public relations pressure from the GlobalFoundries mantra, “We don’t compete with partners!”
Competition is what has made the semiconductor industry and semiconductors themselves what they are today! Competition is what drives innovation and keeps costs down. Not destructive competition, where the success of one depends on the failure of another, but constructive competition that promotes mutual survival and growth where everybody can win. The semiconductor design ecosystem is the poster child for destructive competition, which is why EDA ( SNPS, CDNS, MNTR, LAVA) valuations are a fraction of what they should be.
The TSMC Open Innovation Platform should be the cornerstone of the semiconductor design ecosystem. The ecosystem must NOT hold designers hostage with proprietary formats! The ecosystem MUSTinnovate to compete! The TSMC Open Innovation Platform MUST lead the way! TSMC is the #1 foundry and that will not change within my lifetime. TSMC must also be #1 in customer satisfaction and the design ecosystem ISwhere customer satisfaction begins.
Critical Area Analysis and Memory Redundancy
Simon Favre, one of our Calibre Technical Marketing Engineers, presented a paper on Critical Area Analysis and Memory Redundancy at the 2010 IEEE North Atlantic Test Workshop in Hopewell Junction, NY, just up the road from Fishkill. As Simon says…
Fishkill, New York. IBM is in Fishkill. IBM invented Critical Area Analysis in what, the 1960’s? Venturing into IBM country to speak on CAA is kind of like being the court jester. Fortunately, no one said, “Off with his head.” 🙂 But seriously, it amazes me how little is known about this topic.
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Semiconductor Forecast 2010-2011 Update!
It’s that time of the quarter again, where the semiconductor analysts revise forecasts, passing off glorified guesstimates as valid financial planning data. They aren’t forecasts! They are observations! I blame these hacks for the 12.5% Silicon Valley unemployment rate! I blame these hacks for the dwindling available capitol for emerging fabless, EDA, and IP companies. I even blame these hacks for global warming! Okay, maybe not global warming, but the other stuff for sure!
iSupply is first out of the gate with a downward observation (forecast) of 32% versus 35%. Semiconductor revenues around the world are now expected to hit $302 billion this year, a gain of 32 percent from $228 billion in 2009. This drop is attributed to “weaker consumer demand for certain electronic devices and higher industry inventory” rather than “just bad forecasting”. Revenue in the fourth quarter is expected to drop by 0.3 percent, which will be the first sequential drop since the semiconductor market took an “unforecasted” nose dive in the fourth quarter of 2008 and first quarter of 2009.
TheSemiconductor Intelligence observation (forecast) was 36% so expect a revision from Bill Jewell. Bill also warns us that, according to National Bureau of Economic Research (NBER), the current recession is the longest since World War II:
- July 1981-November 1982: (14 months)
- July 1990-March 1991: (8 months)
- March 2001-November 2001: (8 months)
- December 2007-June 2009: (18 months)
The NBER is generally seen as the authority for documenting US recessions and defines them as:
“a significant decline in the economic activity spread across the country, lasting more than a few months, normally visible in real GDP growth, real personal income, employment (non-farm payrolls), industrial production, and wholesale-retail sales.”
By definition, the end of a recession means the U.S. economy stopped contracting and not when it reaches the level it was at the start, so we have a way to go yet. The US Real GDP & Durable Goods graphic is based on data from the U.S. Department of Commerce and shows the quarterly U.S. real gross domestic product (GDP) indexed to 4th quarter 2007, the peak prior to the recession.
Speaking of the semiconductor ecosystem, next week I will be at the 2010 TSMC OIP Partner Forum on Tuesday and the SMIC 2010 Technology Symposium on Friday, two free lunches, the life of a world famous blogger! It would be a pleasure to meet you, that is, of course, if you recognize me without the Porsche hat!
TSMC GigaFab Tour!
During my most recent Taiwan trip I was not only afforded a meeting with Dr Mark Liu, Sr VP of TSMC, a guided tour of GigaFab #12 was also included. Even more impressive, I’m now considered “Elite” by Eva Airlines so I automatically get the good seats, better food, and VIP service. My wife, however, is not impressed with my Elite status so I still have to do chores around the house.
Mark Liu ramped up TSMC’s first 200mm fab in 1993 and has been building fabs for TSMC ever since. Mark’s favorite topic is the 300mm GigaFabs, Fab#12, Fab#14, and Fab #15 which TSMC just broke ground on last month. Clearly TSMC has learned a valuable lesson from the 40nm wafer shortage experience. Not having enough capacity is far more costly than having too much. After 40nm, customer priorities have certainly changed: Capacity is now the 1st concern with price a close 2[SUP]nd[/SUP], and last but not least design enablement. Please note that the perceived value of semiconductor design enablement is often overlooked but it is clearly the key enabler to TSMC’s expansive customer base.
After putting on the clean room space suit and being lightly air washed I entered a GigaFab for the first time and was literally speechless. If you know me personally, being speechless is not one of my strong suits so this was a new experience.
The insignias on the machines were logos and acronyms that I recognized but what struck me was the total automation of a GigaFab. Machines outnumbered man exponentially with 99% automation. Shuttles zoomed around on tracks above delivering thousands of 40nm wafers to the 300+ steps in the semiconductor manufacturing process. The few people I did see were at monitoring stations. Even more impressive than the billions of dollars of hardware in a GigaFab, is the millions of lines of software developed to run it: Automated Material Handling Systems (AMHS) for transporting, storing, and managing semiconductor wafer carriers and reticles plus Manufacturing Execution Systems (MES) software to manage overall production efficiency.
This year TSMC will spend a record $5.9B on capital expenditures. Approximately 75% will be used to expand TSMC’s 65/40/28nm technology capacity and 15% will be used for mainstream processes. The remainder will be used for equipment, R&D expenses, and new business such as solar and LED. TSMC’s newest Gigafab, Fab 15, will cost an estimated $9.4B. TSMC is also set to complete Phase 5 expansion at Fab 12, and Phase 4 expansion at Fab 14.
According to the most recent management report, TSMC has accelerated its capacity expansion plan for 2010. Total managed capacity was 2,749K 8-inch equivalent wafers in 2Q10, increased by 7% from 2,566K in 1Q10. Current capacity plan calls for an overall increase by 14% to 11,299 8- inch equivalent wafers, compared with 11,247 8-inch equivalent wafers planned in the last quarter.
Demand for TSMC’s advanced technology wafers in all major semiconductor market segments again increased quarter to quarter. Among the advanced technologies, 40nm not only increased an additional 2% of TSMC’s revenue share, the output of Gigafab wafers processed using 40nm technology increased by 30% sequentially.
The 40nm race is officially over, TSMC wins by a landslide in regards to capacity, price, and design enablement. The race for 28nm dominance however is still on between TSMC, Samsung, and GlobalFoundries. Samsung is in production at 32nm so moving to 28nm should just be a process shrink. For TSMC and GlobalFoundries, 28nm is a completely new node which will bring new technical challenges. Still, in my opinion, the foundry race to 28nm is too close to call today and it will certainly be an exciting finish!
Semiconductor Realization!
Insanity is doing the same thing over and over again and expecting different results (Albert Einstein). Given that statement, according to John Bruggeman (Cadence CMO and EDA360 Chief Anarchist) the semiconductor industry is INSANE!
This year the EDA Tech Forum and the Global Semiconductor Alliance Expo were not only on the same day, but also at the same location, which saved me a trip to the Santa Clara Convention Center but the conference session overlap was INSANE!
The award for the best panel definitely goes to the GSA: From MIDs to Base Stations – Where Mobility Infrastructure Meets Innovation, featuring heavy weight semiconductor executives from fabless companies around the world: Scintera, NetLogic, PicoChip, Altera, and eSilicon. The fifth panelist was John Bruggeman!?!? Whoever put John B. on this panel is INSANE!
First let’s look at the semiconductor problem statement best illustrated by Aart Degues, Synopsys CEO, in last week’s blog:
It’s an INSANE attempt at bottom-up design where you try to find a vegetarian restaurant while avoiding your level 12 vegan mother in-law (been there, done that). It’s a complicated and somewhat treacherous trip through System, SoC, and Silicon design and implementation. Unfortunately, this trip is getting longer and more expensive every day which has officially qualified semiconductor design starts and fabless semiconductor start-ups as endangered species.
Enter EDA360. I now consider myself an EDA360 expert since I have read the vision statement 360 times, blogged about it: EDA360 Manifesto, EDA360 Redux, TSMC OIP vs CDNS OIP, and have had endless conversations with the foundries, fabless, EDA and IP companies alike. So far, EDA360 is all about the WHY, which is something I see everyday in working with the top semiconductor companies and foundries on leading edge technologies. I also now work with an Eastern European investment fund targeted at fabless semiconductor companies in Silicon Valley which may sound INSANE but I can assure you it’s not. There is still plenty of money to be made IF you can get an SoC into production on time and within a REASONABLE amount of money.
Per JohnB: EDA360 is a top down approach starting with System Realization – to SoC Realization – ending with Silicon Realization. The WHY of EDA360 makes complete sense, great vision, I’m on board, I even have an EDA360 shirt. The question I have is: exactly HOW is this going to work?
During the GSA panel John B. spoke last and challenged the panel to turn it upside down, start at the top and be SYSTEM versus SILICON driven. The lack of meaningful discussion on the topic was disappointing. This was an infrastructure innovation panel, right? The panelists knew JohnB was on the panel, right? The crowd definitely wanted more EDA360 discussion but left empty headed!
IF EDA360 is a fantasy and the cost of semiconductor design continues to increase exponentially, where will the design starts come from? Where is the meaningful discussion within the top EDA vendors on this topic? When will there be a panel with Wally, Aart, and JohnB? I would even invite Rajeev! WE NEED DESIGN STARTS!
Insanity is doing the same thing over and over again and expecting different results (Albert Einstein). Given that statement, according to Daniel Nenni (World Famous Blogger) the Electronic Design Automation industry is INSANE!