Synopsys IP Designs Edge AI 800x100

Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo

Podcast EP309: The State of RISC-V and the Upcoming RISC-V Summit with Andrea Gallo
by Daniel Nenni on 10-03-2025 at 10:00 am

Daniel is joined by Andrea Gallo, CEO of RISC-V International. Before joining RISC-V he worked in leadership roles at Linaro for over a decade and before Linaro he was a fellow at STMicroelectronics.

Dan explores the current state of the RISC-V movement with Andrea, who describes the focus and history of this evolving standard. Andrea describes the significant traction RISC-V is seeing across many markets, thanks to its ability to facilitate innovation. Andrea then describes the upcoming RISC-V Summit. He explains that the event will have many high-profile keynote speakers including Google and NASA, who will discuss RISC-V in space. Application of RISC-V to blockchain will also be discussed.

Andrea explains that there will be a new developers workshop on the first day of the summit which will include lectures and a hands-on lab with a real design. Exercises will include analyzing a SystemVerilog implementation to determine if a problem is in hardware or software. Other topics at the summit will include analyst presentations. Andrea also comments on the software enablement work underway as well as future expansion of RISC-V.

The RISC-V Summit will be held at the Santa Clara Convention Center on October 21-23. (October 21 is Member Day.) You can get more information and register for the event here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


Scaling Debug Wisdom with Bronco AI

Scaling Debug Wisdom with Bronco AI
by Bernard Murphy on 10-03-2025 at 8:00 am

Scaling Debug Wisdom min

In the business press today I still find a preference for reporting proof-of-concept accomplishments for AI applications: passing a bar exam with a top grade, finding cancerous tissue in X-rays more accurately than junior radiologists, and so on. Back in the day we knew that a proof-of-concept, however appealing, had to be followed by the hard work required to transition that technology to a scalable solution, robust in everyday use across a wide range of realistic use cases. A less glamorous assignment than the initial demo, but ultimately the only path to a truly successful product. The challenge in productization for AI-based systems is that the front-end of such products intrinsically depends on a weak component: our imperfect directions to AI. I recently talked to David Zhi LuoZhang, CEO of Bronco AI, on their agentic solution for verification debug. I came away with a new appreciation for how scaling our learned debug wisdom might work.

The challenge in everyday debug

When we verification types think of debug challenges we naturally gravitate towards corner case problems, exemplified by a strange misbehavior that takes weeks to isolate to a root cause before a designer can even start to think about a fix.

But those cases are not what consume the bulk of DV time in debug. Much more time-consuming is triage for the hundred failures you face after an overnight regression, getting to first pass judgment for root causes and assigning to the right teams for more detailed diagnosis. Here some of the biggest time sinks more likely come from mis-assignments rather than from difficult bugs. You thought the bug was in X but really it was in Y or in an unexpected interaction between Y and Z.

How do DV teams handle this analysis today? It’s tempting to imagine arcane arts practiced by seasoned veterans who alone can intuit their way from effects to causes. Tempting, but that’s not how engineering works and it would be difficult to scale to new DV intakes if they could only become effective after years of apprenticeship. Instead DV teams have developed disciplined and shared habits, in part documented, in part ingrained in the work culture. Consider this a playbook, or more probably multiple playbooks. Given a block or design context and a failure, a playbook defines where to start looking first, what else to look at (specs, RTL, recent checkins, testbench changes, …), what additional tests might need to be run, drilling down through a sequence of steps, ultimately narrowing down enough to likely handoff targets.

Tough stuff to automate before LLMs and agentic methods. Now automating a significant chunk of this process seems more within reach.

The Bronco.ai solution

The Bronco solution is agentic, designed to consume overnight regression results, to triage those result down to decently confident localizations, and to hand off tickets to the appropriate teams.

Playbooks are learned through interaction with experienced DV engineers. An engineer starts with a conversational request to Bronco AI, say

“I want to check that my AES FSMs are behaving properly. Check for alerts, interrupts, stalls, and that the AES CTR counter FSM is incrementing for the right number of cycles”

The engineer also provides references to RTL, testbench, specs, run log files, waveforms and so on. The tool then suggests a playbook to address this request as a refined description of the requirement. The engineer can modify that refined version if they choose, then the tool will execute the playbook, on just that block if they want, or more comprehensively across a subsystem or the full design and then will report back as required by the playbook. During this analysis, Bronco AI will take advantage of proprietary AI-native interfaces to tap into tool, design, spec and other data.

Playbooks evolve as DV experts interact with the Bronco tools. David was careful to stress while the tool continuously learns and self-improves through this process, it does not build models around customer design or test data but rather around the established yet intuitive debug process (what David calls the “Thinking Layer”), which becomes easier to interpret and compartmentalize (and if needed can be forgotten).

He also clarified an important point for me in connecting specs to RTL design behavior. There is an inevitable abstraction gap between specs and implementation with consequent ambiguity in how you bridge that gap. That ambiguity is one place where hallucinations and other bad behaviors can breed. David said that they have put a lot of work into “grounding” their system’s behavior to minimize such cases. Of course this is all company special sauce, but he did hint at a couple of examples, one being understanding the concept of backtracking through logic cones. Another is understanding application of tests to different instantiations of a target in the design hierarchy, obvious to us, not necessarily to an AI.

The Bronco.ai philosophy

David emphasized that the company’s current focus is on debug, which they view as a good motivating example to later address other opportunities for automation in verification and elsewhere in the design flow  He added that they emphasize working side by side with customers in production, rather than in experimental discovery in pre-sales trials.  Not as a service provider, but to experience and resolve real problems DV teams face in production, to refine their technology to scale.

I see this as good progress along a path to scaling debug wisdom. You can connect with Bronco.ai starting HERE.

Also Read:

Arm Lumex Pushes Further into Standalone GenAI on Mobile

The Impact of AI on Semiconductor Startups

MediaTek Dimensity 9500 Unleashes Best-in-Class Performance, AI Experiences, and Power Efficiency for the Next Generation of Mobile Devices


CEO Interview with David Zhi LuoZhang of Bronco AI

CEO Interview with David Zhi LuoZhang of Bronco AI
by Daniel Nenni on 10-03-2025 at 8:00 am

2023 11 17 Contrary 2168 (2) (1)

David Zhi LuoZhang is Co-Founder and CEO of Bronco AI with extensive experience in building AI systems for mission-critical high-stakes applications. Previously while at Shield AI, he helped train AI pilots that could beat top human F-15 and F-16 fighter pilots in aerial combat. There, he created techniques to improve ML interpretability and reliability, so the system could explain why it flew the way it did. He gave up a role at SpaceX working on the algorithms to coordinate constellations of Starlink satellites in space, and instead founded Bronco to bring AI to semiconductors and other key industries.

Tell us about your company.

We do AI for design verification. Specifically, we’re building AI agents that can do DV debugging.

What that means is the moment a DV simulation fails, our agent is already there investigating. It looks at things like the waveform, the run log, the RTL and UVM, and the spec to understand what happened. From there, it works until it finds the bug or hands off a ticket to a human.

We’re live-deployed with fast-moving chip startups and are working with large public companies to help their engineers get a jump on debugging. And we’re backed by tier-1 Silicon Valley investors and advised by leading academics and semiconductor executives.

What problems are you solving?

If you look at chip projects, verification is the largest, most time-consuming, and most expensive part. And if you look at the time-spent of each DV engineer, most of their time is spent on debug. They are watching over these regressions and stomping out issues as they show up over the course of the project.

Every single day, the DV engineer gets to work and they have this stack of failures from the night’s regression to go through. They have to manually figure out if it’s a design bug or a test bug, if they’ve seen the bug before, what the root cause might be, and who to give it to. And this is quite a time-consuming and mundane debugging process.

This creates a very large backlog in most companies, because typically this task of understanding what’s happening in each failure falls onto a select few key people on the project that are already stretched thin. Bronco is helping clear this bottleneck and take the pressure off those key folks and in-so-doing unblock the rest of the team.

What application areas are your strongest?

We focus on DV debug. We chose DV debug because it is the largest pain point in chip development, and because from a technical standpoint it is a very strong motivating problem.

To do well at DV debug, we need to be able to cover all the bases of what a human DV is currently looking at and currently using to solve their problems. For example, we’re not just assisting users in navigating atop large codebases or in reading big PDF documents. We’re also talking about making sense of massive log files and huge waveforms and sprawling design hierarchies. Our agent has to understand these things.

This applies at all levels of the chip. With customers, we’ve deployed Bronco everywhere from individual math blocks up to full chip tests with heavy NoC and numerics features. One beautiful thing about the new generation of Generative AI tools is that it can operate at different levels of abstraction the same way humans can, which greatly improves its scalability compared to more traditional methods that would choke on higher gate counts.

What keeps your customers up at night?

It’s a well-known set of big-picture problems that trickle into day-to-day pains.

Chip projects need to get to market faster than ever, and the chips need to be A0 ready-to-ship, but there just aren’t enough DV engineers to get the job done.

That manifests in there not being enough engineers to handle the massive amount debugging that needs to go into getting any chip closed out. So the engineers are in firefighting mode, attacking bugs as they come up, and being pulled away from other important work – work that could actually make them more productive in the long-run or could surface bigger issues with uncovered corner cases.

And moreover, this burden falls most heavily on the experts on the project. During crunch time, it’s these more experienced engineers that get inundated with review requests, and because of institutional knowledge gaps, the rest of the team is blocked by them.

What does the competitive landscape look like and how do you differentiate?

There are the large EDA giants, and there are a few other startups using AI for design and verification. Most of their work focuses on common DV tasks like document understanding and code help. These are general, high surface area problems that aren’t too far from the native capabilities of general AI systems like GPT.

No other company is taking the focused approach we are to AI for DV. We are focused on getting agents that can debug very complex failures in large chip simulations. We use that actually as a way to define what it means to be good at those more general tasks in the DV context like understanding spec docs or helping with hardware codebases.

For example, it’s one thing to answer basic questions from a PDF or write small pieces of code. It’s another thing to use all that information while tracing through a complex piece of logic. By taking this focused approach, we’re seeing huge spillover benefits. We almost naturally have a great coding assistant and a great PDF assistant because they’ve been battle-tested in debug.

What new features or technology are you working on?

All of our tech is meant to give your average DV engineer superpowers.

On the human-in-the-loop side, we are making a lot of AI tools that automate the high-friction parts of manual debug. For example, our tool will go ahead and set up the waveform environment to focus on the right signals and windows, so engineers don’t have to spend ridiculous amounts of time clicking through menus.

On the agent side, we want to allow each DV engineer to spin up a bunch of AI DVs to start debugging for them. That requires a really smart AI agent with the right tools and memory, but also really good ways for users to transfer their knowledge to the AI. And of course, we are doing all this in a safe way that stays on-premise at the customer’s site to put their data security first.

And we’re doing all these things on ever-larger and more sophisticated industry-scale chip designs. In the long term, we see a large part of the Bronco Agent being like a scientist or architect, able to do very large system-level reasoning about things like performance bottlenecks, where the Agent has to connect some super high-level observation to some super low-level root cause.

How do customers normally engage with your company?

Customers have a very easy time trying our product, since we can deploy on-prem and can leverage existing their AI resources (eg. Enterprise ChatGPT). First, the customer chooses a smaller, lower-risk block to deploy Bronco on. Bronco deploys on-premise with the customer, typically via a safe, sandboxed system to run our app. Then, Bronco works with the block owner to onboard our AI to their chip and to onboard their DVs to our AI.

From there, it’s a matter of gauging how much time our AI is saving the DV team on tasks they were already doing, and seeing what new capabilities our tool unlocked for their team.

Also Read:

Scaling Debug Wisdom with Bronco AI

Arm Lumex Pushes Further into Standalone GenAI on Mobile

The Impact of AI on Semiconductor Startups

 

 


Webinar – The Path to Smaller, Denser, and Faster with CPX, Samtec’s Co-Packaged Copper and Optics

Webinar – The Path to Smaller, Denser, and Faster with CPX, Samtec’s Co-Packaged Copper and Optics
by Mike Gianfagna on 10-02-2025 at 10:00 am

Webinar – The Path to Smaller, Denser, and Faster with CPX, Samtec’s Co Packaged Copper and Optics

For markets such as data center, high-performance computing, networking and AI accelerators the battle cry is often “copper is dead”. The tremendous demands for performance and power efficiency often lead to this conclusion. As is the case with many technology topics, things are not always the way they seem. It turns out a lot of the “copper is dead” sentiment has to do with the view that it’s a choice of either copper or optics. In such a situation, optical interconnect will win.

But what if copper and optics could be integrated and managed together on one platform?  It turns out there are many short-reach applications where copper is superior. The ability to achieve this co-technology integration at advanced 224G speeds is the topic of an upcoming webinar from Samtec. If you struggle with the negative ramifications of “copper is dead”, you will want to attend this live webinar. The event will be broadcast live on October 21. More details will follow, but first let’s examine the path to smaller, denser, and faster with CPX, Samtec’s co-packaged copper and optics solution.

Who’s Speaking

Matt Burns

The quality of a webinar, especially a live one is heavily influenced by the quality of the speaker. In the case of the upcoming event, everyone is in good hands. Matt Burns will be presenting. I’ve known Matt for quite a while. Samtec was an excellent partner of eSilicon back in the day, and I’ve attended many discussions and events with Matt. He has an easy-going presentation style, but under it all is a substantial understanding of what it takes to build high-performance communication channels and why it matters for any successful system design.

A quick summary of Matt’s background is in order. He develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 25 years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. He currently serves as Secretary at PICMG. If it’s a close-to-impossible system design issue, Matt has likely seen it and helped to flatten it.

Some Topics to be Covered

Using all the tools and technologies available for any complex design project is usually the best approach. Matt will discuss this in some detail, describing the situations where passive copper interconnect delivers the best result. Short reach is certainly one aspect that influences this decision, but there are other considerations as well.

For longer reach channels, active optical channels can be an excellent choice. The reasons to drive one way vs. another are not as simple as you may think and Matt will help with examples for various strategies.

The key point in all this is, what if you could deploy both copper and optical interconnect in a unified way?  A mix and match scenario if you will. It turns out Samtec has been managing this kind of platform-level integration for about 15 years.

Getting into some specifics, the transition to 224 Gbps PAM4 signaling can strain copper interconnects due to reduced signal-to-noise rations and tighter insertion loss budgets. This usually limits reach to under 1 meter. Using co-packaged copper (CPC), this limit can be extended to 1.5 meters, enabling dense intra-rack GPU clusters while lowering system cost. But copper’s limitations over longer distances hinder inter-rack scaling.

Co-packaged optics (CPO) helps by integrating the optical engine within the switch silicon, enabling high-bandwidth, scalable links across racks. CPO overcomes copper’s physical constraints, reducing power and cooling costs, and unlocking scalable, efficient AI supercomputing fabrics that interconnect thousands of GPUs across data centers.

But what if you could have it both ways? Matt will describe Samtec’s new strategy for advanced channel speeds that combines CPC and CPO to create a new category called CPX. This capability is delivered by Samtec’s Si-Fly® HD. A photo of the platform is shown on the top of this post.

Matt will describe how his technology delivers the highest density 224 Gbps PAM4 solution in today’s market. He will provide details about how the electrically pluggable co-packaged copper and optics solutions (CPX) are achievable on a 95 mm x 95 mm or smaller substrate using Samtec’s SFCM connector. The SFCM mounts directly to the package substrate and is pluggable with Samtec’s SFCC cable assembly or an optical cable assembly of your choosing.

Synopsys Example

Samtec has already worked with several high-profile system OEMs and IP providers to deploy this technology. Matt will also talk about some of those achievements.

To Learn More

If you are faced with tough decisions regarding channel interconnect choices, you may have more options that you think. Matt Burns will take you through a new set of options enabled by Samtec’s new Si-Fly HD.  The webinar’s full title is CPX: Leveraging CPC/CPO for the Latest Scale-Up and Scale-Out AI System Topologies. It will be broadcast on October 21 from 10:00 AM – 11:00 AM Pacific time  and you can save a seat for the event here.


Thermal Sensing Headache Finally Over for 2nm and Beyond

Thermal Sensing Headache Finally Over for 2nm and Beyond
by Admin on 10-02-2025 at 6:00 am

PNPBJT in a diode connected configuration

By Nir Sever, Senior Director Business Development, proteanTechs

Silicon-proven LVTS for 2nm: a new era of accuracy and integration in thermal monitoring

Effective thermal management is crucial to prevent overheating and optimize performance in modern SoCs. Inadequate temperature control due to inaccurate thermal sensing compromises power management, reliability, processing speed, and lifespan, leading to issues like electromigration, and hot carrier injection and even thermal runaway.

Unfortunately, precise thermal monitoring reached an inflection point at 2nm, with traditional solutions proving less practical below 3nm. To tackle the issue, this article delves into a novel approach, accurate to ±1.0°C, that overcomes this critical challenge.

proteanTecs now offers a customer-ready, silicon-proven solution for 5nm, 3nm and 2nm nodes. In fact, our latest silicon reports demonstrate robust performance, validating that accurate and scalable thermal sensing is achievable in the most advanced nodes.

Accurate Thermal Sensing in Advanced Process Nodes: A Growing Challenge

As process nodes scale to 2nm and below, accurately measuring on-chip temperature has become increasingly difficult. Traditional Voltage and Temperature sensors based on diodes are less practical in these nodes due to their high-voltage requirements. This gap in temperature measurement creates risks that compel chipmakers to seek future-ready solutions. The challenge is magnified in designs that leverage DVFS techniques.

Why Traditional Solutions Fall Short

Traditional thermal sensing technologies are hitting hard limitations in precision and overall feasibility when moving beyond 3nm:

  • Temperature sensors based on BJT diodes

Analog thermal diodes with Bipolar Junction Transistors (BJTs) have been a go-to option for accurate thermal sensing. However, their reliance on high I/O voltages makes them inapplicable for nodes beyond 3nm based on Gate-All-Around (GAA) technology, which doesn’t support high I/O (analog) voltages, and BJT support may be discontinued as well in the future.

PNPBJT in a diode-connected configuration. The base-emitter junction has a predictable transfer function that depends on temperature, making it suitable for thermal sensing. However, analog thermal diodes are a no-go for nodes beyond 3nm.

Even before GAA, thermal diodes suffered from low coverage as they were hard to integrate. Their design restricted placement to chip edges near the I/O power supply, leaving vital internal areas unmonitored due to analog routing limitations. Furthermore, they consumed more power than low-voltage alternatives due to their high-voltage requirement.

  • Digital Temperature Measurements based on Ring oscillators

Ring oscillators are scalable to advanced nodes, but their temperature measurement error can be as high as ±10°C. They are inadequate where accuracy is paramount. One example concern using thermal sensing to determine voltage or frequency adjustments (e.g. DVFS), as even slight temperature variations can significantly degrade performance.

Ring oscillator temperature error of different calibration techniques[1] can be greater than -10°C, which is too high for many use cases.
The limitations above underscore the need for an accurate thermal sensing solution designed with core transistors only to fit advanced nodes.

A Thermal Sensor Built for the Future

proteanTecs LVTS (Local Voltage and Thermal Sensor) is purpose-built for precision thermal sensing in advanced nodes without relying on I/O transistors and high analog I/O voltages and even BJTs. It measures temperature with accuracy of ±1.0°C while using core transistors exclusively and operating in a wide range of core voltages, combining precision with future readiness for GAA nodes.

Key features of LVTS:
  • Temperature measurement accuracy of +/-1°C (3-sigma)
  • Voltage measurement accuracy of +/-1.5% (3-sigma)
  • Over temperature fast alert
  • Wide range of operational voltages (650-950 mV)
  • High-speed measurement

proteanTecs LVTS measurements demonstrate an accuracy of ±1°C in a wide range of voltages (0.65V SSG – 1.05V FFG) and temperatures (-40°C – 125°C.)

Unmatched Benefits Across All Critical Parameters

LVTS operates with low VDD core rather than high I/O voltage while maintaining superb accuracy, unlike Digital Thermal sensors based on ring oscillators. This unique design enables easy integration anywhere on the chip, providing more granular voltage and temperature monitoring than thermal diodes. Additionally, its smaller size and lower power consumption minimize the impact on PPA compared to BJT-based solutions.

LVTS compared with thermal diodes and ring oscillators (ROSC)

An additional capability of LVTS provides real-time warnings and critical alerts in the form of HW signals when predetermined thermal thresholds are breached. This feature enables immediate corrective action, reducing the risk of overheating to maintain chip integrity.

LVTS Flavors for Enhanced Flexibility

In addition to the standard LVTS described above, proteanTecs offers two specialized variants to address diverse design needs:

  • An extended flavor – includes external voltage measurement to extend the measured voltage range down to zero volts.
  • A distributed flavor – designed as a Core VDD-only, analog thermal and DC voltage level sensor hub, it supports extremely small remote thermal sensors for precise temperature measurements at hot spots.

These two versions complement the regular LVTS, allowing chipmakers to tailor their thermal sensing approach for maximum coverage, precision, and responsiveness in critical areas of the design.

Complementing Deep Data Analytics with Accurate Voltage and Temperature Sensing

LVTS is already silicon-proven in 5nm, 3nm, and now also in 2nm, with a detailed silicon report available, making it the industry-leading, future-proof, customer-ready solution.

This innovation was warmly embraced by multiple chipmakers concerned about the absence of accurate and reliable thermal sensing in next-generation silicon.

These customers use LVTS alongside other proteanTecs products, as it complements the broader deep data monitoring and analytics solutions explored here.

LVTS is seamlessly integrated into proteanTecs’ HW Monitoring System, enabling accurate DC voltage and thermal measurements real-time, making LVTS a vital addition to chipmaker power and reliability strategies.

Want to know more about how LVTS can help scale your design to advanced nodes with accurate voltage and temperature sensing? Contact us here.

[1] El-Zarif, Nader, Mostafa Amer, Mohamed Ali, Ahmad Hassan, Aziz Oukaira, Christian Jesus B. Fayomi, and Yvon Savaria. 2024. “Calibration of Ring Oscillator-Based Integrated Temperature Sensors for Power Management Systems” Sensors 24, no. 2: 440.

Nir Sever brings with him more than 30 years of technological and managerial experience in advanced VLSI engineering. Prior to joining ProteanTecs, Nir served for 10 years as the COO of Tehuti Networks, a pioneer in the area of high speed networking Semiconductors. Before that, he served for 9 years as Senior Director of VLSI Design and Technologies for Zoran Corporation, a recognized world leader in Semiconductors for the highly competitive Consumer Electronics Market. Nir was responsible for driving Zoran silicon technologies and delivering more than 10 new silicon products each year. Prior to Zoran, Nir held various managerial and technological VLSI roles at 3dfx Interactive, GigaPixel Corporation, Cadence Design Systems, ASP Solutions and Zoran Microelectronics. Nir earned his BSEE degree from the Technion – Israel Institute of Technology.

Also Read:

DAC News – proteanTecs Unlocks AI Hardware Growth with Runtime Monitoring

Webinar – Power is the New Performance: Scaling Power & Performance for Next Generation SoCs

Podcast EP279: Guy Gozlan on how proteanTecs is Revolutionizing Real-Time ML Testing

 


Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation

Synopsys and TSMC Unite to Power the Future of AI and Multi-Die Innovation
by Daniel Nenni on 10-01-2025 at 10:00 am

UNDER EMBARGO 1PM PT Sept 24 Synopsys TSMC OIP 2025 (1)

In a rapidly evolving semiconductor landscape, where AI demands unprecedented computational power and efficiency, Synopsys has deepened its partnership with TSMC to pioneer advancements in AI-driven designs and multi-die systems. Announced during the TSMC OIP Ecosystem Summit last week, this collaboration leverages Synopsys’ EDA tools and IP solutions alongside TSMC’s cutting-edge processes and packaging technologies. The result? Accelerated innovation that empowers chip designers to create high-performance, low-power multi-die architectures essential for next-generation AI applications, from data centers to edge devices, absolutely.

At the heart of this alliance is Synopsys’ commitment to enabling differentiated designs on TSMC’s advanced nodes. Certified digital and analog flows, integrated with Synopsys.ai, are now available for TSMC’s N2P and A16 processes, incorporating the innovative NanoFlex architecture. This setup not only boosts performance but also streamlines analog design migration, allowing engineers to scale chips efficiently while optimizing power consumption. For the A16 node, Synopsys has enhanced capabilities for Super Power Rail (SPR) designs, improving power distribution and thermal management in backside routing. Additionally, pattern-based pin access methodologies have been refined to deliver superior area efficiency. Looking ahead, the duo is already collaborating on flows for TSMC’s A14 process, with the first process design kit slated for release later in 2025.

Physical verification is equally robust, with Synopsys’ IC Validator certified for A16, supporting design rule checking (DRC) and layout versus schematic (LVS) verification. Its elastic architecture handles complex electrostatic discharge (ESD) rules on N2P with faster turnaround times, ensuring reliability in high-stakes AI systems.

A standout feature of the collaboration is the focus on 3D integration, addressing the limitations of traditional 2D scaling. Synopsys’ 3DIC Compiler platform, a unified exploration-to-signoff tool, supports TSMC’s SoIC-X technology for 3D stacking, as well as CoWoS packaging for silicon interposers and bridges. This has facilitated multiple customer tape-outs, demonstrating real-world success. The platform automates critical tasks like UCIe and HBM routing, through-silicon via (TSV) planning, bump alignment, and multi-die verification, slashing design cycles and enhancing productivity. In photonics, an AI-optimized flow for TSMC’s Compact Universal Photonic Engine (COUPE) tackles multi-wavelength operations and thermal challenges, boosting system performance in optical interconnects vital for AI data transfer.

Complementing these EDA advancements is Synopsys’ expansive IP portfolio, optimized for TSMC’s N2/N2P nodes to minimize power usage and integration risks. It includes high-performance interfaces like HBM4, 1.6T Ethernet, UCIe, PCIe 7.0, and UALink, alongside automotive-grade solutions for N5A and N3A processes. This suite—encompassing PHYs, embedded memories, logic libraries, programmable I/O, and non-volatile memory—ensures safety, security, and reliability across markets like automotive, IoT, and high-performance computing (HPC). For multi-die designs, specialized 3D-enabled IP further accelerates silicon success.

I spoke with Michael Buehler-Garcia, Senior Vice President at Synopsys at the event. He is a long time friend. He emphasized the partnership’s impact:

Our close collaboration with TSMC continues to empower engineering teams to achieve successful tape outs on the industry’s most advanced packaging and process technologies,” said Michael Buehler-Garcia, Senior Vice President at Synopsys. “With certified digital and analog EDA flows, 3DIC Compiler platform, and our comprehensive IP portfolio optimized for TSMC’s advanced technologies, Synopsys is enabling mutual customers to deliver differentiated multi-die and AI designs with enhanced performance, lower power, and accelerated time to market.”

Echoing this, Aveek Sarkar, Director of TSMC’s Ecosystem and Alliance Management Division, highlighted the ecosystem’s role:

“TSMC has been working closely with our long-standing Open Innovation Platform® (OIP) ecosystem partners like Synopsys to help customers achieve high quality-of-results and faster time-to-market for leading-edge SoC designs,”.

“With the ever-growing need for energy efficient and high-performance AI chips, the OIP ecosystem collaboration is crucial for providing our mutual customers with certified EDA tools, flows and high-quality IP to meet or exceed their design targets.”

Bottom Line: This synergy positions Synopsys and TSMC at the forefront of the AI revolution, where multi-die systems promise to overcome Moore’s Law bottlenecks by integrating heterogeneous dies for superior efficiency. As AI workloads explode, such innovations will reduce energy footprints in hyperscale data centers and enable smarter autonomous vehicles.

Also Read:

Synopsys Announces Expanding AI Capabilities and EDA AI Leadership

AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025

Synopsys Collaborates with TSMC to Enable Advanced 2D and 3D Design Solutions


Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025

Revolutionizing AI Infrastructure: Alchip and Ayar Labs’ Co-Packaged Optics Breakthrough at TSMC OIP 2025
by Daniel Nenni on 10-01-2025 at 6:00 am

Alchip TSMC OIP 2025

In the relentless race to power next-generation artificial intelligence (AI) systems, data connectivity has emerged as the critical bottleneck. As AI models balloon in size—from billions to trillions of parameters—compute resources alone are insufficient. According to Ayar Labs, approximately 70% of AI compute time is wasted waiting for data, a inefficiency that escalates exponentially with system scale. Traditional copper-based electrical I/O, while reliable for intra-rack connections, falters under the demands of multi-rack AI clusters. Power consumption soars, latency spikes, and bandwidth caps out, rendering electrical solutions obsolete for hyperscale datacenters. Enter the strategic collaboration between Alchip Technologies and Ayar Labs, unveiled in September 2025, which promises to shatter these barriers through co-packaged optics (CPO) and advanced packaging innovations.

At the TSMC North America Open Innovation Platform (OIP) Ecosystem Forum on September 26, the partnership fuses Alchip’s expertise in high-performance ASIC design and 2.5D/3D packaging with Ayar Labs’ pioneering optical I/O chiplets. This isn’t mere integration; it’s a holistic ecosystem leveraging TSMC’s COUPE (Co-packaged Optics with Unified Packaging and Electronics) technology to embed optical engines directly onto AI accelerator packages. The result? A reference design platform that enables seamless, multi-rack scale-up networks, transforming AI infrastructure from rigid, power-hungry monoliths into flexible, composable architectures.

At the heart of this solution lies Ayar Labs’ TeraPHY™ optical engines, silicon photonics-based chiplets that replace cumbersome pluggable optics with in-package optical I/O. Each TeraPHY engine employs a stacked Electronic Integrated Circuit (EIC) and Photonic Integrated Circuit (PIC) architecture, utilizing microring modulators for dense, efficient light-based data transmission. The EIC, fabricated on advanced nodes, handles protocol-specific features like UCIe-A (Universal Chiplet Interconnect Express-Advanced) for logic protocols such as CHI, while the PIC manages optical signaling. A detachable optical connector simplifies manufacturing, assembly, and testing, ensuring high-volume scalability. Protocol-agnostic by design, TeraPHY supports endpoints like UALink, PCIe, and Ethernet, with forward error correction (FEC) and retimer logic delivering raw bit error rates below 10^-6 for PAM4 CWDM optics—achieving single-hop latencies of 100-200 nanoseconds. Future DWDM variants promise even lower 20-30 ns latencies and BERs under 10^-12.

Alchip complements this with its I/O protocol converter chiplets, bridging UCIe-A (streaming mode) to scale-up protocols, and integrated passive devices (IPDs) that optimize signal integrity through custom capacitors. Their prototype, showcased at Booth 319 in Taipei and Silicon Valley, integrates two full-reticle AI accelerators, four protocol converters, eight TeraPHY engines, and eight HBM stacks on a common substrate. This configuration unlocks over 100 Tbps of scale-up bandwidth per accelerator and more than 256 optical ports, dwarfing electrical I/O’s limits. Power density remains manageable, as optics reduce end-to-end energy per bit by minimizing electrical trace lengths and avoiding the thermal overhead of pluggables.

The implications for AI workloads are profound. In scale-up networks, where XPUs (AI processing units) must act as unified entities—scaling from 100 to 1,000 units—the joint solution enables XPU-to-XPU, XPU-to-switch, and switch-to-switch connectivity with path diversity for ultra-low latency. Extended memory hierarchies, pooling DRAM across racks via optical links, boost application metrics like training throughput by 2-3x, per preliminary simulations. Energy efficiency improves dramatically: Optical I/O consumes up to 10x less power than copper equivalents, critical as AI racks approach 100kW densities. For hyperscalers like those deploying GPT-scale models, this means greener, more interactive datacenters capable of real-time inference at exascale.

This collaboration underscores a broader industry shift toward disaggregated, photonics-driven computing. By addressing reach limitations beyond copper’s 1-2 meter horizon and enhancing radix for massive parallelism, Alchip and Ayar Labs are not just solving today’s challenges but future-proofing AI. As Vladimir Stojanovic, Ayar Labs’ CTO and co-founder, notes, “AI has reached an inflection point where traditional interconnects limit performance, power, and scalability.” Erez Shaizaf, Alchip’s CTO, echoes this, emphasizing the need for “innovative, collaborative advanced packaging.” With production-ready test programs and reliability qualifications, the duo is poised to accelerate adoption, potentially slashing AI deployment costs by 30-50% through efficiency gains.

Bottom line: This partnership heralds a new era of AI infrastructure: scalable, flexible, and composable. As models grow unabated, optical CPO will be indispensable, and Alchip-Ayar Labs’ blueprint offers a proven path forward. Hyperscalers take note—this is the optics revolution AI has been waiting for.

Contact Alchip

Also Read:

Alchip’s 3DIC Test Chip: A Leap Forward for AI and HPC Innovation

Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 Roadmap

Alchip’s Technology and Global Talent Strategy Deliver Record Growth


AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025

AI Everywhere in the Chip Lifecycle: Synopsys at AI Infra Summit 2025
by Kalar Rajendiran on 09-30-2025 at 10:00 am

Godwin Talk Summary AI Infra Summit 2025

At the AI Infra Summit 2025, Synopsys showed how artificial intelligence has become inseparable from the process of creating advanced silicon. The company’s message was clear: AI is an end-to-end engine that drives every phase of chip development. Three Synopsys leaders illustrated this from distinct vantage points. Godwin Maben, Synopsys Fellow, delivered a talk on designing ultra–energy-efficient AI chips. Arun Venkatachar, Vice President of AI & Central Engineering, joined a dynamic panel on the impact of AI on semiconductor startups. And Frank Schirrmeister, Executive Director of Strategic Programs, gave a talk on meeting the quadrillion-cycle verification demands of modern datacenter designs. Together, their sessions formed a comprehensive narrative of how Synopsys enables greener, faster, and more reliable silicon.

Designing for Energy Efficiency

Godwin set the context with a stark statistic: AI workloads are projected to grow fifty-fold by 2028, threatening to overwhelm datacenter power budgets. He described how next-generation system-on-chip (SoC) designs must balance unprecedented performance with aggressive energy targets. Domain-specific accelerators, near-memory compute, and chiplet-based 3D integration all play a role, but Godwin emphasized that the real breakthrough comes when AI-driven electronic design automation (EDA) is applied at every level. Machine-learning-guided synthesis, floor-plan optimization, and continuous energy regression allow architects to reduce power per watt while meeting tight performance and area goals. His talk highlighted that sustainable AI silicon isn’t a final step—it’s architected in from the start.

Accelerating the Design Flow

In the panel session “The Impact of AI on Semiconductor Startups,” Arun explained how Synopsys began weaving machine learning into its design tools nearly a decade ago, well before today’s hype cycle. That early start is paying off. AI now informs power, performance, and area (PPA) optimization, verification, and manufacturing test, enabling some customers to cut design times by as much as 40 percent. Arun stressed that this isn’t about replacing engineers; rather, AI acts as a force multiplier, automating routine tasks and surfacing optimal design choices so human experts can focus on system-level creativity. He painted a picture of a continuous AI-assisted pipeline where improvements in one stage cascade into the next, shortening schedules and reducing the risk of late-stage surprises. For startups, this means faster paths to market and the ability to compete with established players.

Arun also discussed how cloud-based EDA is enabling startups to accelerate time to results and drive improvements by leveraging scalable, AI-powered development tools that empower small teams to achieve breakthrough innovation more efficiently.

Verifying at Quadrillion-Cycle Scale

Frank turned the spotlight on the most daunting phase: verification. Modern datacenter chips integrate multi-die architectures, Arm-based compute subsystems, and heterogeneous accelerators. Ensuring these complex systems meet power, performance, and reliability targets requires quadrillions of verification cycles. Traditional simulation alone can’t keep pace. Frank outlined how Synopsys addresses the challenge with hardware-assisted verification (HAV), including ZeBu emulation, HAPS prototyping, and EP-Ready hardware that seamlessly switches between emulation and prototyping. These platforms support early software bring-up, high-fidelity power analysis, and rapid coverage closure, allowing design teams to meet yearly product refresh cycles without compromising quality or budget.

Customer proof points from companies like Microsoft, NVIDIA, and AMD underscore the productivity gains.

A Unified AI-Driven Pipeline

What emerges from these three perspectives is a powerful theme: AI is now the connective fabric of the semiconductor lifecycle. Godwin’s focus on energy efficiency, Arun’s account of AI-assisted design flows, and Frank’s hardware-accelerated verification all reveal different facets of the same strategy. Synopsys doesn’t merely provide point tools; it delivers a continuous, AI-enabled ecosystem that shortens time-to-market, minimizes energy consumption, and raises confidence in first-silicon success.

The Summit sessions also highlighted Synopsys’s broader collaborations—with cloud providers for scalable compute, with Arm for ready-to-integrate IP, and with hyperscalers eager to validate enormous AI workloads. These partnerships reinforce the company’s role as the hub where cutting-edge design, advanced verification, and manufacturing readiness converge.

Summary

AI Infra Summit 2025 confirmed that designing the next generation of silicon is no longer about isolated breakthroughs. It is about orchestrating every step—architecture, layout, verification, and manufacturing—as one AI-driven continuum. Synopsys has been preparing for this moment for years, and the results are clear: faster design cycles, lower power footprints, and reliable chips that scale from edge devices to the largest datacenters.

By bringing together energy-efficient architecture, accelerated design flows, and quadrillion-cycle verification under a single AI umbrella, Synopsys demonstrated that “AI everywhere in the chip lifecycle” is the roadmap for the future of semiconductor innovation.

Also Read:

Synopsys Announces Expanding AI Capabilities and EDA AI Leadership

The Rise, Fall, and Rebirth of In-Circuit Emulation (Part 1 of 2)

eBook on Mastering AI Chip Complexity: Pathways to First-Pass Silicon Success


Neurosymbolic code generation. Innovation in Verification

Neurosymbolic code generation. Innovation in Verification
by Bernard Murphy on 09-30-2025 at 6:00 am

Innovation New

Early last year we talked about state space models, a recent advance over large language modeling with some appealing advantages. In this blog we introduce neurosymbolic methods, another advance in foundation technologies, here applied to automated code generation. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford, EE292A) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Neural Program Generation Modulo Static Analysis. The authors are from Rice University, UT Austin and the University of Wisconsin. The paper was published in Neural Information Processing Systems 2021 and has 27 citations.

Amazing as they are, LLMs and neural networks have limitations becoming apparent in “almost correct” code generation from CoPilot, the underwhelming release of GPT5 and other examples. Unsurprising. Neural nets excel at perception-centric learning from low level detail, but they do not excel at reasoning based on prior knowledge, an area where symbolic methods fare better. Neurosymbolic methods fuse the two approaches to leverage complementary strengths. Neurosymbolic research and applications are not new but have been overshadowed by LLM advances until recently.

This month’s blog uses a neurosymbolic approach to improve accuracy in automated software generation for Java methods.

Paul’s view

LLM-based coding assistants are rapidly becoming mainstream. These assistants rely mostly on their underlying LLM’s ability to generate code from a user text prompt and surrounding other code already written. Under the hood, these LLMs are “next word” predictors that write code one word at a time, beginning with the prompt as their input and then consecutively appending each word generated so far to the prompt to form a successor prompt which is then used to generate the next word and so on.

This paper observes that unlike natural language, all programming languages must conform to a formal grammar (search “BNF grammar” in your browser). These grammars map source code into a “syntax tree” structure. It’s entirely possible to make a neural network that is a syntax tree generator rather than a word generator. Such a network recursively calls itself to build a syntax tree in a left-to-right depth-first search approach.

The authors further propose to annotate nodes in a syntax tree with a “symbol table” containing all declared variables and their types from surrounding code already written and portion of the syntax tree generated so far. The symbol table is created by a traditional non-AI algorithm as would be done by a software compiler and is used during training of the network as a weak supervisor – code generated that assigns variables or function arguments in violation of the symbol table are labeled as bad code.

The authors train and benchmark a 60M parameter “neurosymbolic grammar” (NSG) syntax tree-based code generator for Java code generation. They use a large database of java classes with 1.6M methods total, randomly removing the body of one method from a class, and asking their NSG to re-generate code for that method based only on the surrounding code for the rest of the class, including its comments. They compare NSG to a variety of baseline LLMs from 125M to 1.3B parameters using a combination of syntax correctness checks and checks for similarity to the golden method used for training. NSG is a lot better: 86% of NSG generated code passes all syntax correctness checks vs. 67% from the best alternative (CodeGPT 125M parameters), and NSG generated code has a 40% average similarity score to golden vs. 22% from the best alternative (GPTNeo 1.3B parameters).

Of course, with today’s 100B+ parameter LLMs using multi-shot reasoning, which can include feeding software compiler errors back to the LLM and asking it to fix them, the benchmark results could prove less compelling. As the authors themselves point out in this paper, more research here would be welcome!

Raúl’s view

Neuro-symbolic approaches in artificial intelligence combine neural methods such as deep learning with symbolic reasoning based on formal languages and logic. The goal is to overcome the weaknesses of both approaches: neural networks excel at pattern recognition from large datasets but cannot easily take advantage of coded expert knowledge and are “black boxes” that make understanding their decision-making processes hard; symbolic systems can encode precise rules and constraints, but they are brittle and hard to scale. The first paper in the trio we blog about this week gives a brief introduction to this topic.

The monograph “Neurosymbolic Programming”  more specifically addresses integrating deep learning and program synthesis. Strategies include neural program synthesis, where neural networks are trained to generate programs directly; learning to specify in which models learn to complete or disambiguate incomplete specifications; neural relaxations aim at using the parameters of a neural network to approximately represent a set of programs; and distillation where trained neural networks are converted back into symbolic programs approximating their behavior.

Against this backdrop, the NeurIPS 2021 paper Neural Program Generation Modulo Static Analysis presents one specific approach to program (Java methods) generation using a neuro-symbolic approach.  The authors argue that large language models of code (e.g., GPT-Neo, Codex) often fail to produce semantically valid long-form code such as full method bodies, and contain basic errors such as uninitialized variables, type mismatches, and invalid method calls. The key thesis of the paper is that static program analysis provides semantic relationships “for free” that are otherwise very hard for neural networks to infer. The paper is self-contained but assumes knowledge of compilation of formal languages and neural models to fully understand the approach.

The models built, Neurosymbolic Attribute Grammars (NSGs), extend context-free grammars with attributes derived from static analysis such as symbol tables, type information, and scoping. During generation, the neural model chooses not only on syntactic context but also based on these semantic attributes (“weak supervision”). This hybrid system improves the model’s ability to respect language rules while still benefiting from statistical learning.

The system was evaluated on the task of generating Java method bodies. Training used 1.57 million Java methods, with a grammar supporting a subset of Java. The NSG model itself had 63 million parameters, which is modest compared to billion-parameter transformers like GPT-Neo and Codex. NSGs substantially outperform these larger baselines on static checks (ensuring no undeclared variables, type safety, initialization, etc.) and fidelity measures (similarity of generated code to ground truth, Abstract Syntax Tree (AST) structure, execution paths). For example, NSGs achieved 86% of generated methods passing all static checks, compared to ~65% for GPT-Neo and ~68% for CodeGPT. On fidelity metrics, NSGs nearly doubled the performance of transformers, showing they not only generate valid code but also code that more closely matches intended behavior.

This work illustrates the power of neuro-symbolic methods in generating programming languages where semantics matter deeply; unlike natural language, code is governed by strict syntactic and semantic rules. Verification and generation of digital systems, e.g., (System)Verilog, obviously benefit from such techniques.

Also Read:

Cadence’s Strategic Leap: Acquiring Hexagon’s Design & Engineering Business

Cocotb for Verification. Innovation in Verification

A Big Step Forward to Limit AI Power Demand


Analog Bits Steps into the Spotlight at TSMC OIP

Analog Bits Steps into the Spotlight at TSMC OIP
by Mike Gianfagna on 09-29-2025 at 10:00 am

Analog Bits Steps into the Spotlight at TSMC OIP

The TSMC Open Innovation Platform (OIP) Ecosystem Forum kicked off on September 24 in Santa Clara, CA. This is the event where TSMC recognizes and promotes the vast ecosystem the company has created. After watching this effort grow over the years, I feel that there is nothing the group can’t accomplish thanks to the alignment and leadership provided by TSMC. Some ecosystem members are new and are finding their place in the organization. Others are familiar names who have provided consistent excellence over the years. Analog Bits is one of the companies in this latter category. Let’s examine what happens when Analog Bits steps into the spotlight at TSMC OIP.

What Was Announced, Demonstrated and Discussed

Analog Bits always arrives at industry events like this with exciting news about new IP and industry collaboration. At TSMC OIP, the company announced its newest LDO, power supply droop detectors, and embedded clock LC PLL’s on the TSMC N3P process.  Clocking, high accuracy PVT, and droop detectors were also announced on the TSMC N2P process.

Here is a bit of information about these fully integrated IP titles:

  • The scalable LDO (low drop-out) regulator macro addresses typical SoC power supply and other voltage regulator needs.
  • The droop detector macro addresses SoC power supply and other voltage droop monitoring needs. It includes an internal bandgap style voltage reference circuit which is used as a trimmed reference to compare the sampled voltage against.
  • The PVT sensor is a highly integrated macro for monitoring process, voltage, and temperature on chip, allowing very high precision even in untrimmed usage. The device consumes very little power even in operational mode, and leakage power only when temperature measurement is complete.
  • The PLL addresses a large portfolio of applications, ranging from simple clock de-skew and non-integer clock multiplication to programmable clock synthesis for multi-clock generation.

These announcements were also backed up with live demonstrations in the Analog Bits booth at the show. The demos included:

  • High accuracy PVT sensors, high performance clocks, droop detectors, and more on the TSMC N2P process
  • Programmable LDO, droop detector, high accuracy sensors, low jitter LC PLL and more on the TSMC N3P process
  • Automotive grade pinless high accuracy PVT, pinless PLL, PCIe SERDES on the TSMC N5A process
Analog Bits booth at TSMC OIP

Analog Bits also participated in the technical program at OIP with two joint papers. 

One with Socionext titled “Pinless PLL, PVT Sensor and Power Supply Spike Detectors for Datacenter, AI and Automotive Applications”.

The other was with Cerebras titled “On-Die Power Management for SoCs and Chiplet” at the virtual event.

While discussing Analog Bits’ new intelligent energy and power management strategy, Mahesh Tirupattur, CEO at Analog Bits commented:

“Whether you are designing advanced datacenters, AI/ML applications, or automotive SoC’s, managing power is no longer an afterthought, it has to be done right at the architectural phase or deal with the consequences of not doing so . We have collaborated with TSMC and trailblazed on our IP development with advanced customers to pre-qualify novel power management IP’s such as LDO, droop detectors, and high-accuracy sensors along with our sophisticated PLL’s for low jitter. We welcome customers and partners to see our latest demos at the Analog Bits booth during this year’s TSMC OIP event.”

Recognition

TSMC also recognizes outstanding achievement by its ecosystem partners with a series of awards that are announced at the show. For the second year in a row, Analog Bits received the 2025 OIP Partner of the Year Award from TSMC in the Analog IP category for enabling customer designs with broad portfolio of IPs to accelerate design creation. This is quite an accomplishment. Pictured at the right is Mahesh Tirupattur receiving the award at OIP.

Mahesh also created a short video for the TSMC event. In that video, he discusses the significance of the collaboration with TSMC, not just in 2025 but over the past two decades. He talks about the age of AI explosion, and the focus Analog Bits has to deliver safe, reliable, observable and efficient power. He talks about the benefits of delivering advanced low power mixed signal IP on TSMC’s 2 and 3 nm technologies. It’s a great discussion, and you can now view it here.

To Learn More

You can learn more about what Analog Bits is doing around the industry on SemiWiki here. You can begin exploring the billions of IP solutions Analog Bits has delivered on the company’s website here.  The TSMC Open Innovation Platform Ecosystem Forum will be held in other locations around the world. Analog Bits will be attending as well. You can learn more about this important industry event here.  And that’s what happens when Analog Bits steps into the spotlight at TSMC OIP.