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Analysis and Exploration of Parasitic Effects

Analysis and Exploration of Parasitic Effects
by Daniel Payne on 07-23-2025 at 10:00 am

parasitc elements min

With advanced semiconductor processes continuing to shrink, the number and complexity of parasitic elements in designs grows exponentially contributing to one of the most significant bottlenecks in the design flow. Undetected parasitic-induced issues can be extremely costly, often resulting in tape-out delays.

Silvaco addresses this challenge with its EDA tool, Viso, which enables intelligent exploration of parasitic effects. Viso helps designers identify and resolve the root causes of parasitic-induced issues early in the design cycle, significantly improving design reliability and reducing time-to-market.

Carlos Augusto Berlitz, PhD , Corporate AE at Silvaco presented a webinar on their Viso tool, so here’s what I learned about its features for parasitic exploration, analysis and debug:

  • RC Delays and Resistances: global node-to-node and detailed calculation
  • Net-to-Net Coupling: sensitive nets verification, coupling map
  • Net comparison: Resistances, RC delays,
Coupling capacitances
  • Sanity Checks: DC path, instances, dangling nodes, etc.

Users can find detailed information about their parasitics, like layer contributions, a heatmap for visualization, tables and charts.  You don’t have to resort to time-consuming manual analysis approaches and excessive SPICE simulations.

Carlos demonstrated Viso with an example high-speed circuit for LVDS operating at 1.2V where a differential signal is used to reduce electromagnetic noise.

Comparing the pre-layout netlist versus post-extracted simulation shows that the duty-cycle had been degraded, so the challenge was to find out how to make the duty-cycle more balanced. Shown in blue is the plot of the schematic netlist with a 53% duty-cycle, and the orange plot is from the post-extracted netlist with a 37% duty-cycle.

Viso was used to look at different nets in the path of the input signal to the output to determine the biggest net contributors to RC delays. Here’s the cumulative RC delay on four nets in the path, where blue is the shortest delay and red is the longest delay.

Once a net has been identified, the tool further shows the highest contributors to the path delay, speeding up the analysis process, all without having to run a SPICE circuit simulator. Tool users can visualize the main layer contributors in tables and charts and even see how sensitive the results are to changes in each layer.

Diving deeper, the tool shows parasitic resistance by each layout segment, so designers and layout engineers know exactly what in the layout is contributing most to RC delays. Knowing where in the layout the largest RC contributors are located allows them to make corrections with precision and fewer iterations. The what-if feature allows you to recalculate the analysis quickly to explore the impact of fixes all without changing the layout. Based on the RC analysis so far, a layout change was made and then the parasitics extracted, yielding an acceptable improvement to a 40% duty-cycle.

Another useful feature in Viso is comparing two nets to verify that they are matched by parasitic resistance, RC delay or capacitive couplings. Differential pairs with imbalances can be quickly spotted. From the example LVDS it was discovered that the RC delay and parasitic capacitive couple were balanced on nets rxin1 and rxin2, but the balance of parasitic resistances between both paths could be improved as shown in the resistance path comparison plot with red points.

The resistance contribution of layer C2 between nets rxin1 and rxin2 were not balanced, identified by Viso in the bar chart comparison.

Capacitive coupling between nets can also be compared to see how it impacts RC delays. When you need to balance capacitive coupling, this is a quick method to use. Another useful feature is analyzing capacitive coupling comparisons by aggressor nets, something not easy to do with traditional parasitic analysis methods.

Summary

With the newer approach using Viso your team can perform analysis of parasitic effects more thoroughly, in less time, with fewer resources and fewer iterations. Using Viso allows engineers to debug and fix parasitic issues early, thus reducing lengthy design cycles. Finding key layout segments where parasitics limit performance is now possible, even tasks like parasitics balancing and matching of differential signals and differential pairs becomes feasible. IC design teams will benefit by adding Viso to their tool flow.

Watch the archived webinar online.

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Siemens Proposes Unified Static and Formal Verification with AI

Siemens Proposes Unified Static and Formal Verification with AI
by Bernard Murphy on 07-23-2025 at 6:00 am

Siemens Proposes Unified Static and Formal Verification with AI min

Given my SpyGlass background I always keep an eye out for new ideas that might be emerging in static and formal verification. Whatever can be covered through stimulus-free analysis reduces time that needn’t be wasted in dynamic analysis, also adding certainty to coverage across that range. Still, advances don’t come easily. Static analyses are infamously noisy, and formal methods equally infamously demand significant verifier expertise. Apps have made formal proofs more accessible within a bounded set of use-cases, and formal and/or AI complementing static methods have made static analyses more tractable in linting and domain crossing applications. What can be done to broaden the useful scope of static/formal? AI, no surprise, is playing an increasing role in answering that question.

Unifying Stimulus-Free Verification

The promise of both static and formal methods is that whatever they can prove, they can do so quite generally without need to define stimulus; whereas dynamic verification can prove correctness only within the bounds of the use-cases you test. The tradeoff is that useful static and formal proofs are quite restricted in application. Siemens aims to loosen those limits through a new product release they call Questa One SFV (stimulus-free verification), integrating static and formal analysis together with AI.

One objective here is to simplify license management — one license pool to draw on whether you are running static checks, formal checks, or AI-operations, which helps simplify access and improve license utilization. This freedom applies equally to parallel usage, again maximizing utilization no matter what licenses are needed for a particular task.

Questa One Stimulus Free Verification

Importantly under this umbrella, as one example, they can combine natural language understanding to parse a user-requested check, and from that generate and verify a property assertion. Similarly, linting checks can be filtered by formal methods to suppress much of the noise common to such static analysis, leaving only truly suspicious cases for DV/design resolution.

In this paper Siemens hints at applying this suite of capabilities to a more challenging requirement. While Questa One already supports a formal VIP library covering a range of needs, including AMBA compliance, it is not uncommon for design houses to adapt protocol standards to their own needs. For example, they might have a modified version of AHB for which they need their own compliance properties suite. Siemens asserts that Questa One SFV could handle this through generative methods, starting from the custom spec as input. They also suggest that partitioning large formal proofs can be automated through SFV, adding scalability to formal methods.

What else might be possible?

Continuing the theme of mixing AI, static, and formal, bug triage of various flavors is already in active deployment, especially around CDC and RDC analysis where I know that unsupervised learning techniques are used for grouping a large number of error reports into likely common root causes.

Another interesting application came up in a recent DAC panel for detecting naming-convention compliance violations (remember those from the Reuse Methodology Manual?). Turns out that adhering to naming conventions is becoming more important in support of equivalence checking and also, I would guess, in AI learning and inference support across design and (formal) testbench file structures. Yet, no surprise, designers aren’t always conscientious in following these rules (my design simulates and synthesizes correctly, who needs naming rules?).

More generally, I am holding out hope that AI can help scale the app concepts to something more flexible. The AHB application mentioned earlier is one example.

Interesting ideas. You can read the white paper HERE.


Memory Innovation at the Edge: Power Efficiency Meets Green Manufacturing

Memory Innovation at the Edge: Power Efficiency Meets Green Manufacturing
by Admin on 07-22-2025 at 10:00 am

Figure 1

By Tetsu Ho

With the ever-increasing global demand for smarter, faster electronic systems, the semiconductor industry faces a dual challenge: delivering high-performance memory while reducing environmental impact. Winbond is meeting this challenge head-on by embedding sustainability into every layer of its operations—from green manufacturing processes to low-power memory innovations designed for AI, automotive, and industrial applications.

One of Winbond’s most significant innovations is its Customized Memory Solution (CMS)—a next-generation DRAM portfolio tailored for application-specific performance and power efficiency. Evolving from Winbond’s extensive DRAM heritage, CMS integrates advanced low-power architectures and 3D packaging like KGD 2.0 to meet the needs of edge AI, industrial automation, smart cities, and healthcare systems.

Green Manufacturing Starts at the Fab

Winbond’s fabrication site at Taichung, the Central Taiwan Science Park, is one of its most energy-efficient semiconductor facilities. Built with sustainability in mind, the Taichung Fab now operates on 90% renewable electricity, achieving a 60% reduction in carbon emissions compared to 2021. Its cleanroom and utility systems are optimized under the ISO 50001 energy management standard, while ISO 14064-1 and ISO 14067 certifications ensure accurate tracking of facility and product-level emissions.

Manufactured in Winbond’s green-certified fabs, CMS is an essential component of the company’s sustainable product strategy. Every CMS device benefits from a supply chain powered by 90% renewable electricity and is tracked through Winbond’s proprietary carbon accounting system, ensuring visibility of Scope 1, 2, and 3 emissions.

Winbond has committed to achieving RE50 by 2030, with half of its global energy consumption sourced from renewable sources. Its proprietary carbon inventory system accounts for Scope 1, 2, and 3 emissions, providing the company and its customers with clear visibility into environmental impact across the supply chain. This digital-first approach aligns with Taiwan’s carbon fee policy and prepares Winbond’s ecosystem for the rising demand for audited ESG data.

1.2V Serial NOR Flash: First in the Industry for Ultra-Low Voltage

Reducing system power begins at the component level. Winbond’s 1.2V Serial NOR Flash—the first in mass production—is a key step forward for energy-conscious design. This memory is built on a 45nm process, which significantly lowers active and standby power. It is ideal for battery-powered applications such as smart meters, wearables, and medical monitoring devices. This NOR Flash reduces the need for voltage regulators and extends battery life.

This enables designers to meet efficiency targets without compromising performance or reliability.

GP-Boost DRAM: High-Throughput, Low-Power Memory for Edge Intelligence

Winbond’s GP-Boost DRAM is designed for applications that require fast, continuous data processing at the edge, such as machine vision, real-time industrial control, or AI-enabled sensor hubs. Based on 20nm and advanced 16nm process nodes, it delivers high bandwidth and thermal stability while maintaining tight power budgets.

GP-Boost DRAM plays a key role in enabling real-time decision-making in embedded AI systems, without the need for active cooling or large energy reserves, making it a strong fit for both industrial and automotive markets.

CMS has already enabled a broad spectrum of intelligent systems—from motion control in factory automation and electric vehicle (EV) chargers, to secure medical devices, smart home systems, and AI-powered sensor hubs in smart cities. These deployments demonstrate how customized memory can extend device lifetime, reduce power draw, and support carbon reduction across vertical markets.

Octal and SLC NAND: Designed for Harsh Environments and Secure Performance

High-endurance Flash memory is essential in mission-critical systems, especially in automotive, industrial automation, and factory control applications. Winbond’s OctalNAND and SLC NAND Flash are built to withstand wide temperature fluctuations, intensive read/write cycles, and demanding performance requirements over long deployment periods.

Built-in bad block management, OTA (over-the-air) update support, and functional safety compliance help reduce failure rates and lower the environmental cost of field servicing or component replacement.

Embedded Security with Energy Efficiency: TrustME® Secure Flash

As embedded systems become more connected and vulnerable, data protection and sustainability are increasingly linked. Winbond’s TrustME® Secure Flash enables secure firmware storage, cryptographic key protection, and authenticated updates—all within a low-power profile optimized for edge and automotive environments.

By supporting secure OTA updates, Secure Flash helps extend device lifetime and reduces unnecessary physical servicing, ultimately lowering emissions and costs.

A Proven Commitment to ESG and Innovation

Winbond’s commitment to environmental, social, and governance (ESG) principles is embedded across its global operations—from how it sources raw materials to how it powers its fabs. Its sustainability performance has earned consistent external recognition, including the Taiwan Corporate Sustainability Awards (TCSA) ESG Award, the Corporate Sustainability Report Platinum Award, and a spot on the Top 100 Global Innovators list, acknowledging its technical leadership and responsible business practices.

A dedicated ESG Committee governs sustainability strategy, aligning with internationally recognized frameworks such as the Task Force on Climate-related Financial Disclosures (TCFD), the Responsible Business Alliance (RBA), and the Greenhouse Gas Protocol. The company publishes annual disclosures on emissions, energy use, and supply chain risk, including a Human Rights Due Diligence Report and a TCFD-aligned climate risk assessment.

Winbond’s environmental credentials are supported by third-party verified certifications, including but not limited to:

  • ISO 14001 (Environmental Management Systems)
  • ISO 14064-1 (Greenhouse Gas Emissions Inventory)
  • ISO 14067 (Product Carbon Footprint)
  • ISO 14046 (Water Footprint)
  • ISO 50001 (Energy Management System)
  • ISO 45001 (Occupational Health & Safety)

Winbond exceeds industry requirements by actively tracking Scope 3 emissions across its supply chain, utilizing its digital carbon accounting system. As a member of the Taiwan Climate Partnership (TCP), the company also works closely with other leading manufacturers to support shared decarbonization goals across the sector.

Whether switching to renewable energy early on or designing ultra-efficient memory products like the 1.2V Serial NOR Flash, GP-Boost DRAM, or CMS, Winbond is helping its customers reduce the carbon footprint of their end products. They’re shaping a more sustainable and resilient future for the semiconductor industry with a clear focus on transparency, measurable results, and practical action.

Conclusion: Sustainable Memory That Performs

Winbond’s sustainable semiconductor strategy is anchored in three core pillars: green fabs, green products, and green partnerships. By combining technical innovation with measurable sustainability gains, Winbond empowers OEMs and developers to create smarter, faster, and more environmentally responsible systems—from AI vision modules and electric vehicles to smart homes and industrial controllers.

Whether extending battery life, improving thermal performance, securing over-the-air updates, or ensuring environmental compliance, Winbond delivers the memory foundation for today’s high-performance, low-impact designs. Discover the complete portfolio at www.winbond.com.

Tetsu Ho, Technology Manager, holds a master’s degree in Industrial Engineering from National Tsing Hua University. He joined Winbond in 2005 and subsequently served as Product Engineer, Product Development Manager, and Marketing Technology Manager, and is responsible for promoting the EU DRAM market.

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Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 Roadmap

Alchip Launches 2nm Design Platform for HPC and AI ASICs, Eyes TSMC N2 and A16 Roadmap
by Daniel Nenni on 07-22-2025 at 6:10 am

Alchip TSMC N2 announcement SemiWiki

Alchip Technologies, a global leader in high-performance computing (HPC) and AI infrastructure ASICs, has officially launched its 2nm Design Platform, marking a major advancement in custom silicon design. The company has already received its first 2nm wafers and is collaborating with customers on the development of high-performance ASICs built on this next-generation node. This milestone positions Alchip among the earliest adopters of TSMC’s leading-edge technologies, with a clear roadmap that extends to both TSMC’s N2 (2nm) and upcoming A16 (1.6nm) process technologies.

Advanced Chiplets and Packaging for 2nm Compute Systems
The new design platform delivers a full-stack methodology for building compute-dense, power-efficient ASICs on TSMC’s N2 node. It supports a broad set of chiplet integration strategies, enabling 2nm compute dies to work in tandem with 3nm or 5nm I/O chiplets. This approach supports a heterogeneous architecture that optimizes performance, yield, and design flexibility—critical in the post-Moore’s Law era.

Alchip’s platform also supports TSMC’s CoWoS®-S/R/L 2.5D/3D packaging, System on Integrated Chip (SoIC®-X) bonding, and is on track to support System on Wafer (SoW™) packaging for 3DICs. Additionally, die-to-die (D2D) IP and IO chiplet development are built into the platform, ensuring robust interconnect and thermal-aware design.

Overcoming N2 Design Complexity

TSMC’s N2 process represents its first gate-all-around (GAAFET) node, replacing FinFETs with nanosheet transistors. This shift offers notable benefits in performance, power efficiency, and area (PPA), with up to 10–15% speed gain or 25–30% power reduction over N3E. However, it also introduces significant layout and manufacturing challenges. These include tighter design rules, more complex power and signal routing, and new constraints around nanosheet stacking and variability.

Alchip’s 2nm Design Platform is engineered to address these issues head-on. The design flow is optimized to manage the increased diversity of standard cells and the denser transistor layouts introduced at N2. By anticipating placement, routing, and power integrity challenges early in the design process—before floorplanning or clock tree synthesis—Alchip reduces turnaround time while enhancing design predictability.

Power and Thermal Density Solutions

At 2nm, power and thermal density per square millimeter rise significantly due to increased gate counts and faster switching. Alchip’s methodology addresses this with thermal-aware floorplanning, advanced packaging co-optimization, and strategic power distribution planning. Even in the absence of native 2nm I/O chiplets, the platform supports mixed-node integration using 3nm and 5nm I/O for early deployment and yield optimization.

First-Pass Success, SoIC Demonstration, and A16 Transition

Alchip’s 2nm test chip achieved first-pass silicon success, validating both its methodology and IP stack. The design featured the company’s proprietary AP-Link-3D I/O interface, demonstrating full compatibility with SoIC-X chiplet interconnect. These results reinforce Alchip’s leadership in 3D integration and position it well for TSMC’s future process nodes, including A16™, which introduces backside power delivery and further transistor performance improvements.

Positioning for the TSMC N2 Era

TSMC began risk production on N2 in late 2024, with volume ramp expected in the second half of 2025. N2 introduces nanosheet GAAFETs, enabling better electrostatic control and design flexibility with variable channel widths. Alchip’s 2nm platform ensures customers are equipped to tap into these benefits while mitigating the risks associated with early-node development.

“We’re open for business and ready to support customers’ 2nm demand,” said Erez Shaizaf, CTO of Alchip Technologies. “Our new platform positions us as an industry leader, not only at 2nm but as we prepare for TSMC’s A16 era.”

“The is really just another milestone on our 2nm roadmap. Alchip’s 2nm platform is ready to work with key IP vendors, and we’ve been actively engaged with a couple of different companies on their 2nm ASIC developments. We anticipate this to be a very popular node for high-performance computing innovation,” explains Dave Hwang, General Manager, North America Business Unit.

Contact Alchip

About Alchip

Founded in 2003 and headquartered in Taipei, Alchip Technologies Ltd. is a leading global ASIC provider, specializing in HPC and AI applications. Its services span ASIC design, chiplet integration, 2.5D/3D packaging, and manufacturing management. Alchip serves top-tier system companies worldwide and is listed on the Taiwan Stock Exchange .

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Agile Analog Update at #62DAC

Agile Analog Update at #62DAC
by Daniel Payne on 07-21-2025 at 10:00 am

agile analog min

On the last day of DAC 2025 I met with Chris Morrison, VP of Product Marketing at Agile Analog, to get an update. Their company provides Analog IP, the way you want it, and I knew that they had internal tools and a novel methodology to speed up the development process. This year they have started talking more about their internal IP automation tool, Composa.

Why use an analog IP automation tool?

Chris told me that there’s a list of challenges with conventional analog design: shortage of analog designers, too many processes and options, advanced nodes are difficult with new parasitics, and manual analog design is way too slow. Their answer was to address these challenges by using analog IP automation.

The approach is to combine Analog experts inside of the company along with SW developers to auto-generate schematics for IP. Their Composa tool works with OpenAccess, the API from the Si2 OpenAccess coalition. Composa users first define their requirements, like SNR, supply rails, bandwidth and other specifications. Then, there are a set of common analog building blocks, elements with their own characteristics that are combined to define the new IP. For example, an Analog to Digital Converter (ADC) needs a sample switch, input buffer and other blocks. These lower-level blocks are combined, a PDK is selected for a specific process, then the tools optimize the transistor W/L sizes using math equations.

A traditional approach to circuit sizing involves running lots of SPICE simulations, but Composa uses a much faster method of equation-based device sizing. With circuits that have feedback, then some SPICE runs could be used. The optimization process with Composa is not CPU intensive at all, typically requiring only a few minutes of CPU time to come up with the proper device sizes to meet your specifications. Full verification of the analog IP  is done with a traditional flow, including many Monte Carlo simulations. There’s little, or no, manual-tweaking of device sizes required to meet your specs.

With Composa the engineers at Agile Analog can get to the exact specs for an IP block in minutes, not days or weeks of manual efforts. Even changing to a different PDK will show new results in just a few minutes.

Customers of Agile Analog span a broad range of sectors and applications: Power Management ICs (PMIC), data converters, chip health and monitoring, PVT, IoT, defense, , security, anti-tamper IP, voltage glitching, clocking attacks, electromagnetic injection. Defense customers could be designing at 165nm or 130nm process nodes, datacom at 3nm, so Composa creates analog IP for quite a wide spectrum of processes.

Digital designers have used logic synthesis to retarget process nodes for decades  and this is now possible with analog design. If a customer wants a new oscillator, then Composa can be used to create a schematic and layout. Composa is an expert system  – it is repeatable, human understandable, and device sizing is not a probability problem.

Composa is a no-code system for users, its parameters are typed in a YAML script to configure what you want. Internally they just fill in the YAML to control each IP block generator. Composa has changed over time by expanding the element library, and verifying that it works across all PDKs, including some tuning for a new PDK. The Composa tool has created some 60 new IPs in the last 2 years..

Analog security IP is of special interest for the Agile Analog team as security has become a critical requirement for every SoC being developed. The company believes that it can offer differentiated anti-tamper solutions that are complementary to other providers of RoT (Root of Trust) and cryptographic engines, delivering value at the subsystem level with their security IP offerings. Another focus area is their data conversion IP solutions. They are working with a strategic customer to deploy their 12 bit ADC on the latest TSMC nodes.

Agile Analog is based in the UK, while Krishna Anne, the CEO is in the valley. 2025 has been another good year of revenue growth at the company. Visit their website for more product information. They have direct sales in US and Europe, with some distributors in Taiwan, Korea and China. Catch up with the Agile Analog team at the GlobalFoundries and TSMC events.

Summary

Analog IP is in high demand, but the older manual methods to hand-craft IP just take too long and require expert experience. Agile Analog has a different approach using their Composa tool to automate the IP creation process, with a library of analog building blocks. What used to take days or weeks of engineering effort now can be accomplished in minutes with this new methodology, significantly reducing the complexity, time and costs associated with traditional analog IP.

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Protecting Sensitive Analog and RF Signals with Net Shielding

Protecting Sensitive Analog and RF Signals with Net Shielding
by Admin on 07-21-2025 at 6:00 am

fig1 net shielding 72dpi

By Hossam Sarhan

Communication has become the backbone of our modern world, driving the rapid growth of the integrated circuit (IC) industry, particularly in communication and automotive applications. These applications have increased the demand for high-performance analog and radio frequency (RF) designs.

However, designing analog and RF circuits can be quite challenging due to their sensitivity to various factors. Changes in layout design, operating conditions, and manufacturing processes can all have a significant impact on circuit performance. One of the major hurdles faced by analog designers is the issue of noise coupling between interconnects.

The proximity and interactions between different circuit elements can lead to signal noise, which can degrade the overall circuit performance. This is a critical concern, as analog and RF circuits are more susceptible to proximity effects, such as crosstalk and coupling noise, compared to their digital counterparts.

Mitigating noise coupling with net shielding

One of the widely used techniques to protect critical nets in analog and RF circuit designs is net shielding. This approach involves surrounding the sensitive signal nets with power or ground nets, which create a shielding effect that helps mitigate the impact of electromagnetic interference and crosstalk on the critical signal traces.

The power and ground nets, with their stable and low-noise characteristics, act as a barrier to isolate the critical signals from noise sources. This shielding helps maintain the integrity of the sensitive signals, preventing unwanted noise and disturbances. Figure 1 illustrates net shielding.

Figure 1: Net shielding methodology.

Additionally, the geometries belonging to the same net, when placed in close proximity to each other, can also act as a form of self-shielding. The proximity of the same-net traces creates a shielding effect, further protecting the critical signals from external interference.

By employing net shielding techniques, circuit designers can effectively safeguard the performance and reliability of analog and RF circuits, ensuring that the critical signals are isolated from noise sources and maintain their intended behavior.

Verifying net shielding effectiveness

Verifying the effectiveness of net shielding is not a straightforward task, as it requires tracing the critical net segments and checking the surrounding nets to confirm how much of the victim net is shielded. This process can be time-consuming and error-prone if done manually.

To address this challenge, designers can adopt an advanced reliability verification platform that provides comprehensive net shielding verification. A solution like Calibre PERC from Siemens EDA offers a packaged checks framework for net shielding verification that automates the verification process, streamlining the design validation workflow. This framework permits simple selection and configuration of pre-coded checks, maximizing ease-of-use and minimizing runtime setup. Calibre PERC packaged checks are provided as well dedicated checks to enhance the reliability of analog circuits.

The input for the packaged checks flow is a user configuration file with specified checks and their parameters. This input constraint file is processed by a package manager, which accesses the checks database and creates a rule file containing all of the selected checks, with the proper configuration parameters to run on the designated design. Figure 2 shows the net shielding setup using Calibre PERC packaged checks GUI.

Advance net shielding checks allows designers to specify the critical nets in their design and the minimum shielding percentage threshold required. The verification tool then automatically traces each critical net, analyzes the surrounding shielding nets and calculates the shielding percentage for each net.

The verification results can be viewed and cross-probed in the layout to help with debug.

By leveraging automated net shielding verification, designers can quickly and reliably validate the effectiveness of their net shielding implementation, ensuring that the critical signals are adequately protected from noise sources. This streamlined approach helps designers identify and address any net shielding issues, enhancing the overall reliability and performance of their analog and RF circuits.

The key benefits of using an advanced net shielding verification tool include:

  • Automated verification: The platform’s dedicated net shielding check eliminates the manual and error-prone process of tracing net segments and calculating shielding coverage, saving designers significant time and effort.
  • Streamlined integration: The platform’s packaged checks framework allows designers to easily integrate net shielding verification into their overall design validation flow, enabling them to combine multiple reliability checks into a single validation run.
  • Improved reliability: By quickly and reliably validating the effectiveness of net shielding implementation, the advanced platform helps designers identify and address any issues, ensuring the overall reliability and performance of their sensitive analog and RF circuits.

Conclusion

Protecting critical signals from noise coupling is a crucial aspect of successful analog and RF circuit design. Net shielding is a widely used technique that involves surrounding sensitive signal nets with power or ground nets to create a shielding effect, mitigating the impact of electromagnetic interference and crosstalk.

However, verifying the effectiveness of net shielding can be a challenging task. Fortunately, solutions exist. Designers can easily adopt an advanced reliability verification platform to provide automated and streamlined net shielding verification. With the right tools, designers can quickly identify and address any issues, ultimately enhancing the reliability and performance of their analog and RF designs. Packaged shielding net checks help designers deliver delivering high-quality products that meet the demanding requirements of today’s communication and automotive applications.

About the author:

Hossam Sarhan is a senior product engineer in the Design to Silicon division of Siemens Digital Industries Software, supporting the Calibre PERC reliability platform and Calibre PEX tools. His current work focuses on circuit reliability verification and inductance parasitics extraction. Prior to joining Siemens, he worked in modeling and design optimization for on-chip power management circuits. Hossam received his B.Sc. from Alexandria University, Egypt, his M.Sc. degree from Nile University, Egypt, and his Ph.D. from CEA-LETI, Grenoble, France.

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Executive Interview with Matthew Addley

Executive Interview with Matthew Addley
by Daniel Nenni on 07-20-2025 at 10:00 am

Matthew Addley SemiWiki Interview

Matthew Addley is an Industry Strategist at Infor, specializing in the global manufacturing sector. With over 30 years of experience in driving business transformation through technology, he aligns industry needs with Infor’s product strategy through thought leadership, customer engagement, and market insight. Beginning his career in the UK aerospace and defence industry, Matthew now spends much of his time in the Asia Pacific region operating from his home office in Sydney, Australia, bringing a global perspective across mature and emerging markets in ERP, manufacturing and supply chain excellence, and the increasing value of platform technologies.

What are the common supply chain and operational challenges you see among your customers?

Across industries and regions, a recurring theme we hear about is the difficulty of achieving true collaboration throughout the supply chain. Interestingly, the specific pain points can differ depending on where you’re located. For example, in the U.S., customers will often say, “Our suppliers aren’t collaborating with us,” while in Thailand, the sentiment is flipped: “Our customers aren’t collaborating with their suppliers.” The underlying issue (a breakdown in coordinated communication) is consistent, but perceptions of where the problem originates shift depending on regional context.

Another major challenge is the need to respond quickly and efficiently to change. The need for resilience and responsiveness has never been higher, as global supply chains continue to face geopolitical disruptions and lingering fragility from past events. As a result, organizations are under pressure to adapt rapidly to changes in demand, supply shortages, and pricing fluctuations.

At the operational level, one challenge that’s often overlooked, but at the same time is incredibly impactful, is onboarding new employees on the shop floor. We’re seeing a massive generational knowledge shift, where the people with deep knowledge of processes are retiring or moving on, and that knowledge is often left undocumented. It becomes extremely difficult to maintain production efficiency when newer workers are left to figure things out on their own. We deliver enterprise applications to bridge that gap by making processes more visible and repeatable, turning experience into data that everyone can use.

Infor’s How Possible Happens report found that while 75% of global companies surveyed expect 20%+ gains from technology but our evidence suggests that, without the focus on bulletproof processes, agility, and customer-centricity that our solutions provide, many fail to reach their objectives. We partner to help organizations better anticipate and adapt to supply chain disruptions, proving that visibility and agility are more than buzzwords. They’re measurable outcomes.

What specific challenges or use cases have you seen in the semiconductor industry, and how are you helping customers address them?

The semiconductor industry faces unique challenges related to supply chain fragility and component sourcing. One specific issue is ensuring the consistent quality of highly specialized parts across different suppliers. Historically, many manufacturers relied on a single supplier to meet the necessary minimum order quantities. But that approach is becoming increasingly risky.

We enable what we call “true dual sourcing,” which is the ability to proactively manage multiple suppliers for the same part, rather than just defaulting to the one that offers the right quantity. More importantly, we track and manage quality and other performance measures across suppliers so that if a company shifts from one supplier to another, they can establish and maintain confidence in quality. We also allow customers to allocate supply based on historical performance, essentially increasing resilience.

In addition, we track parts beyond just the generic descriptors of form, fit, and function. We capture the manufacturer’s part number, which gives far more granular insight and allows our customers to know whether a part can be used in a highly specific application or only in a generic context. That’s critical in semiconductor manufacturing and downstream activities, where a seemingly identical part from two different sources might not behave the same way. With our system, customers gain the visibility they need to make those nuanced decisions.

One semiconductor manufacturer cited in the How Possible Happens report saw a 40% reduction in time spent on quality-related supplier follow-ups after implementing Infor’s solution, which is a great example of how precise data and supplier insights drive better decision-making.

Where does your solution outperform your competitors?

Where Infor really shines is in operations, especially in areas like production, supply chain planning, and execution.

We often hear from our customers that “our operations are cleaner and better with your solution.” That’s because we’re built with manufacturing and supply chain complexity in mind, not just financial reporting. In fact, our financial modules are strong enough to support global operations, but they don’t need to be over-engineered because we reduce the amount of rework required. We’re able to capture accurate data at the point of production, which flows directly into financial processes, minimizing the need for reconciliation.

The challenge for us is that CFOs are sometimes comfortable with Infor’s competitors. One of our goals is to reassure them that we’re not trying to immediately overhaul everything, especially not their core financial systems. Instead, we often coexist with them initially, while bringing real-time, detailed operational visibility to the production floor. That’s where we outperform: in helping customers operate more efficiently day-to-day.

And customers are seeing the difference: 64% of Infor users report improved operational efficiency within 12 months of go-live, underscoring our ability to drive immediate, meaningful value where it matters most.

How do you ensure flexibility while maintaining a prescriptive product approach?

We take a prescriptive approach where it makes sense, but we know that not every customer fits into a single mold. That’s why we maintain a verticalized product management structure. When a customer comes to us with a unique need, we first ask: “Is this a one-off requirement, or is it something we’re hearing across the industry?” If it’s a common issue, we’ll prioritize building it into the product roadmap. If it’s a one-off, we offer customization through cloud extensibility.

One key advantage of our platform is that customizations don’t break during upgrades. In many legacy ERP systems, custom code can derail an entire upgrade process, forcing customers to rework configurations every 6–12 months. With Infor, upgrades are seamless because we offer a tailored experience without sacrificing agility or incurring high maintenance costs. This is especially important for companies that need to adapt quickly while remaining within budget.

How does your partner ecosystem support customer success across different segments, from SMBs to large enterprises?

Our partner ecosystem is one of our most important assets. We work with a range of partners, from regional experts and boutique consulting firms to global systems integrators like Deloitte. These partners help us deliver localized, industry-specific support to customers of all sizes.

Infor’s CloudSuite solutions play a central role in enabling this success. Built on a multi-tenant cloud architecture, CloudSuite gives businesses of all sizes the ability to scale quickly, respond to market changes with agility, and gain real-time visibility into operations across the enterprise. Our partners are trained to leverage these capabilities to help customers drive faster time-to-value, reduce IT complexity, and improve transparency across the board.

For mid-market and enterprise clients, particularly in multi-tier manufacturing or semiconductor settings, we often operate in a “two-tier” ERP model: running on the shop floor while headquarters uses a different enterprise system. In these cases, our partners help ensure seamless data flow and coordination between the two systems.

For SMBs, our partners play a critical role in delivering fast, cost-effective implementations. These customers often don’t have large IT teams, so our partners step in as both implementers and ongoing advisors, sometimes even serving as virtual CIOs or COOs. The goal is to meet customers where they are and provide the right level of support based on their size, industry, and growth trajectory. And it’s working, with 79% of Infor customers saying that moving to CloudSuite helped them scale more quickly and respond to business changes with greater agility.

What is your approach to incorporating new technologies like AI and machine learning?

We don’t believe in handing customers a generic AI toolkit and saying, “Go figure it out.” Instead, we’re focused on delivering purpose-built, scenario-driven AI solutions that solve specific, tangible problems.

Take contract analysis in the electronics industry, for example. Service terms in these contracts are critical and comparing them manually is time consuming and error-prone. We’re using generative AI to help partners instantly analyze and compare service terms across contracts. This drastically reduces the time and effort required to make informed decisions, particularly in fast-moving environments where speed and accuracy are essential.

Infor Velocity Suite plays a key role in how we enable rapid, value-driven innovation. It provides a foundation of pre-built, industry-specific accelerators and extensible AI capabilities that help customers deploy and scale technology quickly without needing to start from scratch. With Velocity, we’re able to deliver advanced features like AI-driven supply chain planning, inventory optimization, and predictive maintenance in a way that’s tailored to each customer’s industry context.

We always prioritize practical value over hype. We’re not here to sell AI for AI’s sake. We’re here to make it work for our customers—in ways they can deploy today and see results from tomorrow.

Also Read:

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CEO Interview with Jonathan Reeves of CSignum

CEO Interview with Jonathan Reeves of CSignum
by Daniel Nenni on 07-20-2025 at 8:00 am

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For more than 30 years, Jonathan has successfully led many start-up ventures, including multiple acquisitions as well as senior operating roles in networking, cloud computing, cybersecurity, and AI businesses.

He co-founded Arvizio, a provider of enterprise AR solutions, was Chairman and co-founder of CloudLink Technologies, which today is part of Dell. He also founded and served as CEO of several networking companies including Sirocco Systems and Sahara Networks.

Tell us about your company?

CSignum’s patented wireless platform is revolutionizing underwater and underground communications by overcoming the limitations of traditional radio, acoustic, and optical systems, unlocking new possibilities for IoT connectivity below the surface.

The company’s flagship product EM-2 product line enables real-time, wireless data transmission from submerged or buried sensors to a nearby surface gateway through many challenging media, including water, ice, soil, rock, and concrete.

The solutions integrate with industry-standard sensors, enabling rapid application deployment, low-maintenance, without the need for surface buoys, pedestals or cables which can clutter natural environments.

What problems are you solving?

CSignum addresses a fundamental connectivity gap by linking data from sensors in submerged and subsurface locations in challenging conditions quickly and easily to the desktop for monitoring and analysis, eliminating the blind spots in critical infrastructure and services.

This opens transformative possibilities for smarter infrastructure, safer operations, and better environmental outcomes on a global scale.

What application areas are your strongest?

CSignum’s strongest application areas are those where reliable, real-time data is needed from environments traditionally considered too difficult or costly to monitor:

  • Water Quality Monitoring: For rivers, lakes, reservoirs, and combined sewer overflows (CSOs), support compliance with evolving environmental regulations.
  • Corrosion Monitoring: For buried pipelines, storage tanks, marine structures, and offshore energy platforms, where monitoring is critical for safety and asset longevity.
  • Under-Vessel Monitoring: Including propeller shaft bearing wear, hull integrity, and propulsion system health for commercial and naval fleets—without dry-docking or through-hull cabling.
  • Urban Infrastructure: Monitoring storm drains, culverts, and wastewater systems in confined spaces.
  • Offshore Wind and Energy: Supporting environmental, structural, and subsea equipment monitoring on and around offshore wind turbines and platforms.
What keeps your customers up at night?

From public water systems and offshore platforms to shipping fleets and underground utilities, our customers are responsible for critical infrastructure. They worry about the impact of not knowing what’s happening below the surface:

  • Missed or delayed detection of environmental incidents, such as sewer overflows, leaks, or pollution events that could lead to regulatory penalties, reputational damage, or public health risks.
  • Undetected equipment degradation, especially corrosion or mechanical wear, that can result in costly failures, downtime, or safety hazards.
  • Gaps in real-time data from buried or submerged infrastructure due to the limits of traditional wireless or cabled systems, particularly in hard-to-access locations.
  • Compliance pressures, especially as governments introduce stricter real-time monitoring and reporting requirements in water, energy, and maritime sectors.
  • Resource constraints: accessing reliable, high-frequency data without adding personnel, vehicles, or costly construction projects.
What does the competitive landscape look like and how do you differentiate?

CSignum is the world’s first commercially viable platform that successfully transmits data through water, ice, soil, and other signal-blocking media, simplifying real-time data collection from the most inaccessible and hazardous locations, reducing risk and cost. No other solution currently achieves this.

The innovation and differentiation lie not just in the core technology but in the range of applications it unlocks: water quality monitoring, corrosion detection in submerged pipelines, tracking structural health of marine infrastructure, and enabling communications in ice-covered or disaster-prone environments.

What new features/technology are you working on?

CSignum is scaling its platform for widespread adoption across water and other utilities, maritime, energy infrastructure, defense, and environmental monitoring, especially through partnerships.

One area of expansion includes under-vessel systems monitoring, where CSignum’s technology enables wireless measurement of propeller shaft bearing wear and propulsion system health, all without the need for through-hull cabling or dry dock access.

In parallel, we will expand our EM-2 product family, launching next-gen models with longer battery life, smaller form factor, enhanced analytics, and plug-and-play compatibility with leading sensor systems. The CSignum Cloud platform will evolve into a hub for predictive diagnostics, anomaly detection, and digital twin integration.

How do customers normally engage with your company?

We work closely with customers to understand the physical constraints, data requirements, and operational goals of their environment.

From there, we guide them through a proof-of-concept or pilot deployment, leveraging our modular EM-2 systems and integrating with their existing sensors or preferred platforms.

Customers value our deep technical support, application expertise, and the flexibility of a platform that requires no cabling, no trenching, and minimal site disruption.

Contact CSigmun

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Podcast EP298: How Hailo is Bringing Generative AI to the Edge with Avi Baum

Podcast EP298: How Hailo is Bringing Generative AI to the Edge with Avi Baum
by Daniel Nenni on 07-18-2025 at 10:00 am

Dan is joined by Avi Baum, Chief Technology Officer and Co-Founder of Hailo, an AI-focused chipmaker that develops specialized AI processors for enabling data-center-class performance on edge devices. Avi has over 17 years of experience in system engineering, signal processing, algorithms, and telecommunications while focusing on wireless communication technologies for the past 10 years.

Dan explores the breakthrough AI processors Hailo is developing. These devices enable high performance deep learning applications on edge devices. Hailo processors are geared toward the new era of generative AI on the edge. Avi describes the impact generative AI on the edge can have by enabling perception and video enhancement through Hailo’s wide range of AI accelerators and vision processors. He discusses how security and privacy can be enhanced with these capabilities as well as the overall impact on major markets such as automotive, smart home and telecom.

Contact Halio

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interview with Shelly Henry of MooresLabAI

CEO Interview with Shelly Henry of MooresLabAI
by Daniel Nenni on 07-18-2025 at 6:00 am

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Shelly Henry is the CEO and Co-Founder of MooresLabAI, bringing over 25 years of semiconductor industry experience. Prior to founding MooresLabAI, Shelly led silicon teams at Microsoft and ARM, successfully delivering chips powering billions of devices worldwide. Passionate about driving efficiency and innovation, Shelly and his team at MooresLabAI are transforming chip development through specialized AI-driven automation solutions.

Tell us about your company.

MooresLabAI, founded in 2025, is transforming semiconductor development using specialized AI automation. With our platform, chip design teams can accelerate their schedules by up to 7x and cut pre-fabrication costs by 86%. We integrate seamlessly into existing workflows, helping semiconductor companies rapidly deliver reliable silicon.

What problems are you solving?

Semiconductor design is notoriously expensive and slow – verification alone can cost tens of millions and take months of engineering effort. Our VerifAgent™ AI platform automates and dramatically accelerates these verification processes, reducing human error and addressing the critical talent shortage facing the industry.

What application areas are your strongest?

Our strongest traction is with companies designing custom AI, automotive, and mobile chips. Our early adopters include major NPU providers and mobile chipset developers who are already seeing impressive productivity gains and significant reductions in costly errors.

What keeps your customers up at night?

They worry about verification delays, costly re-tapeouts, and stretched engineering resources. With MooresLabAI, our customers experience significantly faster verification cycles, fewer late-stage bugs, and can do more with existing resources, easing these critical pain points.

What does the competitive landscape look like and how do you differentiate?

Many current AI tools provide general assistance but are not built specifically for semiconductor workflows. MooresLabAI uniquely offers end-to-end, prompt-free automation designed explicitly for silicon engineering. We seamlessly integrate with all major EDA platforms and offer secure, flexible deployment options, including on-premises solutions.

What new features/technology are you working on?

We are expanding beyond verification to offer complete end-to-end chip development automation—from architecture and synthesis to backend physical design, firmware generation, and full SoC integration. Our modular AI-driven platform aims to cover the entire silicon lifecycle comprehensively.

How do customers normally engage with your company?

Customers typically start with our pilot programs, which clearly demonstrate value with minimal initial effort. Successful pilots transition smoothly into subscription-based engagements, with flexible licensing options tailored to customer needs. For those hesitant about immediate adoption, we also offer verification services to quickly address specific project needs.

Contact MooresLabAI

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