Synopsys’ SLM PVT Monitor (process detector, voltage monitor, temperature sensor) IP can collect voltage, temperature, and process parameters from different blocks within the IC in real time. These data can be analyzed and used to take meaningful action to optimize the performance of the chip at any stage of silicon lifecycle.
Analog/mixed-signal IC design is a critical challenge for ASIC development with tight specifications and ambitious tapeout schedules that are not easy to meet. Many manual design steps from architecture through layout verification limit the amount of early insights and force time-consuming design iterations.
ASIP Designer enables the creation of custom vector DSPs for AI
Wednesday, May 22, 2024
4:00 – 6:00 pm CEST / 7:00 – 9:00 am PT
The revolution in AI triggers an increased awareness for application-specific instruction-set processors
Thursday, May 30, 2024 | 10:00-11:00 a.m. PDT
Many automotive applications require processing workloads with minimum latency and precise timing budgets. This is especially true for safety-critical applications like adaptive cruise control and anti-lock braking, where human life may be jeopardized. These systems require
In partnership with the U.S. Department of Labor’s Office of Disability Employment Policy and The Good Jobs Initiative, CHIPS for America will host this webinar for organizations that serve, support, or otherwise work with the disability community. This will serve as a CHIPS for America program primer and will focus on CHIPS … Read More
Over the past two months, the CHIPS Program Office (CPO) has announced preliminary memorandum of terms (PMTs) with 7 applicants totaling nearly $29 billion as part of the CHIPS and Science Act to revitalize American semiconductor manufacturing. This webinar will discuss the process by which CPO reviews and evaluates applications… Read More
In recent years, the semiconductor industry has experienced a breakthrough in the onset of 2.5D and 3D chiplet-based products. These products promise to extend the limits of Moore’s Law while demolishing limitations on speed and capacity for our highest tiers of compute. But for all the adulation we heap upon the 3DIC paradigm,
Combining market-leading design-for-test (DFT) technologies with best-in-class netlist synthesis allows you to achieve DFT success more quickly. Many customers, including those for emulation and IC test, have challenges with scaling architectures. This webinar describes how Siemens emulation and silicon test solutions
Antenna/RF design problems often involve the optimization of many variables, requiring numerous evaluations (EM simulations) using traditional optimization methods. Design engineers need an intelligent, accurate, and easy-to-use simulation platform and analysis solution that reduces repetitive design cycles while… Read More
Join this webinar to meet Cadence’s comprehensive digital twin solution that facilitates sustainable data center design and modernization, marking a significant leap forward in optimizing data center efficiency and operational capacity. See why industry leaders are praising the ground-breaking Cadence Reality Digital… Read More
