Webinar: In-Field RAS Challenges with Chiplets and AI-based Systems

Webinar: In-Field RAS Challenges with Chiplets and AI-based Systems
by Admin on 04-24-2025 at 11:26 am

Featured Speakers:

  • Jyotika Athavale, Director, Engineering Architecture, Synopsys
  • Yervant Zorian, Chief Architect & Fellow, Synopsys

Abstract:

Advancements in data center and automotive System-on-Chips (SoCs) to meet AI workload demands have resulted in the increased adoption of emerging technology nodes and chiplet… Read More


Webinar: Can Intel Reclaim Its Crown in the Semiconductor World?

Webinar: Can Intel Reclaim Its Crown in the Semiconductor World?
by Admin on 04-24-2025 at 11:00 am

Join David MacQueen and James Sanders as they explore Intel’s bold strategies to regain dominance in the semiconductor industry. With increasing competition from AMD and TSMC, Intel faces significant challenges in its bid to reclaim leadership. This webinar will provide expert insights into the market forces shaping Intel’s… Read More


Webinar: Trump’s Tariff Tensions: What’s Next for the Semiconductor Industry?

Webinar: Trump’s Tariff Tensions: What’s Next for the Semiconductor Industry?
by Admin on 04-24-2025 at 10:58 am

From the U.S. and EU to Southeast Asia and beyond, countries are redrawing the lines of technology competition and economic security. What does it mean for semiconductor design, manufacturing, and supply chains?

How current and proposed semiconductor tariffs are reshaping the global industry

The effects of export restrictions,

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Webinar: Using Veloce PCD to implement an Arm CSS with confidence

Webinar: Using Veloce PCD to implement an Arm CSS with confidence
by Admin on 04-22-2025 at 10:09 am

Software Defines Everything
For today’s SoC and system designs, hardware is designed and optimized for the software workload. Workloads can include firmware, multi-OS architectures, AI/ML and complex graphics. These combined produce large software models that put pressure on system-level verification.

What is the Arm

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Webinar: Boost Verification Efficiency with VC Execution Manager: Harnessing AI/ML for Superior Regression Management

Webinar: Boost Verification Efficiency with VC Execution Manager: Harnessing AI/ML for Superior Regression Management
by Admin on 04-18-2025 at 9:48 am

Featured Speakers:

  • Gopinath Lakshmi Narasimhan, Sr. Architect Applications Engineer
  • Robert Ruiz, Sr. Director, Product Management

Why You Should Attend:

  • Discover the innovative capabilities of Synopsys VC Execution Manager for streamlined verification processes.
  • Learn about the seamless integration of advanced AI/ML
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Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 04-09-2025 at 2:36 am

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

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Webinar: PCIe 7.0? Understanding Why Now is the Time to Transition

Webinar: PCIe 7.0? Understanding Why Now is the Time to Transition
by Admin on 04-07-2025 at 3:16 am

Join us for an Q&A technical session with Madhumita Sanyal, technical product director of HPC IP, and Richard Solomon, principal product manager and vice-president of PCI-SIG, discussing the pivotal role of PCIe 7.0 in enabling high-performance computing, AI clusters, and next-gen chip designs. This session will explore

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Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library

Webinar: Simplifying Interface Protocol Verification with Veloce Transactor Library
by Admin on 03-27-2025 at 1:04 pm

As hyperscaler chiplet and SoCs grow in complexity, integrating and validating multiple high-speed and low-speed interface protocols—such as PCIe, CXL, UCIe, AMBA, AXI, AHB, CHI, CSI2, and DSI2, can be a significant challenge. Design Verification Engineers and Technical Managers must ensure seamless protocol compliance

Read More

Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction

Upcoming Webinar: Accelerating Semiconductor Design with Generative AI and High-Level Abstraction
by Daniel Nenni on 03-27-2025 at 10:00 am

RDA SemiWikiblog graphic

We have been hearing so much lately about the power of AI and the potential of technologies like agentic AI to address the productivity gap and complexities of semiconductor designs of today and tomorrow.  Currently, however, the semiconductor industry has been slow to adopt generative and agentic AI for RTL design code.   There… Read More