Webinar: Securing Post-Quantum Implementations Against Physical Attacks

Webinar: Securing Post-Quantum Implementations Against Physical Attacks
by Admin on 06-26-2025 at 7:59 pm

Description

We’ll dive into one of the most pressing questions in the community:

Are physical attacks practical against post-quantum schemes in the real world? If yes, how to harden the code or the hardware?

We’ll explore:

How can cryptographic algorithms and their implementations be targeted by physical attacks?

Leveraging… Read More

Webinar: What it really takes to build a future-proof AI architecture?

Webinar: What it really takes to build a future-proof AI architecture?
by Admin on 06-26-2025 at 7:54 pm

Abstract

As AI workloads increasingly dominate numerous cloud and edge applications, building a scalable, efficient, and future-ready AI chips is no longer optional—it’s essential. This webinar explores the latest AI trends, highlighting the growing demand for intelligent processing closer to the data source and

June 13, 2025June 18, 2025

WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs

WEBINAR Unpacking System Performance: Supercharge Your Systems with Lossless Compression IPs
by Daniel Nenni on 06-13-2025 at 8:00 am
Categories: CAST, Events, IP

In today’s data-driven systems—from cloud storage and AI accelerators to automotive logging and edge computing—every byte counts. The exponential growth in data volumes, real-time processing demands, and constrained bandwidth has made efficient, lossless data compression a mission-critical requirement. Software-based… Read More

Webinar: Data Center RAS in the Age of AI Computing

Webinar: Data Center RAS in the Age of AI Computing
by Admin on 06-12-2025 at 1:57 pm

Thursday, July 10, 2025

10:00am PDT | 1:00pm EDT | 19:00 CEST

As AI revolutionizes industries, the demand for high-performance, low power computing intensifies, placing unprecedented requirements on data centers. This panel will explore the transformative impact of AI processing on data center reliability, availability,… Read More

Essential Debugging Techniques Workshop

Essential Debugging Techniques Workshop
by Admin on 06-12-2025 at 1:48 pm

Essential Debugging Techniques Workshop

This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado

Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques

Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques
by Admin on 06-12-2025 at 1:45 pm

Description

Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx… Read More

From Theory to Practice: Applying Timing Constraints Workshop

From Theory to Practice: Applying Timing Constraints Workshop
by Admin on 06-12-2025 at 1:42 pm

From Theory to Practice: Applying Timing Constraints Workshop

Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices.

This… Read More

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration

Webinar: Exploring AMD Kria SOM for ROS 2 Multi-Node Communications with TSN Acceleration
by Admin on 06-12-2025 at 1:40 pm

Description

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for your applications. In this session, you’ll explore the TSN-ROS application and its role in enhancing communications… Read More

Achieving Timing Closure in FPGA Designs Workshop

Achieving Timing Closure in FPGA Designs Workshop
by Admin on 06-12-2025 at 1:37 pm

Achieving Timing Closure in FPGA Designs Workshop

Do you find it challenging to close timing in your FPGA design? This workshop will guide you through leveraging AMD Vivado’s tools, optimizing your design, and applying best practices for static timing analysis to achieve reliable timing closure.

Gain hands-on experience … Read More

Webinar: Getting Started with the Vitis Unified IDE

Webinar: Getting Started with the Vitis Unified IDE
by Admin on 06-12-2025 at 1:33 pm

Description

BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar.

When it comes to embedded software development, managing multiple tools, maintaining version control, and navigating complex workflows can feel overwhelming. The AMD Vitis™ Unified IDE simplifies the process… Read More