Featured Speaker:
In this Synopsys webinar, Intel will present how its disaggregated designs across client and server platforms have driven the evolution of robust 3D multi-die design construction and signoff methodologies. Intel will share practical experience using Synopsys’
In this webinar, Intel will present how EMIB-T (Embedded Multi-die Interconnect Bridge with TSVs) enables compact, cost-effective multi‑die design while sustaining the bandwidth and power efficiency required for AI and datacenter designs. Intel will share a production-oriented EMIB-T reference methodology built … Read More
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Full-chip SoC debug has become one of the most expensive bottlenecks in modern verification. A single production issue can pull multiple engineers away days as they chase a failure through waveforms, logs, and across hundreds of thousands of lines of code.
In this webinar, we will demonstrate… Read More
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Embedded systems programs rarely fail because any one team lacks capability. They fail because critical engineering artifacts drift out of alignment over time and distance.
This includes requirements, architecture, implementation, verification, hardware bring-up, firmware,… Read More
As power integrity challenges increase with advanced nodes and multi-die architectures, EMIR analysis must evolve beyond traditional signoff. In this Synopsys webinar, we will show how RedHawk-SC is expanding its capabilities not only to enhance EMIR analysis, but also to enable IR-aware Static Timing Analysis (IR-STA) … Read More
Dive into the future of Bluetooth audio with Ceva and Dolphin Semiconductor’s breakthrough 12nm Smart Edge AIoT SoC solution.
This webinar shows how advanced wireless connectivity, integrated AI processing, and premium audio technologies and power management come together to deliver superior performance, lower
As semiconductor complexity increases and board designs become denser, manufacturing teams face tighter tolerances, reduced test access, and rising pressure to maintain yield and throughput. Validating RF performance and high-speed digital signal integrity at production scale adds a new layer of complexity that traditional… Read More
AI data center networks now operate at a scale where device-level validation no longer reflects real performance. Engineers must understand how systems behave under realistic traffic conditions, not just in isolated tests.
Join Ram Periakaruppan, vice president and general manager of network applications and security at… Read More
As systems move into higher frequencies and wider bandwidths, small measurement errors can lead to costly design decisions. Engineers working in wireless, radar, satellite, and optical domains must now validate signals that push existing tools to their limits.
Join Jun Chie, Vice President of Product Management at Keysight,… Read More
Data rates have doubled, but validation methods have not kept pace. As PCIe, DDR, and multi-terabit optical interconnects evolve, engineers are encountering signal integrity challenges much earlier in the design process.
Join Niels Fache, Senior Vice President and General Manager of Design Engineering Software at Keysight,… Read More
