A few times a year, I check in with AMIQ EDA co-founder Cristian Amitroaie to see what’s new with their company and the integrated development environment (IDE) market for hardware design and verification. Usually he suggests a topic for us to discuss, but this time I specifically wanted to learn more about the version of their Design… Read More
Tag: verilog
Sigasi September Productivity Hacks Workshop
Sigasi Studio serves as a code browser for VHDL, Verilog and SystemVerilog. You can navigate through your project to understand large and complex legacy designs. Visuals of your code update instantly and are cross-linked to your code to allow graphical
Verific Sharpening the Saw
Verific is an unusual company. They are completely dominant in what they do – providing parsers for Verilog/SV, VHDL and UPF. Yet they have no ambition to expand beyond that goal. Instead, per Michiel Ligthart (President and COO), they continue to “sharpen the saw”. This is an expression I learned in sales training, habit #7 from… Read More
Why I made the world’s first on-demand formal verification course
Verification Challenge
As chip design complexity continues to grow astronomically with hardware accelerators running riot with the traditional hardware comprising CPUs, GPUs, networking and video and vision hardware, concurrency, control and coherency will dominate the landscape of verification complexity for safe … Read More
Introduction to Visualizer for the Verilog Users
Register For This Web Seminar
8:00 AM – 9:00 AM US/Pacific
Overview
Complex testing and methodology with complex silicon require powerful but simple to use debug solutions. The Visualizer Debug Environment provides a common debug solution for simulation, emulation and other engines,
Webinar: Designing Complex SoCs and Dealing with Multiple File Formats
In SoC design it’s all about managing complexity through modeling, and the models that make up IC designs come in a wide range of file formats like:
- Transistor-level , SPICE
- Interconnect parasitics, SPEF
- Gate and RTL, Verilog, VHDL
Even with standard file formats, designers still have to traverse the hierarchy to find out… Read More
Foundational Excellence in a Laid-Back Style
I recently had a call with Rob Dekker, Founder and CTO of Verific. If you’re in EDA or semiconductor CAD, chances are high that you know who they are. They’re king of the hill in parser software for SystemVerilog and VHDL. When you hear a line like that, you assume a heavy dose of marketing spin, but here it really is fact. I don’t know of… Read More
Design Automation and the Engineering Workstation
This is the seventeenth in the series of “20 Questions with Wally Rhines”
Several common aspects have existed for what is now the modern Electronic Design Automation (EDA) industry. When I joined TI in 1972, the company was very proud of its design automation capability as a competitive differentiator. Much of the… Read More
CEO Interview: Cristian Amitroaie of AMIQ EDA
AMIQ EDA has caught my attention over the last few months. My first impression was that this was just another small IDE company trying to compete with established and bundled IDEs from the big 3, a seemingly insurmountable barrier. This view was challenged by an impressive list of testimonials, not just from the little guys but also… Read More
Why Open and Supported Interfaces Matter
Back in the early 1980’s during the nascent years of electronic design automation (EDA), I worked at Texas Instruments supporting what would become their merchant ASIC business. Back then, life was a bit different. The challenge we faced was to make our ASIC library available on as many EDA flows as we could to give as many users as… Read More