Webinar Offers View into TSMC IP Design Methodology

Webinar Offers View into TSMC IP Design Methodology
by Tom Simon on 10-21-2016 at 12:00 pm

Standard cell and memory IP are key enablers for new process node availability. These two items must be in place early and be completely ready for a process node to scale to volume. Development of both leaves no room for error and they require the highest performance possible. Foundries are extremely focused on this and spend a lot… Read More


TSMC and Solido to Share Experiences with Managing Variation in Webinar

TSMC and Solido to Share Experiences with Managing Variation in Webinar
by Tom Simon on 09-10-2016 at 7:00 am

TSMC knows better than anyone the effect that variation can have at advanced process nodes. Particularly in memory designs and in standard cell designs, variation has become a very critical because of its effects on yield and because of the high-cost of compensating for it. Smaller feature sizes combined with lower voltage thresholds… Read More


Statistical Simulation Provides Insight into 6T SRAM Optimization

Statistical Simulation Provides Insight into 6T SRAM Optimization
by Tom Simon on 08-24-2016 at 12:00 pm

ARM’s Azeez Bhavnagarwala recently gave a talk hosted by Solido on the benefits of variation aware design in optimizing 6T bit cells. Azeez sees higher clock rates, increasing usage of SRAM per processor and the escalating number of processors, shown in the diagram below, as trends that push designers toward 6T. Six Transistor… Read More


Solido Saves Silicon with Six Sigma Simulation

Solido Saves Silicon with Six Sigma Simulation
by Tom Simon on 08-16-2016 at 4:00 pm

When pushing the boundaries of power and performance in leading edge memory designs, yield is always an issue. The only way to ensure that memory chips will yield is through aggressive simulation, especially at process corners to predict the effects of variation. In a recent video posted on the Solido website, John Barth of Invecas… Read More


TSMC Update at #53DAC!

TSMC Update at #53DAC!
by Daniel Nenni on 05-31-2016 at 4:00 pm

TSMC is having an interesting year for sure. I was at the TSMC Symposium in Hsinchu last week and everyone was talking about the new 16FFC process. Silicon is out and it is exceeding expectations leading some people (me included) to believe that TSMC 16FFC will be the next TSMC 28nm in regards to popularity. To be clear, 16FFC is currently… Read More


How TSMC Tackles Variation at Advanced Nodes

How TSMC Tackles Variation at Advanced Nodes
by Pawan Fangaria on 05-27-2016 at 12:00 pm

The design community is always hungry for high-performance, low-power, and low-cost devices. There is emergence of FinFET and FDSOI technologies at ultra-low process nodes to provide high-performance and low-power requirements at lower die-size. However, these advanced process nodes are prone to new sources of variation.… Read More


TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes

TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
by Daniel Nenni on 05-10-2016 at 12:00 pm

Being that TSMC and Solido are founding members of SemiWiki, you should be able find out everything you ever wanted to know on their respective landing pages. If not, just ask a question in the SemiWiki forum and I can assure you it will be answered in great detail. And here are some other interesting 2015 factoids from Solido:… Read More


Variation Aware FinFETs are Critical!

Variation Aware FinFETs are Critical!
by Daniel Nenni on 12-18-2015 at 4:00 pm

As I mentioned in “EDA Dead Pool” acquisitions in our industry will continue at a rapid pace. The latest victim is 10 year old French company Infiniscale who was recently purchased by Silvaco. This was more of a “let’s put your product through our massive sales and support channel” kind of deal so it will be 1 + 1 = 3 accretive for sure.… Read More


Moving with Purpose for Certainty

Moving with Purpose for Certainty
by Pawan Fangaria on 11-01-2015 at 12:00 pm

In 1492 Christopher Columbus sailed from Spain towards west on Atlantic Ocean in search of Asia and Indies. Between his four voyages (1492 – 1502) he discovered many different islands and then what we call Americas. Although he had a compass with him, imagine searching a needle in a haystack. Even with localization of areas and then… Read More


Solidly Across the Chasm

Solidly Across the Chasm
by Paul McLellan on 10-05-2015 at 12:00 pm

Last week I wrote about EDA companies crossing the chasm, with Jim Hogan (who needs no introduction) and Amit Gupta, CEO of Solido. So how did those rules work out for Solido?

See also Getting EDA Across the Chasm: 15 Rules Before and 5 After

The founding team of Solido:

  • discovered process variation for analog was a problem as companies
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