TSMC ♥ Oasys

TSMC ♥ Oasys
by Paul McLellan on 01-31-2013 at 8:05 pm

Oasys has joined the TSMC Soft-IP Alliance Program. This means that TSMC IP partners have access to a new RTL exploration tool to improve QoR and reduce the iterations needed for design closure. In modern process nodes, RTL engineers implementing complex IP cores for graphics, networking, and mobile computing are struggling … Read More


How We Got Here…

How We Got Here…
by Paul McLellan on 01-22-2013 at 12:54 pm

Over at the GSA Forum website I have an article on the history of the semiconductor industry. It is actually based on a couple of brief history of semiconductor blogs (here and here) I published here on SemiWiki last year but edited down a lot and tightened up.

Since the start of the year seems to be the time for predictions, here are the… Read More


Semiconductor Packaging (3D IC) Emerging As Innovation Enabler!

Semiconductor Packaging (3D IC) Emerging As Innovation Enabler!
by Daniel Nenni on 01-29-2012 at 4:00 pm

The ASIC business is getting more and more complicated. The ability to produce innovative die at a competitive price to solve increasingly complex problems just isn’t enough. The technology required to package that die is now front and center.

Here, at the junction of advanced design, process technology and state-of-the art … Read More


Silicon IP to take over CAE in EDAC results… soon but not yet!

Silicon IP to take over CAE in EDAC results… soon but not yet!
by Eric Esteve on 07-20-2011 at 11:44 am

Very interesting results launched by EDAC for Q1 2011, if Computer Aided Engineering (CAE) is still the largest category with $530.6M, the second category is Silicon IP (SIP) with $371.4M, followed by IC Physical Design & Verification at $318.5M. Even more significant is the four quarter moving average results, showing … Read More