Webinar on TFT and FPD Design

Webinar on TFT and FPD Design
by Daniel Payne on 05-11-2017 at 12:00 pm

I knew that the acronym for TFT meant Thin Film Transistors, but I hadn’t heard that FPD stands for Flat Panel Detectors. It turns out the FPD are solid-state sensors used in x-ray applications, similar in operation to image sensors for digital photography and video. I’ll be attending and blogging about what I learn… Read More


Approaches for EM, IR and Thermal Analysis of ICs

Approaches for EM, IR and Thermal Analysis of ICs
by Daniel Payne on 04-26-2017 at 12:10 pm

As an engineer I’ve learned how to trade off using various EDA tools based on the accuracy requirements and the time available to complete a project. EDA vendors have been offering software tools to help us with reliability concerns like EM, IR drop and thermal analysis for several years now. Last week I attended a webinar … Read More


The Importance of EM, IR and Thermal Analysis for IC Design – Webinar

The Importance of EM, IR and Thermal Analysis for IC Design – Webinar
by Daniel Payne on 04-17-2017 at 4:00 pm

Designing an IC has both a logical and physical aspect to it, so while the logic in your next chip may be bug-free and meet the spec, how do you know if the physical layout will be reliable in terms of EM (electro-migration), IR (voltage drops) and thermal issues? EDA software once again comes to our rescue to perform the specific type… Read More


Analyzing All of those IC Parasitic Extraction Results

Analyzing All of those IC Parasitic Extraction Results
by Daniel Payne on 03-30-2017 at 12:00 pm

Back at DAC in 2011 I first started to hear about this EDA company named edXact that specialized in reducing and analyzing IC parasitic extraction results. So Silvaco acquired edXact and I wanted to get an update on what is new with their EDA tools that help help you to analyze and manage the massive amount of extracted RLC and even K … Read More


What You Don’t Know about Parasitic Extraction for IC Design

What You Don’t Know about Parasitic Extraction for IC Design
by Daniel Payne on 02-23-2017 at 7:00 am

Out of college my first job was doing circuit design at the transistor-level with Intel, and to get accurate SPICE netlists for simulation we had to manually count the squares of parasitic interconnect for diffusion, poly-silicon and metal layers. Talk about a burden and chance for mistakes, I’m so thankful that EDA companies… Read More


CEO Interview: David Dutton of Silvaco

CEO Interview: David Dutton of Silvaco
by Daniel Nenni on 01-30-2017 at 7:00 am

Silvaco has undergone one of the most impressive EDA transformations so it was a pleasure to interview the man behind it. David Dutton’s 30+ year career started at Intel, Maxim, and Mattson Technology where he led the company’s turnaround and finished as President, CEO, and board member. David joined Silvaco as CEO… Read More


TCAD Simulation of Organic Optoelectronic Devices

TCAD Simulation of Organic Optoelectronic Devices
by Daniel Payne on 01-20-2017 at 4:00 pm

In my office there are plenty of LED displays for me to look at throughout the day: three 24″ displays from Viewsonic, a 15″ display from Apple, an iPad, a Samsung Galaxy Note 4, a Nexus tablet, a Garmin 520 bike computer, and a temperature display. LED and OLED displays are ubiquitous in all sorts of consumer electronics,… Read More


It’s Better than SUPREM for 3D TCAD

It’s Better than SUPREM for 3D TCAD
by Daniel Payne on 12-06-2016 at 12:00 pm

Process and device engineers have a tough task to model and simulate an IC process prior to fabricating silicon, however this approach is much better than the alternative choice in the 1970’s of just running multiple lots of wafers and then making measurements to see if your node was meeting specifications. Out of Stanford… Read More


It’s Time to Put Your Spice Netlists on a Diet

It’s Time to Put Your Spice Netlists on a Diet
by Tom Dillinger on 06-28-2016 at 7:00 am

Spice circuit simulation remains the backbone of IC design validation. Digital cell library developers rely upon Spice for circuit characterization, to provide the data for Liberty models. Memory IP designers utilize additional Spice features to perform statistical sampling. Analog and I/O interface designers extend these… Read More


My #53DAC Must See List!

My #53DAC Must See List!
by Daniel Nenni on 06-04-2016 at 7:00 am

It may be hard to believe but this happens to be my thirty third Design Automation Conference. Where does the time go? Three of my kids are out of college and the last one is getting close. That is where my time has gone. The conference itself started in 1964 but my first one was in 1984 in Albuquerque, New Mexico. In fact, that was the year… Read More