The semiconductor industry is entering a transformative era, and few trends are generating more discussion or confusion than Agentic AI. From autonomous design exploration to next-generation verification strategies, Agentic AI promises dramatic changes in how chips are conceived, validated, and delivered. But as with … Read More
Daniel is joined by Luca TESTA, the COO and co-founder of Keysom. After studying microelectronics in Italy, Luca obtained his PhD in France while working with STMicroelectronics on analog/RF circuit design.
Dan explores the charter and focus of Keysom with Luca. Luca describes how Keysom is providing an automated and reliable… Read More
*Work Email Required*
Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an overview of IP architecture and integration methodologies that support… Read More
Key Takeaways
– High-Level Synthesis (HLS) delivers not only design productivity and quality but also dramatic gains in verification speed and debug – and it delivers them today.
– Rise Design Automation uniquely enables SystemVerilog-based HLS and SystemVerilog verification, reusing proven verification… Read More
An engineering change order, or ECO in the context of ASIC design is a way to modify or patch a design after layout without needing to re-implement the design from its starting point. There are many reasons to use an ECO strategy. Some examples include correcting errors that are found in post-synthesis verification, optimizing … Read More
This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.
The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More
Functional ECO (Engineering Change Order) continues to pose a persistent challenge for ASIC designers. To address this, Easy-Logic Technology, in collaboration with SemiWiki, is launching a webinar series focused on tackling ECO challenges across various ASIC design segments—starting with Mixed-Signal ASICs.
After being held in San Francisco since the pandemic the beloved Design Automation Conference will be on the move again. In 2026 DAC will be held in Huntington Beach. For you non-California natives, Huntington Beach is a California city Southeast of Los Angeles. It’s known for surf beaches and its long Huntington Beach Pier.… Read More
In this episode of the Semiconductor Insiders video series, Dan is joined by Dr Greg Law, CEO of Undo, He is a C++ debugging expert, well-known conference speaker, and the founder of Undo. Greg explains the history of Undo, initially as a provider of software development and debugging tools for software vendors. He explains that… Read More
A recent survey of more than 120 anonymous semiconductor professionals offers a grounded view of how the industry is evaluating non-volatile memory (NVM) technologies—and where things may be heading next.
The 2024 NVM Survey, run in late 2024 and promoted through various semiconductor-related platforms and portals including… Read More
