Tag: rfic

Reimagining Custom Design with AI-Powered Virtuoso Studio

Reimagining Custom Design with AI-Powered Virtuoso Studio
by Admin on 08-21-2025 at 2:22 am

Join us for an in-person seminar to explore the future of custom design and migration with AI-powered Virtuoso Studio. Discover how the latest innovations from Cadence are transforming analog, custom, RFIC, and MMIC design. Learn how these advancements enable faster, smarter insight analysis and more precise workflows using

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Revolutionizing RFIC Design: Introducing RFIC-GPT

Revolutionizing RFIC Design: Introducing RFIC-GPT
by Jason Liu on 02-28-2024 at 6:00 am
Categories: EDA

Figure1 (10)

In the rapidly evolving world of Radio Frequency Integrated Circuits (RFIC), the challenge has always been to design efficient, high-performance components quickly and accurately. Traditional methods, while effective, come with a high complexity and a lengthy iteration process. Today, we’re excited to unveil RFIC-GPT… Read More

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Best Practices are Much Better with Ansys Cloud and HFSS

Best Practices are Much Better with Ansys Cloud and HFSS
by Daniel Nenni on 02-04-2021 at 6:00 am
Categories: Ansys, Inc., EDA

Ansys PAM4 PKG

Compute environments have advanced significantly over the past several years. Microprocessors have gotten faster by including more cores, available RAM has increased significantly, and the cloud has made massive distributed computing more easily and cheaply available.

HFSS has evolved to take advantage of these new capabilities,… Read More

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At Last, Package and Chip integration for RF Design

At Last, Package and Chip integration for RF Design
by Tom Simon on 01-21-2019 at 7:00 am
Categories: Cadence, EDA

It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro … Read More

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RFIC Design Challenges at #50DAC

RFIC Design Challenges at #50DAC
by Daniel Nenni on 05-31-2013 at 8:00 pm
Categories: Uncategorized

RFIC developers used to favor mature silicon processes, typically staying back a couple of nodes behind the leading edge. This bought foundries time for ‘RF-enabling’ their PDKs, and also maximized return on investment for developing RF models and infrastructure IP. Not the case any more, it seems. To address the insatiable … Read More