SoC Sign-off, Real Intent at DAC

SoC Sign-off, Real Intent at DAC
by Daniel Payne on 06-09-2013 at 8:10 pm

Monday morning at DAC I met with Real Intent to get an update on their SoC sign-off tools:

  • Dr. Prakash Narain, President and CEO
  • Graham Bell, Sr. Dir. Mktg.

Years ago Prakash was at IBM the only two years that they attended DAC, in an attempt to offer their internal EDA tools to the EDA marketplace. Graham worked at Nassda marketing the… Read More


At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT

At DVCon: Pre-Simulation Verification for RTL Sign-Off includes Automating Power Optimization and DFT
by Graham Bell on 02-24-2013 at 8:10 pm

By now, you will have seen several postings about all the different activities that are going on at Design and Verification Conference being held Feb. 25-28 at its usual location – the DoubleTree Hotel in San Jose, CA. Besides organizing an experts panel “Where Does Design End and Verification Begin?“, Real… Read More


Clock Domain Crossing (CDC): Survey Says

Clock Domain Crossing (CDC): Survey Says
by Paul McLellan on 03-06-2012 at 11:30 pm

I had no idea that there was a clock domain crossing (CDC) linkedIn group but indeed there is. Richard Brabant has set up a survey to see which tools people are using.


The graph is somewhat confusing since, for example, Cadence Conformal is currently at zero but has a significant looking bar. But far and away the market leader (in this… Read More