We still don’t know the precise status about a potential acquisition of Arteris by Qualcomm, and I prefer not to comment a rumor and wait for the official announcement, if any. But I would like to comment … a comment about this rumor, recently made by Sonics. This comment has taken the form of an Open Letter, from “Grant Pierce, CEO of… Read More
I just read this very interesting article posted by Kurt Shuler from Arteris, describing the “History of SoC Interconnect Fabric” and explaining why the SC industry needs an advanced approach, named the “fourth phase of the Interconnect Fabric history” in the article. Kurt’s point of view is that in the past the SoC interconnect… Read More
As an Oakland Raider season ticket holder I attend as many Raider home games as possible. If you have ever attended a live sporting event at a large stadium, and you travelled by car, you are probably familiar with the traffic problems that occur at the end of the game when everyone wants to leave the stadium parking lot at the same time.… Read More
I remember during my first ten years as a software developer, I used many different computers such as IBM mainframes, Apollo and Sun workstations, and VAX computers. During that time I also bought my first home computer, a Macintosh. I didn’t of course think of this at the time, but the one thing they all had in common was that they did… Read More
The news from Arteris, Inc., announcing that “its interconnect fabric IP has been licensed and deployed in a majority of chips developed by China’s leading semiconductor companies for applications including consumer electronics, smartphones, and tablets,” is holding attention for several reasons. At first, because it’s… Read More
Everyone understands that as we increasingly focus on the design of mobile devices, there is an increasing focus on low power. But, what is implied in designing for low-power? Designing for low power means we have to work with multiple power domains and multiple clock domains—making our design task more complex. We also must get… Read More
Just as important as block RAMs, IO and DSP48’s is what interconnect or fabric is going to be used when considering SoC FPGA designs. I think Xilinx has found the winning combination. What is paramount to the new SoC FPGA methodologies is not only the challenge of moving huge amounts of data around; we are now to consider data… Read More
I never understood when I was a kid how ‘the Blob’ could actually catch someone but it sure did. It caught the unsuspecting, the off guard. I mean you’d have time for a soda and shower if you saw it on your road. And no, your manager is not the Blob; don’t think like that, it’s always his boss. The blob comes to consume the worker who was unaware… Read More
Recently Bill Dally, nVidia’s Chief Scientist & SVP of Research, and a professor of electrical engineering and computer science at Stanford University, has been out speaking quite a bit including a “short keynote” at the Design Automation Conference and a keynote at ISC 2013. The DAC audience is primarily EDA tool users and… Read More
Application Processor SoC integrates more and more functions, generation after generation, challenging performance, cost, power efficiency, reliability, and time-to-market. But the maximum die size can’t increase, at least because of the constraints linked with wafer production, manufacturability, yield and finally… Read More
