Most of us understand the basic concept of a virtual channel: mapping multiple channels of traffic, possibly of mixed priority, to a single physical link. Where priority varies, quality of service (QoS) settings can help ensure higher priority traffic flows unimpeded. SoC designers can capture the benefits of virtual channels… Read More
Tag: network on chip
How to Overcome NoC Validation Multiple Challenges?
NetSpeed has developed NocStudio, a front end optimization design tool helping architects to create SoC architecture bridging the gap with the back end, floor planning and place and route. At the chip level, NocStudio generates a cache-coherent Network-on-Chip (NoC) allowing interconnecting the various CPU, GPU or Acceleration… Read More
Last line of defense for IoT security
If I grab 10 technologists and ask what are the most important issues surrounding the Internet of Things today, one of the popular answers will be “security.” If I then ask them what IoT security means, I probably get 10 different answers. Encryption. Transport protocols. Authentication. Keying. Firewalls. Secure boot. Over-the-air… Read More
Opportunity NoCs, But Not Without Software
It is easy to think that semiconductor IP is all about structures on the silicon. After all, there is “semiconductor” in the phrase “semiconductor IP”. But increasingly the heart is actually software. Sonics’ SGN product is a network-on-chip but to build it you need to use the software that actually… Read More
Is Interconnect Ready for the Post-mobile SoCs?
The interconnect technology is one of the unsung heroes of the system-on-chip (SoC) revolution. It’s the on-chip networking fabric that is used to link various IP cores on an SoC floorplan. The technology facilitates links between multiple processors, on-chip memories, hardware accelerators and more. In other words,… Read More
Is Low Power a Challenge? ICE-Grain Answers the Challenge
Blogs have limited wordcount so insert your own generic opening paragraph here about the importance of low power in IC design. Mention IoT and cloud datacenters for extra credit.
It is well-known that the biggest reductions in power come from changes at the architectural level. Tools and process can do some things and since they… Read More
Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design
China was a virgin territory for Arteris Inc. before July 19, 2012 when Fuzhou Rockchip Electronics announced that it has licensed the Arteris FlexNoC network-on-chip (NoC)-based interconnect IP technology for its multicore SoCs for budget Android tablets. Rockchip mostly targets the tablet and set-top box (STB) markets … Read More
SystemC Co-Simulation of NoCs and IP Blocks
Verification in general suffers from a couple of fundamental problems. Availability of models and performance of different levels of representation.
The first problem, availability of models, is that you would like to start verification as soon as possible but all the representations are not ready early enough. Obviously … Read More
eSilicon Just Taped-out a SonicsGN-based SoC. And It’s Not a Secret
I slipped into the shadows at the back of the bar in the Tenderloin. Mid-afternoon on a weekday, almost nobody in there.
“So you’re with the NSA?” I asked.
“I can’t confirm that,” the man said.
“The Network Stealing Agency.”
“That’s not what it stands for,” he said indignantly. “It’s the National Security Agency. We ensure…well, … Read More
Using NoCs to Reduce Power
Earlier this week I moderated a webinar at Sonics entitled NoC 102: Using SonicsGN to Address Low Power Requirements. Drew Wingard, the CTO of Sonics, presented it. It goes without saying that power is a major concern in SoC design, not just with chips for battery powered devices but also tethered devices. A major cost of ownership… Read More