Webinar: RISC-V system debug & analysis made easy with Lauterbach TRACE32 and Tessent Embedded Analytics

Webinar: RISC-V system debug & analysis made easy with Lauterbach TRACE32 and Tessent Embedded Analytics
by Admin on 09-27-2024 at 2:34 am

Processor trace gives software developers access to critical insights and forensic capabilities to manage the risk of building embedded systems. In this presentation, Siemens and Lauterbach will give an overview of how processor trace can be used to improve embedded software and applications. We will explain the RISC-V Efficient

Read More

Emulation from In Circuit to In Virtual

Emulation from In Circuit to In Virtual
by Bernard Murphy on 11-08-2018 at 7:00 am

At a superficial level, emulation in the hardware design world is just a way to run a simulation faster. The design to be tested runs on the emulator, connected to whatever test mechanisms you desire, and the whole setup can run many orders of magnitude faster than it could if the design was running inside a software simulator. And … Read More


Virtual Emulation Extends Debugging Over Physical

Virtual Emulation Extends Debugging Over Physical
by Pawan Fangaria on 12-13-2014 at 7:30 am

Amid burgeoning complexity of SoC verification with ever increasing hardware, software and firmware content, verification engineers are hard pressed with learning multiple tools, technologies and methodologies and still completing SoC verification with full accuracy in time. The complexity, size and diversity of SoC … Read More